JP4249691B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor equipment, the method of manufacturing a semiconductor equipment embedded with a memory cell and a logic circuit, particularly one substrate.

  In a semiconductor device in which a dynamic random access memory (DRAM) and a logic circuit are mixedly mounted, a metal silicide film is formed on the source / drain regions and the gate electrode of the MISFET in the logic circuit portion in order to improve the performance of the logic circuit.

  In a semiconductor device such as a DRAM, it is preferable to reduce the junction leakage current of the source / drain region in order to improve the data retention characteristics of the memory cell. However, when a metal silicide film is formed on the surface of the source / drain region, the junction leakage current increases (Meeting the Electrochemical Society P218-220). For this reason, in the manufacture of a DRAM, a metal silicide film is usually not formed.

In a semiconductor device in which a DRAM and a logic circuit are mixedly mounted, it is desired to form a metal silicide only in the logic circuit part without forming a metal silicide in the DRAM part.
In the DRAM portion, normally, the gate electrode of the MISFET constituting each memory cell is formed integrally with the word line. The word line is formed of polysilicon or the like, and it is preferable that the polysilicon constituting the word line is doped with impurities at a high concentration in order to reduce the resistance. On the other hand, in the logic circuit section, a preferable impurity concentration is determined from the threshold value of the MISFET. The preferred impurity concentrations of the gate electrode of the memory cell portion and the gate electrode of the logic circuit portion do not necessarily match.

  When a capacitor used in an analog circuit is formed in the logic circuit portion, it is desired to increase the accuracy of the capacitance of the capacitor. For this reason, usually, a three-layer structure of polysilicon film / silicon oxide film / polysilicon film is taken. In order to reduce the voltage dependency of the capacitor, it is preferable to increase the impurity concentration of the polysilicon film. In order to suppress an increase in manufacturing cost, it is desired to suppress an increase in manufacturing steps for forming a high concentration polysilicon film as much as possible.

  A method is known in which only the memory cell portion is formed first and then the logic circuit portion is formed. When the bit line is arranged under the cell plate which is a common electrode of the capacitor constituting each memory cell, the end of the bit line is connected to the edge of the cell plate in order to connect the bit line and the logic circuit wiring. It is necessary to put it outside. Therefore, a process for removing the interlayer insulating film deposited on the logic circuit portion when forming the memory cell and a process for patterning the cell plate must be performed separately.

An object of the present invention is to suppress an increase in the number of manufacturing steps is to provide a manufacturing how a semiconductor device embedded with DRAM and a logic circuit capable of forming a capacitor in the logic circuit portion.

  According to one aspect of the present invention, a step of preparing a semiconductor substrate in which a memory cell portion and a logic circuit portion are defined in a main surface, and an insulating material is formed on a partial region of the main surface of the semiconductor substrate. Forming an element isolation structure and defining an active region; forming a first gate insulating film on a region of the main surface of the semiconductor substrate where the element isolation structure is not formed; and Forming a first conductive film on the element isolation structure and the first gate insulating film; removing a portion of the first conductive film on the memory cell portion; and Forming a capacitive insulating film on the surface of the conductive film, forming a second conductive film on the capacitive insulating film and on the semiconductor substrate, and patterning the second conductive film. And leaving the upper electrode above the element isolation structure In addition, a step of leaving a plurality of word lines also serving as gate electrodes above the memory cell portion, and patterning the capacitor insulating film and the first conductive film, leaving a lower electrode made of the first conductive film. The lower electrode is left in a shape in which the lower electrode includes the upper electrode as viewed from the normal direction of the semiconductor substrate, and the first conductive film is formed on the active region of the logic circuit portion. There is provided a method for manufacturing a semiconductor device, including a step of leaving a gate electrode and leaving the capacitive insulating film between the upper electrode and the lower electrode.

  The upper electrode of the capacitor and the word line are formed at the same time, and the lower electrode and the gate electrode of the logic circuit portion are formed at the same time. For this reason, a capacitor can be formed while suppressing an increase in the number of steps.

  According to the present invention, the lower electrode of the capacitor formed in the logic circuit portion is formed simultaneously with the gate electrode of the MISFET of the logic circuit portion, and the upper electrode is formed simultaneously with the word line of the memory cell portion. For this reason, the increase in the number of processes can be suppressed.

  A first embodiment of the present invention will be described with reference to FIGS. 1 to 4 are sectional views of a substrate for explaining a method of manufacturing a semiconductor device according to the first embodiment. In each figure, the left side of the cut portion shows the memory cell portion, and the right side shows the n-channel MISFET formation region of the logic circuit portion.

The steps up to FIG. 1A will be described. A shallow trench type element isolation structure 2 is formed on the surface of the p-type silicon substrate 1 by a known method. The element isolation structure 2 defines an active region 3 in the memory cell array portion and an active region 4 in the logic circuit portion. A gate oxide film 7 having a thickness of 5 to 10 nm made of SiO ₂ is formed on the surfaces of the active regions 3 and 4 by thermal oxidation. A polysilicon film 8 having a thickness of 100 to 250 nm is deposited on the gate oxide film 7. The polysilicon film 8 is deposited by chemical vapor deposition (CVD) using, for example, SiH ₄ .

The first phosphorus (P) ion implantation is performed on the polysilicon film 8 under conditions of an acceleration energy of 10 to 30 keV and a dose of 3 to 6 × 10 ¹⁵ cm ⁻² . At this time, the p-channel MISFET formation region (not shown) of the logic circuit portion is covered with a resist pattern.

As shown in FIG. 1B, the surface of the polysilicon film 8 in the logic circuit portion is covered with a resist pattern 5. Under the conditions of acceleration energy of 10 to 30 keV and dose of 5 to 8 × 10 ¹⁵ cm ⁻² , second ion implantation of P is performed on the polysilicon film 8 in the memory cell portion. After the ion implantation, the resist pattern 5 is removed.

As shown in FIG. 1C, the polysilicon film 8 is patterned to leave a plurality of word lines 8a in the memory cell portion and leave a gate electrode 8b in the logic circuit portion. The polysilicon film 8 can be etched by, for example, reactive ion etching (RIE) using a mixed gas of Cl ₂ and O ₂ . The word line 8a extends in a direction perpendicular to the paper surface of FIG. Two word lines 8 a pass over one active region 3. A word line 8 a is also formed on the element isolation structure 2 on both sides of the active region 3. The word line 8 a on the active region 3 also serves as a gate electrode of a MISFET formed in the active region 3.

Impurities are ion-implanted using the word line 8a and the gate electrode 8b as a mask. P is ion-implanted into the MISFET formation region of the memory cell portion under conditions of acceleration energy of 10 to 30 keV and a dose of 1 to 5 × 10 ¹³ cm ⁻² . In the n channel MISFET formation region of the logic circuit portion, P is ion-implanted under conditions of acceleration energy of 5 to 30 keV and a dose of 1 to 5 × 10 ¹³ cm ⁻² , and As is further accelerated energy of 5 to 30 keV and a dose of 1 Ion implantation is performed under conditions of ˜50 × 10 ¹³ cm ⁻² . By this ion implantation, the source / drain region 9a of the MISFET is formed in the memory cell portion, and the low concentration region 9b of the source / drain region having a low concentration drain (LDD) structure is formed in the logic circuit portion.

  By adding As to the low concentration region 9b of the MISFET in the logic circuit portion, a high-performance MISFET can be obtained. By adding only P without adding As to the source / drain region 9a of the MISFET in the memory cell portion, a leak current can be reduced and a DRAM with good refresh characteristics can be obtained.

The steps up to FIG. 2A will be described. A SiO ₂ film having a thickness of 80 to 120 nm is deposited on the entire surface of the substrate. The SiO ₂ film is deposited by CVD using SiH ₄ and O ₂ , for example. The memory cell portion is covered with a resist pattern 11, and the SiO ₂ film in the logic circuit portion is anisotropically etched. The sidewall insulating film 10b remains on the side wall of the gate electrode 8b of the logic circuit portion, and the SiO ₂ film 10a remains in the memory cell portion. The resist pattern 11 is removed.

Next, ion implantation for forming source / drain regions is performed in the logic circuit portion. In the n channel MISFET formation region, As is ion-implanted under the conditions of an acceleration energy of 30 to 40 keV and a dose of 2 to 4 × 10 ¹⁵ cm ⁻² , and boron (B) is implanted into the p channel MISFET formation region with an acceleration energy of 5 Ion implantation is performed under conditions of ˜15 keV and a dose of 2-4 × 10 ¹⁵ cm ⁻² . Note that at any ion implantation, the memory cell portion is covered with a resist pattern. By this ion implantation, the high concentration region 12b of the source / drain region of the LDD structure is formed. After ion implantation, the natural oxide film on the silicon surface is removed using hydrofluoric acid.

As shown in FIG. 2B, a cobalt silicide (CoSi ₂ ) film 15 is formed on the surfaces of the gate electrode 8b and the high concentration region 12b. Hereinafter, a method of forming the CoSi ₂ film 15 will be described. First, a Co film is deposited by sputtering or the like so as to cover the entire surface of the substrate. A first heat treatment is performed at a substrate temperature of 450 to 550 ° C., and then a second heat treatment is performed at a substrate temperature of 800 to 900 ° C. The silicon surface and the Co film undergo a silicide reaction, and a CoSi ₂ film 15 is formed. The excess Co film that did not undergo the silicide reaction is removed using hydrofluoric acid. In this way, the CoSi ₂ film 15 can be formed in a self-aligned manner only on the surface where Si is exposed.

Since the surfaces of the source / drain regions 9a and the word lines 8a in the memory cell portion are covered with the SiO ₂ film 10a, no silicide reaction occurs in this portion. Since the high concentration region 12b of the source / drain region of the logic circuit portion is in contact with the Co film, a silicide reaction occurs at this interface. In addition to Co, other metals that cause a silicide reaction with Si to form metal silicide, such as Ti, may be used.

As shown in FIG. 2C, a borophosphosilicate glass (BPSG) film 18 having a thickness of 800 to 1200 nm covering the entire surface of the substrate is deposited. The BPSG film 18 is deposited by CVD using a mixed gas of SiH ₄ , B ₂ H ₆ , O ₂ and PH ₃ as a source gas. After heat treatment at a substrate temperature of 700 to 850 ° C., the surface is flattened by chemical mechanical polishing (CMP).

A contact hole 19 exposing the surface of the central source / drain region 9a in the active region 3 is opened. The BPSG film 18 is etched by RIE using a mixed gas of CF ₄ , CHF _3, and Ar. A bit line 20 connected to the central source / drain region 9a through the contact hole 19 is formed. The bit line 20 extends in a direction orthogonal to the word line 8a in a portion other than the cross section shown in FIG.

Hereinafter, a method of forming the bit line 20 will be described. A polysilicon film having a thickness of 50 nm to which P is added and a tungsten silicide (WSi) film having a thickness of 100 nm are deposited so as to cover the entire surface of the substrate. The polysilicon film is deposited by CVD using SiH ₄ as a source gas, and the WSi film is deposited by CVD using WF ₆ and SiH ₄ as source gases. Note that the natural oxide film formed on the bottom surface of the contact hole 19 may be removed using hydrofluoric acid before the polysilicon film is deposited.

The polysilicon film and the WSi film are patterned to form the bit line 20. Etching of the polysilicon film and the WSi film is performed by RIE using Cl ₂ and O ₂ .
As shown in FIG. 2D, a BPSG film 23 having a thickness of 800 to 1200 nm covering the entire surface of the substrate is deposited. After heat treatment at a substrate temperature of 700 to 850 ° C., the surface is flattened by CMP.

  Contact holes 24 that expose the surfaces of the source / drain regions 9a at both ends of the active region 3 are opened. For each contact hole 24, a storage electrode 25 connected to the source / drain region 9a through the contact hole 24 is formed. The storage electrode 25 is formed by depositing a polysilicon film having a thickness of 300 to 800 nm to which P is added and then patterning the polysilicon film.

As shown in FIG. 3, a silicon nitride (SiN) film having a thickness of 3 to 5 nm is deposited to cover the entire surface of the substrate. This SiN film is thermally oxidized at a temperature of 700 to 800 ° C. to form a capacitive insulating film 28 made of SiON. A counter electrode 29 made of polysilicon doped with P and having a thickness of 100 nm is formed so as to cover the capacitor insulating film 28. The capacitive insulating film 28 and the counter electrode 29 other than the memory cell array portion are removed. The two layers are etched by RIE using Cl ₂ and O ₂ .

As shown in FIG. 4, a BPSG film 30 having a thickness of 1000 to 1500 nm covering the entire surface of the substrate is deposited. A contact hole 32 for exposing a part of the surface of the counter electrode 29 and a part of the surface of the CoSi ₂ film 15 of the logic circuit portion is formed. Although not shown in FIG. 4, a contact hole that exposes a part of the surface of the bit line 20 is formed at the same time.

  The contact hole 32 is filled with a W plug 35. Hereinafter, a method for forming the W plug 35 will be described. First, a barrier metal layer is deposited by sputtering. The barrier metal layer has, for example, a two-layer structure of a Ti film and a TiN film. A W film having a thickness of 300 to 500 nm is deposited on the barrier metal layer by CVD to fill the contact hole 32. The excess W film and the barrier metal layer are removed by CMP, and the W plug 35 is left only in the contact hole 32.

  A wiring 40 is formed on the BPSG film 30. The wiring 40 has a laminated structure including a barrier metal layer, an aluminum (Al) film, and an antireflection film. The antireflection film is made of, for example, TiN.

A SiO ₂ film 41 is deposited on the BPSG film 30 so as to cover the wiring 40. The SiO ₂ film 41 is deposited by, for example, CVD using high density plasma. A contact hole is opened in the SiO ₂ film 41 and the inside is filled with a W plug 42. A wiring 43 is formed on the surface of the SiO ₂ film 41, and a SiO ₂ film 44 covering the wiring 43 is deposited.

A cover film 45 covering the SiO ₂ film 44 is deposited. The cover film 45 has a two-layer structure of an SiO ₂ film by plasma CVD and an SiN film by plasma CVD.
In the first embodiment, the first ion implantation shown in FIG. 1A and the second ion shown in FIG. 1B are injected into the gate electrode of the MISFET of the memory cell portion, that is, the word line 8a. Is done. On the other hand, only the first ion implantation shown in FIG. 1A is performed on the gate electrode 8b of the n-channel MISFET in the logic circuit portion.

  In the ion implantation process for forming the source / drain regions described with reference to FIGS. 1C and 2A, the gate electrode and the word line are used as a mask. At this time, impurities are additionally implanted into the word line 8a and the gate electrode 8b. The impurity concentration of the gate electrode of the MISFET in the memory cell portion and the logic circuit portion is determined by appropriately selecting the dose amount of the first and second ion implantations in consideration of the amount of impurities to be additionally implanted. Each can be set within a suitable range.

FIG. 5A is a graph showing the relationship between the amount of impurities implanted into the gate electrode and the drain current when a voltage of 2.5 V is applied to the gate electrode. The horizontal axis represents the amount of impurity implantation into the gate electrode in the unit of “× 10 ¹⁵ cm ⁻² ”, and the vertical axis represents the drain current as a relative value, where 100 is the sample showing the maximum drain current. The thickness of the gate electrode was 180 nm, the implanted impurity was P, and the acceleration energy of ion implantation was 20 keV. Further, the impurity implantation amount into the channel region was adjusted so that the threshold voltage was 0.45V.

The maximum drain current is obtained when the impurity implantation amount is about 4 × 10 ¹⁵ cm ⁻² . When the implantation amount is larger than this, the drain current decreases. This is because the impurity concentration of the channel region needs to be increased as the impurity concentration of the gate electrode increases in order to prevent the threshold value from decreasing. If the impurity concentration of the gate electrode is too low, the gate electrode is depleted and the characteristics of the MISFET are degraded. Therefore, it is preferable that the amount of impurities implanted into the gate electrode is about 4 × 10 ¹⁵ cm ⁻² .

FIG. 5B is a graph showing the relationship between the amount of impurities implanted into the gate electrode and the sheet resistance of the gate electrode. The horizontal axis represents the amount of impurity implantation into the gate electrode in the unit “× 10 ¹⁵ cm ⁻² ”, and the vertical axis represents the sheet resistance in the unit “Ω / □”. Note that the thickness of the gate electrode, implanted impurities, and acceleration energy are the same as in the case of (A). The sheet resistance required for the word line of DRAM is usually 80Ω / □ or less. In order to satisfy this requirement, the amount of impurities implanted into the gate electrode may be about 1 × 10 ¹⁶ cm ⁻² .

  5A and 5B, it can be seen that the impurity implantation amount required for the gate electrode of the logic circuit portion is different from the impurity implantation amount required for the word line of the memory cell portion. As in the first embodiment, the first ion implantation is performed on the entire polysilicon film 8, and the second ion implantation is performed only on the polysilicon film 8 in the memory cell section. An appropriate amount of impurities can be implanted into both the electrode and the word line of the memory cell portion.

In the first embodiment, the memory cell portion is covered with the SiO ₂ film 10a during the silicide reaction step shown in FIG. 2B. Therefore, metal silicide can be prevented from being formed on the surface of the source / drain region of the memory cell portion. As a result, good data retention characteristics can be ensured.

  Next, a second embodiment will be described with reference to FIGS. In the second embodiment, a capacitor is formed in the logic circuit section. 6 and 7, the diagram on the right side of the cut portion in each drawing shows the memory cell portion, and the diagram on the left side shows the logic circuit portion.

  Processes up to the state shown in FIG. An element isolation structure 51 is formed on the surface of the p-type silicon substrate 50, and active regions are defined in the memory cell portion and the logic circuit portion. A gate oxide film 52 having a thickness of 5 to 10 nm is formed on the surface of the active region by thermal oxidation. A first conductive film 53 made of polysilicon and having a thickness of 100 to 250 nm is deposited on the entire surface of the substrate by CVD. Note that the first conductive film 53 may be formed of amorphous silicon instead of polysilicon.

In the first conductive film 53, P ions are implanted into the n-channel MISFET formation region and the capacitor formation region of the logic circuit portion. The implantation conditions are, for example, an acceleration energy of 20 keV and a dose amount of 3-6 × 10 ¹⁵ cm ⁻² . Note that P and As may be implanted so that the total dose amount is 3 to 6 × 10 ¹⁵ cm ⁻² . Boron (B) is ion-implanted into the p-channel MISFET formation region of the logic circuit portion. It is not always necessary to implant impurities into the p-channel MISFET formation region. A p-type impurity is implanted into the gate electrode of the p-channel MISFET simultaneously with the ion implantation for forming the source / drain regions. After the ion implantation, activation annealing is performed.

After the activation annealing, the first conductive film 53 in the memory cell portion is removed. The removal of the first conductive film 53 is performed by RIE using a mixed gas of Cl ₂ and O ₂ . After the patterning of the first conductive film 53, the gate oxide film 52 remaining on the surface of the memory cell portion and the natural oxide film formed on the surface of the first conductive film 53 are removed with hydrofluoric acid.

  As shown in FIG. 6B, the surface of the active region of the memory cell portion is thermally oxidized to form a second gate oxide film 55 having a thickness of 5 to 10 nm. At the same time, the surface layer of the first conductive layer 53 is also oxidized to form a capacitive insulating film 56 having a thickness of 10 to 30 nm.

  As shown in FIG. 6C, a polysilicon film 60, a tungsten silicide (WSi) film 61, and a first SiN film 62 are deposited in this order on the entire surface of the substrate by CVD. The polysilicon film 60 has a thickness of 50 to 100 nm and is doped with P to impart n-type conductivity. The thicknesses of the WSi film 61 and the first SiN film 62 are both 100 to 200 nm.

As shown in FIG. 7A, the three layers from the first SiN film 62 to the polysilicon film 60 are patterned to leave the word line 65 in the memory cell portion, and in the capacitor formation region of the logic circuit portion, the capacitor is formed. The upper electrode 66 is left. Both the word line 65 and the capacitor upper electrode 66 have a three-layer structure including a polysilicon film 60, a WSi film 61, and a first SiN film 62. The first SiN film 62 is etched by RIE using a mixed gas of CF ₄ , CHF ₃ and Ar, and the WSi film 61 is etched by RIE using a mixed gas of Cl ₂ and O _2. The polysilicon film 60 is etched by RIE using a mixed gas of Cl ₂ and O ₂ .

P is ion-implanted into the memory cell portion under the conditions of acceleration energy of 10 to 30 keV and dose of 2 to 5 × 10 ¹³ cm ^{−2 using} the word line 65 as a mask. Source / drain regions 67 are formed on both sides of the word line 65 in the memory cell portion.

A sidewall insulating film 68 made of SiN is formed on the side walls of the word line 65 and the capacitor upper electrode 66. The sidewall insulating film 68 is formed by depositing a SiN film on the entire surface of the substrate and anisotropically etching the SiN film. This anisotropic etching is performed by RIE using a mixed gas of CF ₄ , CHF ₃ and Ar. At this time, the capacitor insulating film 56 in the region where the capacitor upper electrode 66 is not formed in the upper surface of the first conductive film 53 is also removed, and the upper surface of the first conductive film 53 is exposed.

As shown in FIG. 7B, the first conductive film 53 is patterned, the capacitor lower electrode 53a is left in the region including the capacitor upper electrode 66 when viewed from the substrate normal direction, and the n channel of the logic circuit portion is formed. The gate electrode 53b is left in the MISFET formation region. Although not shown in the figure, the gate electrode is also left in the p channel MISFET formation region. The first conductive film 53 is etched by RIE using a mixed gas of Cl ₂ and O ₂ . The sidewall insulating film 68 remaining on the side wall of the first conductive film 53 may remain without being removed. In such a case, when the first conductive film 53 is etched, the vicinity of the edge may be covered with a mask pattern, and the first conductive film 53 may be positively left in that portion.

As ions are implanted into the n-channel MISFET formation region of the logic circuit portion using the gate electrode 53b as a mask to form a low concentration region of the LDD structure. The ion implantation conditions are an acceleration energy of 5 to 15 keV and a dose of 1 to 10 × 10 ¹³ cm ⁻² . Similarly, B ions are implanted into the p-channel MISFET formation region. The ion implantation conditions are an acceleration energy of 5 to 15 keV and a dose of 1 to 10 × 10 ¹³ cm ⁻² .

A SiO ₂ film is deposited on the entire surface of the substrate and anisotropic etching is performed to leave the sidewall insulating film 70b on the sidewall of the gate electrode 53b. At this time, the sidewall insulating film 70a remains on the sidewall of the capacitor lower electrode 53a, and the sidewall insulating film 70d remains on the slope of the sidewall insulating film 68. Further, in the memory cell portion, the region between the word lines 65 are embedded in the buried insulating member 70c made of SiO _2.

As ions are implanted into the n-channel MISFET formation region of the logic circuit portion using the gate electrode 53b and the sidewall insulating film 70b as a mask to form a high concentration region of the LDD structure. The ion implantation conditions are an acceleration energy of 30 to 40 keV and a dose of 2 to 4 × 10 ¹⁵ cm ⁻² . Similarly, B ions are implanted into a p-channel MISFET formation region (not shown). The ion implantation conditions are an acceleration energy of 5 to ¹⁵ keV and a dose of 2 to 4 × 10 ¹⁵ cm ⁻² . After the ion implantation, activation annealing is performed to form the source / drain regions 71 having the LDD structure.

As shown in FIG. 7C, a CoSi ₂ film 72 is formed on the upper surfaces of the source / drain regions 71 of the MISFET and the gate electrode 53b in the logic circuit portion. The CoSi ₂ film 72 is formed by the same method as the formation of the CoSi ₂ film 15 described with reference to FIG. 2B of the first embodiment. At this time, since the surface of the source / drain region 67 of the memory cell portion is covered with the buried insulating member 70 c, no CoSi ₂ film is formed on the surface of the source / drain region 67.

  A logic circuit-embedded DRAM including a capacitor including the capacitor lower electrode 53a, the capacitor insulating film 56, and the capacitor upper electrode 66 is formed through the same process as the process after FIG. 2C of the first embodiment.

In the second embodiment, similarly to the first embodiment, the metal silicide film can be formed only in the logic circuit portion without forming the metal silicide film in the memory cell portion. Further, in the second embodiment, the upper electrode 66 of the capacitor is formed in the same process as the word line 65 of the memory cell part, and the lower electrode 53a is formed in the same process as the gate electrode 53b of the logic circuit part. Therefore, a capacitor having a polysilicon film / SiO ₂ film / polysilicon film structure can be formed while suppressing an increase in the number of steps as much as possible.

  Further, as shown in FIG. 7C, the side and upper side of the word line 65 are covered with a sidewall insulating film 68 and a first SiN film 62 made of SiN. When the contact hole 19 shown in FIG. 2C and the contact hole 24 shown in FIG. 2D are formed under the condition that SiN is not substantially etched, the sidewall insulating film 68 and the first SiN are formed. The film 62 serves as a protective film for the WSi film 61 and the polysilicon film 60. For this reason, the contact holes 19 and 24 can be formed in a self-aligning manner.

The side wall insulating film 70b on the sidewalls of the gate electrode 53b of the logic circuit portion is formed of SiO _2. For this reason, the hot carrier resistance of the MISFET can be increased and the parasitic capacitance can be reduced as compared with the case where the sidewall insulating film is formed of SiN. Further, since the sidewall insulating film 70b is formed in a process different from the sidewall insulating film 68 of the memory cell portion, the thickness of the sidewall insulating film 70b is set to an optimum value for suppressing the short channel effect. It becomes possible.

Next, a third embodiment will be described with reference to FIGS. 8 and 9, the diagram on the right side of the cut portion of each figure represents the memory cell unit, and the diagram on the left side represents the logic circuit unit.
FIG. 8A shows a state corresponding to FIG. 1C of the first embodiment. The difference from the first embodiment is that an upper SiO ₂ film 80 having a thickness of about 100 nm is arranged on the word line 8a. Hereinafter, the process up to FIG. 8A will be described by focusing on the difference from the process up to FIG. 1C of the first embodiment.

On a substrate forming an isolation structure 2 is deposited a polysilicon film and the SiO ₂ film and the SiO ₂ film is removed in the logic circuit area. The polysilicon film is ion-implanted in the same manner as in the first embodiment. After removing the SiO ₂ film in the logic circuit portion, the same process as in the first embodiment is performed, and the state shown in FIG. 8A is reached.

  In the third embodiment, after ion implantation for forming the low concentration region 9b of the MISFET in the logic circuit portion, ion implantation for forming the source / drain region 9a in the memory cell portion is performed.

Steps similar to those up to the step of forming the CoSi ₂ film 15 shown in FIG. 2B of the first embodiment are performed.
As shown in FIG. 8B, a CoSi ₂ film 15 is formed on the upper surface of the gate electrode 8b of the logic circuit portion and on the upper surface of the high concentration region 12b of the source / drain region. The memory cell portion is covered with the SiO ₂ film 10a. The thickness of the SiO ₂ film 10a is 50 to 120 nm.

As shown in FIG. 8C, a low temperature formed SiO ₂ film 81 having a thickness of 20 to 50 nm is deposited on the entire surface of the substrate. The low temperature formed SiO ₂ film 81 is deposited by CVD with a growth temperature of 700 ° C. or lower. For example, the SiO ₂ film 81 is deposited by plasma CVD at a substrate temperature of about 400 ° C. By depositing at a low temperature, the CoSi ₂ film 15 can be prevented from being deteriorated by heat.

As shown in FIG. 9A, the SiO ₂ film 10a and the low-temperature formed SiO ₂ film 81 are anisotropically etched to form on the side wall of the laminated structure including the word line 8a of the memory cell portion and the upper SiO ₂ film 80. The sidewall insulating film 82 is left. At this time, the logic circuit portion is covered with a resist pattern. The low temperature formed SiO ₂ film 81 remains in the logic circuit portion.

A P-doped amorphous silicon film having a thickness of 100 to 200 nm is deposited on the entire surface of the substrate by CVD. This amorphous silicon film is patterned to leave a pad 83 corresponding to the source / drain region 9a of the memory cell portion. The pad 83 covers from the surface of the source / drain region 9 a to a part of the upper surface of the upper SiO ₂ film 80 via the side surfaces of the sidewall insulating films 82 on both sides thereof.

  As shown in FIG. 9B, a BPSG film 18 is deposited on the entire surface of the substrate, a contact hole 19 is opened, and a bit line 20 is formed. The steps so far are the same as the steps described with reference to FIG. 2C of the first embodiment.

  As shown in FIG. 9C, a BPSG film 23 is deposited on the entire surface of the substrate, a contact hole 24 is opened, and a storage electrode 25 is formed. The steps up to here are the same as those described with reference to FIG. 2D of the first embodiment.

  In the case of the third embodiment, when the contact holes 19 and 24 shown in FIGS. 9B and 9C are opened, the pads 83 are exposed on the bottom surfaces thereof. Since the source / drain region 9a is not directly exposed to the etching atmosphere, it is possible to prevent a defect from occurring in the source / drain region 9a. For this reason, it is possible to prevent deterioration of data retention characteristics of the DRAM due to defects in the source / drain region 9a.

  In the first to third embodiments, the case where the MISFET of the memory cell portion and the MISFET of the logic circuit portion are formed substantially in parallel has been described. As a method of manufacturing a DRAM in which a logic circuit is embedded, a method for forming a source / drain region of a MISFET in a logic circuit part after forming all parts up to the counter electrode (for example, the counter electrode 29 in FIG. 3) of the memory cell part. It has been known. In the case of this method, it becomes a problem how to connect the bit line of the memory cell portion and the wiring of the logic circuit portion. The fourth and fifth embodiments described below are characterized by this connection configuration.

A fourth embodiment will be described with reference to FIG. 10A and 10B are cross-sectional views of a boundary region between the memory cell portion and the logic circuit portion.
As shown in FIG. 10A, the MISFET 91, the word line 92, the interlayer insulating film 98, the bit line 93, the interlayer insulating film are formed in the memory cell portion of the silicon substrate 90 (the region on the almost right half of FIG. 10A). 99, a storage electrode 94, a capacitor insulating film 95, and a counter electrode 96 are formed. The configuration so far is formed by the same method as the steps from FIG. 1A to FIG. 3 of the first embodiment. However, in the logic circuit portion, only the gate electrode is formed, ion implantation for forming the high concentration region 12b of the source / drain region shown in FIG. 2A, and the CoSi ₂ film 15 shown in FIG. 2B. Is not formed. In the logic circuit portion, a gate electrode 100 and a sidewall insulating film 101 disposed on the sidewall are formed. The interlayer insulating films 98 and 99 and the counter electrode 96 are also formed on the logic circuit portion.

  A resist pattern 97 is formed to cover the surface of the counter electrode 96 in the memory cell portion. The edge of the resist pattern 97 is arranged closer to the logic circuit portion by about 0.2 μm than the tip of the bit line 93. Using the resist pattern 97 as a mask, the counter electrode 96 deposited on the logic circuit portion is removed. The counter electrode 96 is removed by isotropic etching using a chlorine-based gas.

  The counter electrode 96 is side-etched, and the edge of the counter electrode 96 recedes from the edge of the resist pattern 97. The depth of side etching is about 1 to 1.5 μm. That is, the edge of the counter electrode 96 recedes from the tip of the bit line 93 by about 0.8 to 1.3 μm.

  After the counter electrode 96 is removed, the interlayer insulating films 99 and 98 in the logic circuit portion are removed using the resist pattern 97 as a mask. The interlayer insulating films 99 and 98 are removed by anisotropic RIE. In order to stop the anisotropic RIE etching with good reproducibility, the surfaces of the gate electrode 100, the sidewall insulating film 101, and the silicon substrate 90 may be covered with a thin SiN film. In the case of covering with an SiN film, the SiN film is removed after the interlayer insulating films 99 and 98 are removed.

  P ions are implanted into the logic circuit portion using the gate electrode 100 and the sidewall insulating film 101 as a mask. The ion implantation conditions are the same as the ion implantation conditions for forming the high concentration region 12b shown in FIG. 2A of the first embodiment. After the ion implantation, the resist pattern 97 is removed.

  As shown in FIG. 10B, an interlayer insulating film 105 made of BPSG is deposited on the entire surface of the substrate, and the surface is flattened by CMP. A contact hole 106 exposing the upper surface of the bit line 93 is formed in the interlayer insulating film 105. The contact hole 106 is disposed closer to the logic circuit portion than the edge of the counter electrode 96. Since the edge of the counter electrode 96 is set back about 0.8 to 1.3 μm from the tip of the bit line 93, the contact hole 106 can be formed without contacting the counter electrode 93.

In the logic circuit portion, a wiring 107 is formed on the interlayer insulating film 105. The wiring 107 is connected to the bit line 93 through the contact hole 106.
In the fourth embodiment, the edge of the counter electrode 96 is defined by side etching, and a dedicated photomask for defining the edge of the counter electrode 96 is not used. That is, the edge of the counter electrode 96 can be defined by using only the resist pattern 97 for defining the boundary line between the memory cell portion and the logic circuit portion.

  Next, a fifth embodiment will be described with reference to FIG. As shown in FIG. 11A, a DRAM circuit is formed in the memory cell portion of the silicon substrate 90. The configuration is the same as that of the DRAM circuit shown in FIG. 10A of the fourth embodiment.

  The element isolation structure 110 defines a boundary between the memory cell portion and the logic circuit portion. A connection wiring 111 is formed on the surface of the element isolation structure 110 so as to correspond to the bit line 93. The connection wiring 111 is formed in the same process as the formation of the word line 92. Each bit line 93 is connected to the corresponding connection wiring 110 through a contact hole formed in the interlayer insulating film 98 in the vicinity of the tip thereof.

  The surface of the counter electrode 96 in the memory cell portion is covered with a resist pattern 97. Using the resist pattern 97 as a mask, the counter electrode 96 and the interlayer insulating films 99 and 98 in the logic circuit portion are removed. A part of the connection wiring 111 is exposed in the logic circuit portion. The surfaces of the gate electrode 100, the sidewall insulating film 101, and the connection wiring 111 may be covered with a SiN film, and this SiN film may be used as an etching stop layer. Similar to the process of FIG. 10A of the fourth embodiment, P ions are implanted into the logic circuit section.

  As shown in FIG. 11B, an interlayer insulating film 105 made of BPSG is deposited on the entire surface of the substrate, and the surface is flattened by CMP. A contact hole 106 that exposes the upper surface of the connection wiring 111 is formed in the interlayer insulating film 105. The contact hole 106 is disposed closer to the logic circuit portion than the edge of the counter electrode 96. Since the connection wiring 111 extends to the logic circuit portion, the contact hole 106 can be formed without contacting the counter electrode 93.

  In the logic circuit portion, a wiring 107 is formed on the interlayer insulating film 105. The wiring 107 is connected to the bit line 93 through the contact hole 106 and the connection wiring 111.

  In the case of the fifth embodiment, the wiring 107 and the bit line 93 are connected through the connection wiring 111. Therefore, as in the case of the fourth embodiment, the wiring 107 and the bit line 93 can be connected with high reproducibility only by using the resist pattern 97 that defines the boundary between the logic circuit portion and the memory cell portion. it can.

Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.
The invention shown in the following supplementary notes is derived from the above embodiments.

(Supplementary Note 1) A MISFET formed on the surface of a semiconductor substrate and including a gate electrode disposed on a source / drain region and a channel region therebetween,
A covering insulating member made of an insulating material covering an upper surface and side surfaces of the gate electrode;
A conductive pad disposed so as to cover the side surface of the covering insulating member from the upper surface of the source / drain region;
An interlayer insulating film disposed on the semiconductor substrate so as to cover the pad and the MISFET;
A contact hole formed in the interlayer insulating film, the contact hole disposed so that the contact hole is included in the pad when viewed from the normal direction of the substrate;
A semiconductor device having a capacitor formed on the interlayer insulating film and having one electrode connected to the pad through the contact hole.

(Additional remark 2) The process of preparing the semiconductor substrate by which the memory cell part and the logic circuit part were demarcated in the main surface,
Forming a DRAM circuit on a memory cell portion of the semiconductor substrate, wherein the DRAM circuit includes a plurality of memory cells and bit lines each of which is a set of a MISFET and a capacitor, and one electrode of the capacitor is The bit line is connected to one of the source / drain regions of the corresponding MISFET, and the other one of the source / drain regions of the MISFETs of some memory cells is connected to each other. Extends to the vicinity of the boundary line between the memory cell portion and the logic circuit portion, and the other counter electrode of the capacitor is disposed above the bit line and connected to each other between the plurality of capacitors. The line and the MISFET are insulated by a first interlayer insulating film, and the bit line and the capacitor are insulated by a second interlayer insulating film, Counter electrode, wherein the first and second interlayer insulating film forming a DRAM circuit disposed in the logic circuit portion,
A step of covering a region of the surface of the counter electrode above the memory cell portion with a resist pattern, the step of covering the edge of the resist pattern so as to be positioned closer to the logic circuit portion than the tip of the bit line When,
Using the resist pattern as a mask, the counter electrode is isotropically etched to remove the counter electrode on the logic circuit portion until the edge of the counter electrode recedes from the tip of the bit line Side-etching the counter electrode;
Etching the first and second interlayer insulating films using the resist pattern as a mask, and removing the first and second interlayer insulating films on the logic circuit portion;
Covering the entire surface of the semiconductor substrate with a third interlayer insulating film;
Forming a contact hole in the third interlayer insulating film, wherein the contact hole is disposed closer to the logic circuit part than an edge of the counter electrode, and exposes a part of the bit line; Forming a hole;
Forming a wiring on the third insulating film, the wiring being connected to the bit line through the contact hole and extending to the logic circuit portion; A method for manufacturing a semiconductor device.

(Additional remark 3) The semiconductor substrate by which the memory cell part and the logic circuit part were demarcated in the main surface,
An element isolation structure formed in a boundary region between the memory cell portion and the logic circuit portion of the semiconductor substrate;
A connection wiring disposed on the element isolation structure;
A DRAM circuit formed on a memory cell portion of the semiconductor substrate, wherein the DRAM circuit includes a plurality of memory cells and bit lines each consisting of a set of a MISFET and a capacitor, and one electrode of the capacitor is The bit line is connected to one of the source / drain regions of the corresponding MISFET, the other of the source / drain regions of the MISFET of some memory cells is connected to each other, and the memory cell The DRAM circuit extending to the vicinity of the boundary line between the circuit portion and the logic circuit portion, disposed in an upper layer than the connection wiring, and connected to the connection wiring;
An interlayer insulating film that covers the DRAM circuit and also covers the logic circuit part;
A contact hole formed in the interlayer insulating film and having a part of an upper surface of the connection wiring as a bottom surface;
A semiconductor device having an upper layer wiring disposed on the interlayer insulating film, connected to the connection wiring through the contact hole, and extending to the logic circuit portion.

It is sectional drawing (the 1) of the board | substrate for demonstrating the manufacturing method of the semiconductor device by the 1st Example of this invention. FIG. 6 is a cross-sectional view of the substrate for explaining the method of manufacturing the semiconductor device according to the first embodiment of the present invention (No. 2). FIG. 6 is a sectional view (No. 3) of the substrate for explaining the method of manufacturing the semiconductor device according to the first embodiment of the invention. FIG. 6 is a sectional view (No. 4) of the substrate for explaining the manufacturing method of the semiconductor device according to the first embodiment of the invention; FIG. 5A is a graph showing the relationship between the amount of impurity implanted into the gate electrode of the MISFET and the drain current, and FIG. 5B shows the relationship between the amount of impurity implanted into the gate electrode and the sheet resistance. It is a graph. It is sectional drawing (the 1) of the board | substrate for demonstrating the manufacturing method of the semiconductor device by the 2nd Example of this invention. It is sectional drawing (the 2) of the board | substrate for demonstrating the manufacturing method of the semiconductor device by the 2nd Example of this invention. It is sectional drawing (the 1) of the board | substrate for demonstrating the manufacturing method of the semiconductor device by the 3rd Example of this invention. It is sectional drawing (the 2) of the board | substrate for demonstrating the manufacturing method of the semiconductor device by the 3rd Example of this invention. It is sectional drawing of the board | substrate for demonstrating the manufacturing method of the semiconductor device by the 4th Example of this invention. It is sectional drawing of the board | substrate for demonstrating the manufacturing method of the semiconductor device by the 5th Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation structure 3, 4 Active region 7 Gate oxide film 8 Polysilicon film 8a Word line 8b Gate electrode 9a Source / drain region 9b Low concentration region 10a SiO ₂ film 10b Side wall insulating film 11 Resist pattern 12b High Concentration region 15 CoSi ₂ film 18 BPSG film 19 Contact hole 20 Bit line 24 Contact hole 25 Storage electrode 28 Dielectric film 29 Counter electrode 35, 42 W plug 40, 43 Wiring 41, 44 SiO ₂ film 45 Cover film 50 Silicon substrate 51 Element isolation structure 52 Gate oxide film 53 First conductive film 55 Second gate oxide film 56 Capacitance insulating film 60 Polysilicon film 61 WSi film 62 First SiN film 65 Word line 66 Capacitor upper electrode 67 Source / drain region 68 sidewall insulating film 70a, 0b, 70d sidewall insulating film 70c buried insulating member 71 source / drain regions 72 CoSi ₂ film 80 upper SiO ₂ film 81 formed at a low temperature SiO ₂ film 82 sidewall insulating film 83 pad 90 silicon substrate 91 MISFET
92 Word line 93 Bit line 94 Storage electrode 95 Capacitance insulating film 96 Counter electrode 97 Resist pattern 98, 99 Interlayer insulating film 100 Gate electrode 101 Side wall insulating film 105 Interlayer insulating film 106 Contact hole 107 Wiring 111 Connection wiring

Claims (4)

Preparing a semiconductor substrate in which a memory cell portion and a logic circuit portion are defined in a main surface;
Forming an element isolation structure made of an insulating material on a partial region of the main surface of the semiconductor substrate and defining an active region;
Forming a first gate insulating film on a region of the main surface of the semiconductor substrate where the element isolation structure is not formed;
Forming a first conductive film on the element isolation structure and the first gate insulating film;
Removing a portion of the first conductive film on the memory cell portion;
Forming a capacitive insulating film on the surface of the first conductive film;
Forming a second conductive film on the capacitive insulating film and on the semiconductor substrate;
Patterning the second conductive film, leaving an upper electrode above the element isolation structure, and leaving a plurality of word lines also serving as gate electrodes above the memory cell portion;
Patterning the capacitive insulating film and the first conductive film to leave a lower electrode made of the first conductive film, the lower electrode including the upper electrode as viewed from the normal direction of the semiconductor substrate Leaving the lower electrode in shape, leaving the gate electrode made of the first conductive film on the active region of the logic circuit portion, and leaving the capacitive insulating film between the upper electrode and the lower electrode; A method for manufacturing a semiconductor device. After the step of removing the first conductive film on the memory cell portion and before the step of forming the capacitive insulating film, a step of removing the first gate insulating film on the memory cell portion Including
2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the capacitive insulating film further includes a step of forming a second gate insulating film on a region of the memory cell portion in the main surface of the semiconductor substrate. . A step of forming a first sidewall insulating film on the side wall of the gate electrode of the logic circuit portion and embedding a space between the word lines of the memory cell portion with an embedded insulating member made of an insulating material;
Implanting impurities into the substrate surface layer on both sides of the gate electrode of the logic circuit portion;
The method of manufacturing a semiconductor device according to claim 1, further comprising: forming a metal silicide film on the upper surface of the gate electrode of the logic circuit portion and on the semiconductor substrate surface on both sides thereof. After the step of forming the second conductive film, further comprising the step of depositing an upper insulating film made of an insulating material having an etching resistance different from that of the embedded insulating member on the second conductive film,
In the step of patterning the second conductive film, the upper insulating film is patterned to be the same pattern as the second conductive film,
After the step of leaving the word line, further comprising a step of forming a second sidewall insulating film made of an insulating material having an etching resistance different from that of the buried insulating member on the side wall of the word line;
4. The method of manufacturing a semiconductor device according to claim 3 , wherein the embedded insulating member embeds between the second sidewall insulating films disposed on each of the opposing side walls of the word lines adjacent to each other.

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