[go: up one dir, main page]

JP4244096B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP4244096B2
JP4244096B2 JP2000113772A JP2000113772A JP4244096B2 JP 4244096 B2 JP4244096 B2 JP 4244096B2 JP 2000113772 A JP2000113772 A JP 2000113772A JP 2000113772 A JP2000113772 A JP 2000113772A JP 4244096 B2 JP4244096 B2 JP 4244096B2
Authority
JP
Japan
Prior art keywords
semiconductor
substrate
electrode
semiconductor device
resin layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000113772A
Other languages
Japanese (ja)
Other versions
JP2001298050A (en
Inventor
隆一 佐原
和美 渡瀬
憲幸 戒能
賢治 植田
康司 竹村
哲正 丸尾
信弥 松村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2000113772A priority Critical patent/JP4244096B2/en
Publication of JP2001298050A publication Critical patent/JP2001298050A/en
Application granted granted Critical
Publication of JP4244096B2 publication Critical patent/JP4244096B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、情報通信機器、事務用電子機器等に利用される半導体画像センサーを内蔵し、さらに外部端子との接続配線などを有し、高密度実装が可能な実装を可能とした半導体装置に関するものである。本発明の半導体装置により、情報通信機器、事務用電子機器等の小型化を容易にするものである。
【０００２】
【従来の技術】
近年、半導体装置およびその製造方法は電子機器の小型化、高機能化に伴い、小型化、高密度化を要求されるようになり、たとえばＣＣＤやＣＭＯＳセンサーといった画像センサーが開発されている。
【０００３】
以下、従来の画像センサーと呼ばれる半導体装置およびその製造方法について断面図を参照にしながら説明する。
【０００４】
図６は、従来の画像センサーと呼ばれる半導体装置を示す断面図である。図６において１０１は半導体チップまたは半導体ウエハー、１０２は半導体ウエハー１０１上に形成された画素部、１０３は電極パッド、１０４は封止樹脂、１０５はリードフレーム、１０６はダイスボンド材、１０７はＡｕ線、１０８は封止用のガラスプレートである。
【０００５】
同図に示すように、従来の画像センサーと呼ばれる半導体装置は、半導体ウエハー１０１上の電極パッド１０３がＡｕ線１０７を介してリードフレーム１０５に接続されており、また半導体ウエハー１０１の主面側がガラスプレート１０８により覆われた構造を有している。
【０００６】
次に、従来の半導体装置の製造方法について、同図を参照にしながら説明する。
【０００７】
まず、半導体ウエハー１０１をあらかじめ封止樹脂１０４を形成したリードフレーム１０５上にダイボンド材１０６により接合する。
【０００８】
次に、Ａｕ線１０７を用いて周知のワイヤーボンド法により、前記半導体ウエハー１０１上の電極パッド１０３とリードフレーム１０５とを電気的に接続する。
【０００９】
次に、ガラスプレート１０８を接着剤（図示せず）を用いて封止樹脂に接着する。以上により、半導体装置を製造していた。
【００１０】
すなわち、このような半導体装置の構造を採用することにより、半導体ウエハー１０１上の画素部１０２が封止樹脂で覆われることなく、なおかつＡｕ線を保護することが可能になるので、情報通信機器、事務用電子機器等の小型化を図れるものである。
【００１１】
【発明が解決しようとする課題】
しかしながら、前記従来の半導体装置においては、以下のような諸問題があった。
【００１２】
前記従来の半導体装置では、半導体ウエハ−とガラスプレートの間は中空であるため組立工程中にダストが半導体ウエハーの画素部に付着したり、組立後、吸湿することにより、ガラスプレートの半導体ウエハ側に結露を生じ、信頼性に乏しいという問題があった。
【００１３】
本発明は前記従来の諸問題を解決するものであり、その目的は、信頼性や実装密度の高い低コストの半導体装置およびその製造方法を提供することにある。
【００１４】
【課題を解決するための手段】
前記目的を達成するために本発明では、請求項１および２に記載されている半導体装置に関する手段と、請求項３に記載されている半導体装置の製造方法に関する手段とを講じている。
【００１５】
本発明の基本的な半導体装置は、請求項１に記載されているように、半導体素子の第１の面に画像素子部および電極が形成され、前記第１の面の前記電極を除く領域で前記画像素子部を覆うように透明な絶縁樹脂層が形成され、開口部を有する樹脂基板に形成された配線金属と前記電極とがバンプを介して接合され、前記配線金属と前記バンプとの接合部が封止樹脂で封止され、前記画像素子部が前記樹脂基板の開口部に対向し、前記樹脂基板上に外部端子が設けられ、前記封止樹脂は、前記透明な絶縁樹脂層と接しており、前記封止樹脂と前記透明な絶縁樹脂層とにより前記半導体素子の画像素子側全面が被覆されている。
【００１６】
これにより、透明な絶縁樹脂層が半導体基板の主面を保護するので、画像素子部へのダスト付着がなくなる。すなわち、信頼性の高い半導体装置を実現することができる。
【００１７】
そして、従来のように、ガラスプレートと封止樹脂からなる中空構造をしていないため、ガラスプレートの画像素子部側に結露が生じることがなくなる。
【００１８】
また封止樹脂を注入する際、絶縁樹脂がダムとなり、画像素子部への封止樹脂の流出を防ぐことができる。
【００２０】
請求項２に記載されているように、前記半導体装置において、前記半導体素子の第１の面の前記素子電極を除く領域にパッシベーション膜をさらに備え、前記絶縁樹脂層は、前記パッシベーション膜の上に形成されている。
【００２１】
これにより、より信頼性の高い半導体装置を得ることができる。
【００２２】
本発明の半導体装置の製造方法は、請求項３に記載されているように、半導体基板上の第１の面上に透明な絶縁樹脂層を形成する第１の工程と、前記透明な絶縁樹脂層のうち素子電極の上方に位置する領域を選択的に除去して、前記素子電極を露出させる開口部を形成する第２の工程と、前記素子電極にバンプを形成する第３の工程と、前記半導体基板を半導体チップ単位の半導体素子に分割する第４の工程と、前記半導体素子の画像素子部が樹脂基板の開口部に対向するように、前記半導体素子を前記樹脂基板に搭載するとともに、前記バンプと前記樹脂基板の配線金属とを接合する第５の工程と、前記バンプと前記半導体基板の接合部および前記配線金属と前記バンプとの接合部を封止樹脂により前記透明な絶縁樹脂層と接するように封止し、前記封止樹脂と前記透明な絶縁樹脂層で半導体素子の画像素子側全面を覆う第６の工程とを備える。
【００２３】
この方法により、チップに分離される前のウエハのままで、多数のチップ領域における画像素子上に塗布した透明な絶縁樹脂層をパターニングすることにより形成することができるので、製造コストを大幅に低減することができる。よって、請求項１の半導体を容易に実現することができる。
【００２５】
【発明の実施の形態】
以下、本発明の一実施形態について、図面を参照しながら説明する。
【００２６】
まず、本発明の第１の実施形態について、図１〜図４を参照しながら説明する。
【００２７】
図１は、本実施形態における半導体装置の平面図であり、図２は本実施形態に係る半導体装置の断面図、図３（ａ）〜（ｆ），図４（ａ）〜（ｃ）は本実施形態における半導体装置の製造工程を示す断面図である。
【００２８】
図１および図２において、１０はトランジスタ等の半導体素子および画像素子部１１によって構成される半導体集積回路を内部に有する半導体基板である。この半導体基板１０は、ウエハ状態であってもよいし、ウエハから切り出されたチップ状態であってもよい。この半導体基板１０の主面の一部（電極配置領域）には、半導体基板１０の素子電極１２が配置されている。
【００２９】
ただし、本実施形態では、電極配置領域は、半導体基板がチップに分割されている場合には、その周辺部である。また、半導体基板１０の主面上において、素子電極１２を除く領域に絶縁樹脂層１３が設けられている。
【００３０】
なお、半導体基板１０の主面のうち素子電極１２以外の領域は、パッシベーション膜（図示せず）によって覆われている。素子電極１２の上にはバンプ１４が形成されており、貫通穴１５が設けられた樹脂基板１６の配線金属１７と電気的に接続されている。
【００３１】
また、バンプ１４と配線金属１７の接続部は、封止樹脂１８により保護されている。また、配線金属の一部には外部電極としてはんだボール１９が搭載されている。なお、樹脂基板１６は、配線金属１７のバンプ１４との接続部およびはんだボール搭載部以外の領域はソルダーレジスト２０で覆われている。
【００３２】
本実施形態の半導体装置によると、半導体基板１０の画像素子部１１が絶縁樹脂層１３により保護されているので、外部からの機械的ダメージに強い構造となっている。
【００３３】
また、信頼性の観点から半導体基板の素子電極と樹脂基板の配線金属との接合部を封止する必要があるがその際、絶縁樹脂は、封止樹脂の画素部への進入を防止するダムの役割を果たすため、信頼性の高い実装構造を実現することができる。
【００３４】
以上、本実施形態の半導体装置は、開口部１５を有した樹脂基板１６上に画像素子部１１を含む半導体素子が配置されている半導体基板１０がバンプ１４を介して前記樹脂基板上の配線金属１７と接合され、前記樹脂基板１６とバンプ１４との領域が封止樹脂１８で封止され、前記半導体基板１０の画像素子部１１が絶縁樹脂１３で部分的に被覆されて、その画像素子部１１が前記樹脂基板１６の開口部１５に位置し、前記樹脂基板１６上にはんだボール１９が外部端子として設けられている半導体装置である。
【００３５】
次に、本実施形態の半導体装置の製造方法について、図３（ａ）〜（ｆ）および図４（ａ）〜（ｃ）を参照しながら説明する。図３（ａ）〜（ｆ）および図４（ａ）〜（ｃ）は、図１および図２に示す半導体装置の構造を実現するための製造工程を示す断面図である。
【００３６】
まず、図３（ａ）に示すように表面に画像素子部１１、素子電極１２を有した半導体基板１０を用意し、そして図３（ｂ）に示すように、半導体基板１０の主面にそれぞれ形成された半導体基板１０の画像素子部１１と素子電極１２とパッシベーション膜（図示せず）との上に、感光性を有する絶縁材料を３０［μｍ］程度の厚みで塗布して乾燥することにより絶縁樹脂層１３を形成する。
【００３７】
次に図３（ｃ）に示すように、乾燥された絶縁樹脂層１３に対して露光と現像とを順次行って、半導体基板１０の素子電極１１の部分が開口した絶縁樹脂層１３を形成する。
【００３８】
なお、感光性を有する絶縁樹脂層１３の絶縁材料としては、例えばカルド樹脂やアクリレート系エポキシ等のポリマーでよく、絶縁性で透明であればよく、無色透明が望ましい。
【００３９】
また、感光性を有する絶縁樹脂層１３は液状材料を乾燥させて形成する必要はなく、フィルム状に予め形成された材料を用いても構わない。その場合には、フィルム状の絶縁樹脂１３を半導体基板１０上に貼りあわせ、露光、現像することで絶縁樹脂層１３に開口部を形成することができ、半導体基板１０上の素子電極１２を露出させることができる。
【００４０】
さらに、絶縁樹脂層１３を構成する絶縁材料が感光性を有する必要はない。感光性を有しな絶縁材料を用いる場合には、レーザーやプラズマによる機械的な加工もしくはエッチングなどの化学的加工により、半導体基板１０上の素子電極１２を露出させることができる。
【００４１】
次に、図３（ｄ）に示すように、半導体基板１０上の素子電極１２上にバンプ１４を電解めっき法あるいは無電解めっき法を用いて形成する。なおバンプとしては、Ｓｎ−Ｐｂ共晶はんだでもよく、Ｓｎ−Ｐｂ高温はんだ、Ｎｉ、Ｓｎ、Ｃｕ、Ａｇ、Ａｕ等の金属およびその合金であってもよい。
【００４２】
次に、図３（ｅ），図３（ｆ）に示すように、ダイシングソーにて、半導体基板１０をチップ単位に分割する。
【００４３】
次に、図４（ａ）に示すように、チップ状の半導体構成体２１を樹脂基板１６の配線金属１７上に搭載し、溶融することでバンプ１４と配線金属１７を電気的に接続する。またソルダーレジスト２０で樹脂基板１６上の配線金属１７のバンプ１４との接続部およびはんだボール搭載部以外の領域を被覆する。
【００４４】
なお、バンプ１４と配線金属１７との接続は、導電性ペーストを用いても構わない。
【００４５】
次に、図４（ｂ）に示すように、封止樹脂１８を用いてバンプ１４と配線金属１７の接合部を封止する。
【００４６】
次に、図４（ｃ）に示すように、配線金属１７の一部に外部電極としてはんだボール１９を搭載する。
【００４７】
なお、図５の別の半導体装置の形態を示す断面図に示すように、はんだボール１９を樹脂基板１６上の半導体構成体２１（半導体基板）が搭載される反対側に形成してもよい。
【００４８】
以上の工程によって、本実施形態に係る半導体装置を得ることができる。
【００４９】
【発明の効果】
本発明の半導体装置は、画像素子部が絶縁樹脂により保護されているので、機械的なダメージに強い半導体装置である。さらにフリップチップ接続されており、ガラスプレート等の部材が必要でないため薄型の半導体装置である。
【００５０】
またその製造方法においては、封止樹脂の流出を画像素子部に形成した絶縁樹脂により防止できるため、画像素子部を覆うこと無く、バンプと樹脂基板の配線金属との接続部を保護することができるので、より低コストで高性能な小型半導体装置を形成することができる。
【図面の簡単な説明】
【図１】本発明の一実施形態における半導体装置を示す平面図
【図２】本発明の一実施形態における半導体装置を示す断面図
【図３】本発明の一実施形態における半導体装置の製造工程を示す断面図
【図４】本発明の一実施形態における半導体装置の製造工程を示す断面図
【図５】本発明の一実施形態における半導体装置を示す断面図
【図６】従来の半導体装置を示す断面図
【符号の説明】
１０ 半導体基板
１１ 画像素子部
１２ 素子電極
１３ 絶縁樹脂層
１４ バンプ
１５ 貫通穴
１６ 樹脂基板
１７ 配線金属
１８ 封止樹脂
１９ はんだボール
２０ ソルダーレジスト
２１ 半導体構成体
１０１ ウエハー
１０２ 画像素子部
１０３ 電極パッド
１０４ 封止樹脂
１０５ リードフレーム
１０６ ダイスボンド材
１０７ Ａｕ線
１０８ ガラスプレート[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device that incorporates a semiconductor image sensor used for information communication equipment, office electronic equipment, and the like, and further has connection wiring to external terminals, etc., and enables high-density mounting. Is. The semiconductor device of the present invention facilitates downsizing of information communication equipment, office electronic equipment, and the like.
[0002]
[Prior art]
2. Description of the Related Art In recent years, semiconductor devices and manufacturing methods thereof have been required to be downsized and increased in density with the downsizing and high functionality of electronic devices, and image sensors such as CCD and CMOS sensors have been developed.
[0003]
Hereinafter, a conventional semiconductor device called an image sensor and a manufacturing method thereof will be described with reference to cross-sectional views.
[0004]
FIG. 6 is a cross-sectional view showing a conventional semiconductor device called an image sensor. In FIG. 6, 101 is a semiconductor chip or semiconductor wafer, 102 is a pixel portion formed on the semiconductor wafer 101, 103 is an electrode pad, 104 is a sealing resin, 105 is a lead frame, 106 is a die bond material, and 107 is Au wire. , 108 are glass plates for sealing.
[0005]
As shown in the figure, in a conventional semiconductor device called an image sensor, an electrode pad 103 on a semiconductor wafer 101 is connected to a lead frame 105 via an Au wire 107, and the main surface side of the semiconductor wafer 101 is glass. The structure is covered with a plate 108.
[0006]
Next, a conventional method for manufacturing a semiconductor device will be described with reference to FIG.
[0007]
First, the semiconductor wafer 101 is bonded to the lead frame 105 on which the sealing resin 104 is previously formed by the die bond material 106.
[0008]
Next, the electrode pad 103 on the semiconductor wafer 101 and the lead frame 105 are electrically connected by the well-known wire bonding method using the Au wire 107.
[0009]
Next, the glass plate 108 is bonded to the sealing resin using an adhesive (not shown). Thus, a semiconductor device has been manufactured.
[0010]
That is, by adopting such a structure of the semiconductor device, the pixel portion 102 on the semiconductor wafer 101 is not covered with the sealing resin, and the Au wire can be protected. This makes it possible to reduce the size of office electronic devices.
[0011]
[Problems to be solved by the invention]
However, the conventional semiconductor device has the following problems.
[0012]
In the conventional semiconductor device, since the space between the semiconductor wafer and the glass plate is hollow, dust adheres to the pixel portion of the semiconductor wafer during the assembling process or absorbs moisture after assembling, so that the side of the glass plate on the semiconductor wafer side There was a problem that dew condensation occurred and reliability was poor.
[0013]
The present invention solves the above-described conventional problems, and an object of the present invention is to provide a low-cost semiconductor device with high reliability and mounting density, and a manufacturing method thereof.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, the present invention employs means relating to the semiconductor device described in claims 1 and 2 and means relating to a method for manufacturing the semiconductor device described in claim 3 .
[0015]
According to a first aspect of the present invention, an image element portion and an electrode are formed on a first surface of a semiconductor element, and a region excluding the electrode on the first surface. A transparent insulating resin layer is formed so as to cover the image element portion, a wiring metal formed on a resin substrate having an opening and the electrode are bonded via a bump, and the wiring metal and the bump are bonded. The sealing portion is sealed with a sealing resin, the image element portion faces the opening of the resin substrate, an external terminal is provided on the resin substrate, and the sealing resin is in contact with the transparent insulating resin layer. The entire surface of the semiconductor element on the image element side is covered with the sealing resin and the transparent insulating resin layer.
[0016]
Thereby, since the transparent insulating resin layer protects the main surface of the semiconductor substrate, dust adhesion to the image element portion is eliminated. That is, a highly reliable semiconductor device can be realized.
[0017]
And since it does not have the hollow structure which consists of a glass plate and sealing resin like the past, dew condensation does not arise in the image element part side of a glass plate.
[0018]
Further, when injecting the sealing resin, the insulating resin becomes a dam, and the outflow of the sealing resin to the image element portion can be prevented.
[0020]
3. The semiconductor device according to claim 2, further comprising a passivation film in a region excluding the element electrode on the first surface of the semiconductor element , wherein the insulating resin layer is formed on the passivation film. Is formed .
[0021]
Thereby, a more reliable semiconductor device can be obtained.
[0022]
According to a third aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: a first step of forming a transparent insulating resin layer on a first surface of a semiconductor substrate; and the transparent insulating resin. A second step of selectively removing a region of the layer located above the device electrode to form an opening exposing the device electrode; a third step of forming a bump on the device electrode; a fourth step of dividing the semiconductor substrate into a semiconductor element of the semiconductor chip unit, together with the image element portion of the semiconductor element so as to face the opening of the resin substrate, for mounting the semiconductor element on the resin substrate, A fifth step of bonding the bump and the wiring metal of the resin substrate; and a bonding portion of the bump and the semiconductor substrate and a bonding portion of the wiring metal and the bump by the sealing resin. Sealed to touch And, and a sixth step of covering the image element side surface of the semiconductor device in the transparent insulating resin layer and the sealing resin.
[0023]
By this method, it is possible to form a transparent insulating resin layer applied on the image element in a large number of chip areas by patterning the wafer before being separated into chips, thereby greatly reducing the manufacturing cost. can do. Therefore, the semiconductor of claim 1 can be easily realized.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[0026]
First, a first embodiment of the present invention will be described with reference to FIGS.
[0027]
FIG. 1 is a plan view of a semiconductor device according to the present embodiment, FIG. 2 is a cross-sectional view of the semiconductor device according to the present embodiment, and FIGS. 3 (a) to 3 (f) and FIGS. It is sectional drawing which shows the manufacturing process of the semiconductor device in this embodiment.
[0028]
1 and 2, reference numeral 10 denotes a semiconductor substrate having therein a semiconductor integrated circuit constituted by a semiconductor element such as a transistor and an image element portion 11. The semiconductor substrate 10 may be in a wafer state or a chip state cut out from the wafer. The element electrode 12 of the semiconductor substrate 10 is arranged on a part (electrode arrangement region) of the main surface of the semiconductor substrate 10.
[0029]
However, in the present embodiment, the electrode arrangement region is a peripheral portion when the semiconductor substrate is divided into chips. An insulating resin layer 13 is provided on the main surface of the semiconductor substrate 10 in a region excluding the device electrodes 12.
[0030]
Note that a region other than the device electrode 12 in the main surface of the semiconductor substrate 10 is covered with a passivation film (not shown). Bumps 14 are formed on the device electrodes 12 and are electrically connected to the wiring metal 17 of the resin substrate 16 provided with the through holes 15.
[0031]
Further, the connection portion between the bump 14 and the wiring metal 17 is protected by a sealing resin 18. A solder ball 19 is mounted as an external electrode on a part of the wiring metal. The resin substrate 16 is covered with a solder resist 20 in areas other than the connection portion between the wiring metal 17 and the bump 14 and the solder ball mounting portion.
[0032]
According to the semiconductor device of this embodiment, since the image element portion 11 of the semiconductor substrate 10 is protected by the insulating resin layer 13, the structure is strong against mechanical damage from the outside.
[0033]
In addition, from the viewpoint of reliability, it is necessary to seal the joint portion between the element electrode of the semiconductor substrate and the wiring metal of the resin substrate. In this case, the insulating resin is a dam that prevents the sealing resin from entering the pixel portion. Therefore, a highly reliable mounting structure can be realized.
[0034]
As described above, in the semiconductor device according to the present embodiment, the semiconductor substrate 10 in which the semiconductor element including the image element unit 11 is disposed on the resin substrate 16 having the opening 15 is connected to the wiring metal on the resin substrate via the bumps 14. 17, the region of the resin substrate 16 and the bump 14 is sealed with a sealing resin 18, and the image element portion 11 of the semiconductor substrate 10 is partially covered with an insulating resin 13. The semiconductor device 11 is located in the opening 15 of the resin substrate 16 and the solder balls 19 are provided on the resin substrate 16 as external terminals.
[0035]
Next, the manufacturing method of the semiconductor device of this embodiment will be described with reference to FIGS. 3 (a) to 3 (f) and FIGS. 4 (a) to 4 (c). FIGS. 3A to 3F and FIGS. 4A to 4C are cross-sectional views showing manufacturing steps for realizing the structure of the semiconductor device shown in FIGS.
[0036]
First, as shown in FIG. 3A, a semiconductor substrate 10 having an image element portion 11 and an element electrode 12 on the surface is prepared, and as shown in FIG. A photosensitive insulating material is applied to a thickness of about 30 [μm] on the image element portion 11, the element electrode 12, and a passivation film (not shown) of the formed semiconductor substrate 10, and then dried. An insulating resin layer 13 is formed.
[0037]
Next, as shown in FIG. 3C, exposure and development are sequentially performed on the dried insulating resin layer 13 to form the insulating resin layer 13 in which the element electrode 11 portion of the semiconductor substrate 10 is opened. .
[0038]
The insulating material of the insulating resin layer 13 having photosensitivity may be, for example, a polymer such as cardo resin or acrylate epoxy, and may be insulating and transparent, and is preferably colorless and transparent.
[0039]
The photosensitive insulating resin layer 13 does not need to be formed by drying a liquid material, and a material previously formed in a film shape may be used. In that case, an opening can be formed in the insulating resin layer 13 by laminating the film-like insulating resin 13 on the semiconductor substrate 10, exposing and developing, and the element electrode 12 on the semiconductor substrate 10 is exposed. Can be made.
[0040]
Furthermore, the insulating material constituting the insulating resin layer 13 need not have photosensitivity. When an insulating material having no photosensitivity is used, the device electrode 12 on the semiconductor substrate 10 can be exposed by chemical processing such as mechanical processing using laser or plasma or etching.
[0041]
Next, as shown in FIG. 3D, bumps 14 are formed on the device electrodes 12 on the semiconductor substrate 10 by using an electrolytic plating method or an electroless plating method. The bump may be Sn-Pb eutectic solder, Sn-Pb high temperature solder, metal such as Ni, Sn, Cu, Ag, Au, and alloys thereof.
[0042]
Next, as shown in FIGS. 3E and 3F, the semiconductor substrate 10 is divided into chips by a dicing saw.
[0043]
Next, as shown in FIG. 4A, the chip-like semiconductor structure 21 is mounted on the wiring metal 17 of the resin substrate 16 and melted to electrically connect the bump 14 and the wiring metal 17. Further, the solder resist 20 covers the region other than the connection portion of the wiring metal 17 on the resin substrate 16 with the bump 14 and the solder ball mounting portion.
[0044]
Note that a conductive paste may be used to connect the bumps 14 and the wiring metal 17.
[0045]
Next, as shown in FIG. 4B, the bonding portion between the bump 14 and the wiring metal 17 is sealed using a sealing resin 18.
[0046]
Next, as shown in FIG. 4C, a solder ball 19 is mounted as an external electrode on a part of the wiring metal 17.
[0047]
In addition, as shown in the cross-sectional view showing another embodiment of the semiconductor device in FIG. 5, the solder balls 19 may be formed on the opposite side on which the semiconductor structure 21 (semiconductor substrate) on the resin substrate 16 is mounted.
[0048]
The semiconductor device according to this embodiment can be obtained through the above steps.
[0049]
【The invention's effect】
The semiconductor device of the present invention is a semiconductor device that is resistant to mechanical damage because the image element portion is protected by an insulating resin. Further, since it is flip-chip connected and does not require a member such as a glass plate, it is a thin semiconductor device.
[0050]
Further, in the manufacturing method, since the leakage of the sealing resin can be prevented by the insulating resin formed on the image element portion, the connection portion between the bump and the wiring metal of the resin substrate can be protected without covering the image element portion. Therefore, a small semiconductor device with high performance at a lower cost can be formed.
[Brief description of the drawings]
FIG. 1 is a plan view illustrating a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating the semiconductor device according to an embodiment of the present invention. FIG. 4 is a cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. FIG. 5 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. Sectional view shown [Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Image element part 12 Element electrode 13 Insulation resin layer 14 Bump 15 Through-hole 16 Resin substrate 17 Wiring metal 18 Sealing resin 19 Solder ball 20 Solder resist 21 Semiconductor structure 101 Wafer 102 Image element part 103 Electrode pad 104 Sealing Stop resin 105 Lead frame 106 Die bond material 107 Au wire 108 Glass plate

Claims (3)

半導体素子の第１の面に画像素子部および電極が形成され、前記第１の面の前記電極を除く領域で前記画像素子部を覆うように透明な絶縁樹脂層が形成され、開口部を有する樹脂基板に形成された配線金属と前記電極とがバンプを介して接合され、前記配線金属と前記バンプとの接合部が封止樹脂で封止され、前記画像素子部が前記樹脂基板の開口部に対向し、前記樹脂基板上に外部端子が設けられ、前記封止樹脂は、前記透明な絶縁樹脂層と接しており、前記封止樹脂と前記透明な絶縁樹脂層とにより前記半導体素子の画像素子側全面が被覆されていることを特徴とする半導体装置。An image element portion and an electrode are formed on the first surface of the semiconductor element, a transparent insulating resin layer is formed so as to cover the image element portion in a region excluding the electrode on the first surface, and has an opening The wiring metal formed on the resin substrate and the electrode are joined via bumps, the joint between the wiring metal and the bump is sealed with a sealing resin, and the image element portion is an opening of the resin substrate. External terminals are provided on the resin substrate, the sealing resin is in contact with the transparent insulating resin layer, and the image of the semiconductor element is formed by the sealing resin and the transparent insulating resin layer. A semiconductor device characterized in that the entire element side is covered. 請求項１に記載の半導体装置において、前記半導体素子の第１の面の前記素子電極を除く領域にパッシベーション膜をさらに備え、前記絶縁樹脂層は、前記パッシベーション膜の上に形成されていることを特徴とする半導体装置。2. The semiconductor device according to claim 1, further comprising a passivation film in a region excluding the element electrode on the first surface of the semiconductor element, and the insulating resin layer is formed on the passivation film. A featured semiconductor device. 半導体基板上の第１の面上に透明な絶縁樹脂層を形成する第１の工程と、前記透明な絶縁樹脂層のうち素子電極の上方に位置する領域を選択的に除去して、前記素子電極を露出させる開口部を形成する第２の工程と、前記素子電極にバンプを形成する第３の工程と、前記半導体基板を半導体チップ単位の半導体素子に分割する第４の工程と、前記半導体素子の画像素子部が樹脂基板の開口部に対向するように、前記半導体素子を前記樹脂基板に搭載するとともに、前記バンプと前記樹脂基板の配線金属とを接合する第５の工程と、前記バンプと前記半導体基板の接合部および前記配線金属と前記バンプとの接合部を封止樹脂により前記透明な絶縁樹脂層と接するように封止し、前記封止樹脂と前記透明な絶縁樹脂層で半導体素子の画像素子側全面を覆う第６の工程とを備えたことを特徴とする半導体装置の製造方法。A first step of forming a transparent insulating resin layer on a first surface of the semiconductor substrate; and a region of the transparent insulating resin layer located above the element electrode is selectively removed to form the element A second step of forming an opening exposing the electrode; a third step of forming a bump on the element electrode; a fourth step of dividing the semiconductor substrate into semiconductor elements in units of semiconductor chips; and the semiconductor as the image element of the element is opposed to the opening of the resin substrate, wherein with the semiconductor element mounted on the resin substrate, and a fifth step of bonding the wiring metal of the resin substrate and the bump, the bump And the junction between the semiconductor substrate and the junction between the wiring metal and the bump are sealed with a sealing resin so as to be in contact with the transparent insulating resin layer, and the semiconductor is formed with the sealing resin and the transparent insulating resin layer. Image element side of the element The method of manufacturing a semiconductor device characterized by comprising a sixth step of covering the surface.
JP2000113772A 2000-04-14 2000-04-14 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4244096B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000113772A JP4244096B2 (en) 2000-04-14 2000-04-14 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000113772A JP4244096B2 (en) 2000-04-14 2000-04-14 Semiconductor device and manufacturing method thereof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2008124278A Division JP2008219041A (en) 2008-05-12 2008-05-12 Semiconductor device and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JP2001298050A JP2001298050A (en) 2001-10-26
JP4244096B2 true JP4244096B2 (en) 2009-03-25

Family

ID=18625689

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000113772A Expired - Fee Related JP4244096B2 (en) 2000-04-14 2000-04-14 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP4244096B2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004165191A (en) * 2002-11-08 2004-06-10 Oki Electric Ind Co Ltd Semiconductor device, method of manufacturing semiconductor device, and camera system
JP3768972B2 (en) 2003-04-28 2006-04-19 松下電器産業株式会社 Solid-state imaging device and manufacturing method thereof
US6943423B2 (en) * 2003-10-01 2005-09-13 Optopac, Inc. Electronic package of photo-image sensors in cellular phone camera modules, and the fabrication and assembly thereof
US6864116B1 (en) * 2003-10-01 2005-03-08 Optopac, Inc. Electronic package of photo-sensing semiconductor devices, and the fabrication and assembly thereof
US20060043513A1 (en) * 2004-09-02 2006-03-02 Deok-Hoon Kim Method of making camera module in wafer level
JP4196937B2 (en) 2004-11-22 2008-12-17 パナソニック株式会社 Optical device

Also Published As

Publication number Publication date
JP2001298050A (en) 2001-10-26

Similar Documents

Publication Publication Date Title
KR100540243B1 (en) Semiconductor device and method for fabricating the same
JP3176542B2 (en) Semiconductor device and manufacturing method thereof
JP3335575B2 (en) Semiconductor device and manufacturing method thereof
JP3400877B2 (en) Semiconductor device and manufacturing method thereof
US8193624B1 (en) Semiconductor device having improved contact interface reliability and method therefor
US20070145603A1 (en) Semiconductor chip, mounting structure thereof, and methods for forming a semiconductor chip and printed circuit board for the mounting structure thereof
JP3356921B2 (en) Semiconductor device and method of manufacturing the same
US20050258502A1 (en) Chip package, image sensor module including chip package, and manufacturing method thereof
JPH10321672A (en) Semiconductor device and its manufacture
JPH0637143A (en) Semiconductor device and manufacture thereof
US8211754B2 (en) Semiconductor device and manufacturing method thereof
JP2001244365A (en) Wiring board, semiconductor device, and method of manufacturing wiring board
JP2001298115A (en) Semiconductor device and its manufacturing method, circuit board, and electronic equipment
JPH053183A (en) Semiconductor device and manufacture thereof
JP3402086B2 (en) Semiconductor device and manufacturing method thereof
JP3618212B2 (en) Semiconductor device and manufacturing method thereof
JP4244096B2 (en) Semiconductor device and manufacturing method thereof
JPS6189657A (en) Semiconductor device and manufacture thereof
JP3569585B2 (en) Semiconductor device
JPH11204560A (en) Semiconductor device and manufacture thereof
JP2006173463A (en) Sensor module
JP2002231765A (en) Semiconductor device
JP2008219041A (en) Semiconductor device and method of manufacturing the same
JP2018088505A (en) Semiconductor device and manufacturing method for the same
JP4631223B2 (en) Semiconductor package and semiconductor device using the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060510

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20060613

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060829

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070508

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070709

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071225

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20080415

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20080428

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080512

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20080618

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080715

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080916

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20081014

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20081031

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20081202

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20081225

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120116

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees