JP4242136B2 - Method for forming wiring structure - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a wiring structure mainly used in a semiconductor device, and is particularly applied when a wiring structure is formed of a material containing at least copper (Cu).
[0002]
[Prior art]
In recent years, with the high integration of semiconductor elements and the reduction in chip size, miniaturization of wiring and multilayer wiring have been accelerated. In a logic device having such multilayer wiring, wiring delay is becoming one of the dominant factors of device signal delay. The signal delay of the device is proportional to the product of the wiring resistance value and the wiring capacitance. Therefore, to improve the wiring delay, it is important to reduce the wiring resistance value and the wiring capacitance.
[0003]
Therefore, in order to reduce the wiring capacity, it has been studied to form a Cu wiring. Cu is difficult to process. Therefore, as a suitable structure when this is applied to a wiring, a connection hole (via hole) and a wiring groove formed in an interlayer insulating film are used to prevent diffusion of Cu and improve adhesion. A so-called damascene structure, which is filled with Cu via a base film (barrier metal film) formed on the substrate, has attracted attention.
[0004]
In this case, in order to form the barrier metal film, a self-sputtering method or an ionization sputtering method typified by IMP or the like is used in order to ensure high coverage.
[0005]
[Patent Document 1]
Japanese Patent No. 3310608
[0006]
[Problems to be solved by the invention]
In order to meet the recent demand for miniaturization and high integration of semiconductor devices, further miniaturization of the Cu wiring structure is required, and accordingly, the via hole needs to have a high aspect ratio. However, even if ionized sputtering is used, it is difficult to obtain sufficient coverage (coverage) of the barrier metal film corresponding to the high aspect ratio of the via hole. For this reason, when a metal film having a sufficient film thickness is formed on the side wall and the bottom of the via hole with respect to the pattern including the via hole and the wiring groove, excess metal adheres to the shoulder. When the inside of the pattern is filled with Cu by a plating method, the penetration of the plating solution into the pattern is hindered, an embedding failure occurs, the yield is lowered, and the wiring reliability is remarkably deteriorated.
[0007]
In addition, by applying an RF bias to the stage side mounted in the sputtering chamber to form a metal film (bias sputtering method), the barrier metal film coverage is improved, but the shoulder of the wiring groove and via hole is improved. There is a concern that a part may be etched and a short circuit may occur between adjacent wirings, particularly in a narrow pitch wiring.
[0008]
Specifically, the bias sputtering method is a method in which an RF bias is applied to the stage mounted in the sputtering chamber, and the film is formed while drawing the sputtered particles. As a result, for example, the effect of increasing the number of sputtered particles entering the via hole and the wiring groove and the effect of scattering the sputtered particles adhering to the via hole and the side wall of the wiring groove again (etching effect) can be effectively used. By doing so, it is possible to form a base film with excellent coverage even in places where the sputtered particles are difficult to adhere and the coverage is insufficient, such as the side wall near the bottom of the via hole.
[0009]
Sputtering for forming the barrier metal film includes non-bias sputtering with no RF bias applied or sputtering with a bias sputtering with RF bias applied (hereinafter referred to as one-step sputtering), non-bias sputtering. Subsequent to the one-step sputtering, there is sputtering (hereinafter referred to as two-step sputtering) performed by combining a bias sputtering method in which an RF bias is applied.
[0010]
However, at this time, inconvenience as described below occurs. FIG. 10 shows the case of one-step sputtering, and FIG. 11 shows the case of two-step sputtering. 10 and 11, a barrier metal film 105 is formed on the inner wall of the wiring groove 104 and the via hole 103 formed in the interlayer insulating film 102 covering the lower layer wiring 101 by the sputtering method, and then the Cu material 106 is formed by plating. Embed.
[0011]
In the non-bias one-step sputtering, as shown in FIG. 10A, the barrier metal film 105 becomes thin particularly at the side wall portion of the via hole 103, and the coverage is lowered. Thereby, when the Cu material 106 is filled, voids 107 are generated due to insufficient coverage.
[0012]
Further, in one-step sputtering in which an RF bias is applied, as shown in FIG. 10B, coverage is ensured at the side wall of the via hole 103, but coverage at the bottom of the via hole 103 is reduced and Overhang becomes strong at the upper portion (shoulder portion) of the side wall of the hole 103, and when the Cu material 106 is filled, voids 108 are generated in the bottom portion or the shoulder portion.
[0013]
On the other hand, in the two-step sputtering, it is possible to form a film without increasing the overhang of the shoulder while ensuring the coverage of the bottom. However, in two-step sputtering, variations in electrical characteristics are likely to occur due to deterioration of in-plane distribution and variations in film thickness at the bottom of the barrier metal film. Furthermore, if the barrier metal film 105 remains partially at the connection site between the lower layer wiring 101 and the via hole 103, there is a risk of causing voids due to non-uniform wiring stress. In addition, when the Cu material 106 of the lower layer wiring 101 and the via hole 103 is joined without passing through the barrier metal film 105, a crystal defect occurs due to a difference in film quality between the two, and the EM (electromigration) resistance is impaired. There is also a fear.
[0014]
From this point of view, in order to ensure wiring reliability, a certain thickness of the barrier metal film 105 at the bottom must be secured, and an attempt is made to achieve Cu filling in which a void is not generated in a high aspect ratio via hole. Then, in one-step sputtering or two-step sputtering, the process window is too narrow and it is difficult to apply the process.
[0015]
The present invention has been made in view of the above-described problems, and makes it possible to reliably obtain sufficient coverage (coverage) of a barrier metal film corresponding to a high aspect ratio of a via hole. It is an object of the present invention to provide a method for forming a wiring structure that realizes improvement in wiring reliability and initial yield while accommodating miniaturization and high integration.
[0016]
[Means for Solving the Problems]
  The wiring structure forming method of the present invention is a method for forming a wiring structure having a wiring material and a barrier metal film for preventing diffusion of the wiring material in a connection hole disposed in an insulating film above a substrate. When the barrier metal film is formed by sputtering, the following two-step sputtering is performed.
  No bias appliedA first sputtering step performed under conditions;After the first sputtering step,A first state in which the material of the barrier metal film is deposited and a second state in which the deposited material of the barrier metal film is etched are mixed, and the first state is the second state at the bottom of the connection hole. And a second sputtering step for 3 seconds to 12 seconds performed by applying a bias so as to be stronger than the above state.
[0017]
  The wiring structure forming method of the present invention is a method for forming a wiring structure having a wiring material and a barrier metal film for preventing diffusion of the wiring material in a connection hole disposed in an insulating film above a substrate. When the barrier metal film is formed by sputtering, the following three-step sputtering is performed.
First sputtering processWhen,After the first sputtering step,A first state in which the material of the barrier metal film is deposited and a second state in which the deposited material of the barrier metal film is etched are mixed, and the second state is the first state at the bottom of the connection hole. A second sputtering step performed under conditions that are stronger than the state ofThird sputtering step performed after the second sputtering stepIncludingIn the first and third sputtering processes, the first and third sputtering processes are performed under the condition of no bias applied, or the first sputtering process is performed under the condition of no bias applied, and the third sputtering process. Performing the process under the condition that the first state is stronger than the second state, or performing the first sputtering step under the condition that the first state is stronger than the second state, Either the third sputtering step is performed under the condition that no bias is applied, or the first and third sputtering steps are performed under the condition that the first state is stronger than the second state, respectively. It is.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
-Basic outline of the present invention-
First, the basic outline based on the operation principle of the present invention will be described.
[0019]
(Basic principle 1)
As a first technique of the present invention, the inventor has sought a film formation technique for a barrier metal film having excellent coverage over the entire via hole and wiring groove while taking advantage of the above-described two-step sputtering.
[0020]
In the bias sputtering method, there are a first state in which a sputtered material is deposited and a second state in which the deposited sputtered material is etched in accordance with the bias power. In general, RF bias (e.g. bias density (W / cm²If)) is low, the deposition rate is higher than the etching rate in the first state due to strength in the second state. On the other hand, if the RF bias is higher than this, the relative intensity of the second state will increase and the etching rate will be higher than the deposition rate.
[0021]
FIG. 1 shows a schematic configuration of the two-step sputtering of the present invention. Here, a barrier metal film 105 is formed on the inner wall of the wiring trench 104 and the via hole 103 formed in the interlayer insulating film 102 covering the lower layer wiring 101 by the sputtering method, and then a Cu material 106 is embedded by a plating method. The material of the barrier metal film 105 includes at least one selected from a refractory metal, a nitrogen compound of a refractory metal, and a silicon compound, and has a diffusion preventing function and an adhesion function of a Cu material. Here, the melting point metal is Ta.
[0022]
In the present invention, paying attention to the above-mentioned property in bias sputtering, first, a low RF bias, preferably a non-bias is used with respect to a state where the inner walls of the wiring trench 104 and the via hole 103 are exposed (FIG. 1A). After depositing the metal material by performing the first sputtering (FIG. 1B), the relative strength in the first state is set higher than that in the second state, that is, the deposition rate is set higher than the etching rate. A second sputtering is performed (FIG. 1C).
[0023]
Here, in the first sputtering, only the first state which is the deposition mode or this is dominant, so that the coverage at the bottom of the via hole 103 of the barrier metal film 105 is ensured. In the second sputtering, the first state that is the deposition mode and the second state that is the etching mode coexist, but the first state is dominant. Therefore, the barrier metal film 105 is formed at the bottom of the via hole 103. Coverage is maintained by suppressing defects caused by etching, and coverage in the side wall portion of the barrier metal film 105 is ensured while suppressing the overhang of the shoulder portion of the via hole 103 due to the presence of the second state. Therefore, excellent coverage of the barrier metal film 105 is obtained not only on the wiring groove 104 but also on the entire inner wall of the via hole 103, and satisfactory filling of the Cu material 106 is realized without generating voids or the like (FIG. 1D). )).
[0024]
The inventor considered specific conditions for realizing the deposition rate> the etching rate in the second sputtering. The parameter that determines the relative superiority of the first and second states is not only the RF bias level. For example, when bias sputtering is performed with an RF bias set to a certain value, the strength of the first and second states is not constant, and the second state becomes stronger than the first state after a certain time. Was found.
[0025]
Therefore, based on comparison with one-step sputtering (non-bias) and conventional two-step sputtering (non-bias +350 W, RF bias with a bias application time of 15 seconds), the two-step sputtering of the present invention (non-bias +350 W, The initial yield of chain resistance at a bias application time of 10 seconds (RF bias) was examined.
[0026]
The experimental results are shown in FIG. As described above, compared with the one-step sputtering and the conventional two-step sputtering, the bias application time is shorter in the second sputtering in the second sputtering (shorter than the conventional 15 seconds). 3 seconds to 12 seconds, here 10 seconds), it can be seen that a sufficient initial yield can be obtained.
[0027]
Furthermore, based on a comparison with one-step sputtering (non-bias) and conventional two-step sputtering (non-bias +350 W, RF bias with a bias application time of 15 seconds), the two-step sputtering of the present invention (non-bias +350 W, The wiring reliability in the case of RF bias with a bias application time of 10 seconds was examined.
[0028]
The experimental results are shown in FIG. Here, a high temperature storage test was performed at 200 ° C. As described above, defects were observed in one-step sputtering or conventional two-step sputtering, whereas no defects were observed in the two-step sputtering of the present invention.
[0029]
Furthermore, based on the comparison with the conventional two-step sputtering (non-bias +350 W, RF bias with a bias application time of 15 seconds), the two-step sputtering of the present invention (non-bias +350 W, RF bias with a bias application time of 10 seconds) is performed. The thickness of each of the barrier metal films on the shoulder A, the side wall B, and the bottom C of the inner wall of the via hole was examined.
[0030]
The experimental results are shown in FIG. In the conventional two-step sputtering, the bottom portion C is swept away by the second sputtering, resulting in film formation failure (partial lack of barrier metal film). On the other hand, in the two-step sputtering of the present invention, a slight overhang is observed in the shoulder A by the second sputtering, but a sufficient film thickness (2-3 ( nm) degree).
[0031]
As described above, according to the first method of the present invention, it is possible to form a barrier metal film having excellent coverage on the inner wall of the via hole as well as the wiring groove by two-step sputtering. The reliability and the initial yield can be improved.
[0032]
(Basic principle 2)
As a second technique of the present invention, the present inventor obtained a barrier metal film having excellent coverage over the entire via hole and wiring trench by performing the third sputtering in addition to the above-described two-step sputtering. I came up with the idea.
[0033]
FIG. 5 shows a schematic configuration of the three-step sputtering of the present invention. Here, as in FIG. 1, after forming the barrier metal film 105 on the inner wall of the wiring groove 104 and the via hole 103 formed in the interlayer insulating film 102 covering the lower layer wiring 101 by the sputtering method, the Cu material is then formed by the plating method. 106 is embedded.
[0034]
The material of the barrier metal film 105 is at least one selected from Ta, Ti, W, Zr, at least one nitride selected from Ta, Ti, W, Zr, or Ta, Ti, W, Zr. Those containing at least one compound selected from the above as a material are preferable. Specifically, as shown in FIG. 6, a combination of Ta and TaN in three sputterings (FIG. 6A), a combination of Ti and TiN (FIG. 6B), and a combination of W and WN (FIG. 6). (C)), a combination of Zr and ZrN (FIG. 6D) was examined. Hereinafter, in this example, a case where Ta is used as the material of the barrier metal film 105 will be described.
[0035]
In the present invention, first, after a metal material is deposited by performing a first sputtering with a low RF bias or non-bias in a state where the inner walls of the wiring trench 104 and the via hole 103 are exposed (FIG. 5A) ( In FIG. 5B, the first state that is the deposition mode and the second state that is the etching mode coexist, and the second state prevails, for example, with an RF bias higher than that of the first sputtering. A second sputtering is performed to deposit a metal material (FIG. 5C). At this time, as in FIGS. 10 and 11, a film formation failure (partial lack of metal material) occurs at the bottom of the via hole 103. Then, the third sputtering is performed with an RF bias or non-bias lower than the second time (FIG. 5D). Thus, the barrier metal film 105 at the bottom of the via hole 103 is formed thick without increasing the overhang at the shoulder of the via hole 103. Therefore, excellent coverage of the barrier metal film 105 is obtained not only on the wiring trench 104 but also on the entire inner wall of the via hole 103, and good filling of the Cu material 106 is realized without generating voids or the like (FIG. 5E). )).
[0036]
Here, the level of the RF bias in the three sputterings is specifically, as an example, when the target power is 10 kW,
▲ 1 ▼ 0.96 (W / cm²In smaller cases, etch rate> deposition rate
(2) 0.96 (W / cm²In larger cases, deposition rate> etch rate
It becomes. Note that the bias power at which both modes are switched varies depending on the DC power of sputtering.
That is, with reference to this, the bias (1) is adopted as the first and third low RF biases, and the bias (2) is adopted as the second high RF bias.
[0037]
As described above, according to the second method of the present invention, the thickness of the barrier metal film at the bottom of the via hole is increased by three-step sputtering without increasing the overhang at the shoulder of the via hole. Can be secured. Accordingly, it becomes possible to effectively correct the film thickness variation of the barrier metal film at the bottom of the via hole which has occurred until the second sputtering, and the process margin can be increased and the wiring reliability can be improved. It becomes possible.
[0038]
-Specific embodiments-
Hereinafter, specific embodiments based on the basic outline of the present invention described above will be described. Here, a specific embodiment in which the present invention is applied to a method of forming a Cu wiring by a damascene method (here, a so-called dual damascene method) will be described in detail with reference to the drawings. In the present embodiment, a general MOS transistor is taken as an example of a semiconductor device, and the present invention is applied to the formation of the wiring structure.
[0039]
(First embodiment)
FIG. 7 is a schematic sectional view showing the method for forming the wiring structure according to the present embodiment in the order of steps.
In forming this wiring structure, a MOS transistor structure (not shown) having a gate electrode and a source / drain is formed on a silicon semiconductor substrate. The present invention is applied to a wiring structure electrically connected to, for example, a gate electrode of this MOS transistor structure.
[0040]
First, as shown in FIG. 7A, a lower layer Cu wiring 1 is formed above a silicon semiconductor substrate (not shown) by a so-called damascene method.
[0041]
Subsequently, an upper layer Cu wiring that is electrically connected to the lower layer Cu wiring 1 through the via hole is formed.
Specifically, after forming a silicon carbide film 2 serving as an etching stopper so as to cover the surface of the lower Cu wiring 1 to a film thickness of about several tens (nm), an interlayer insulating film such as an organic SOD film, here polyaryl An ether-based low dielectric constant film 3 is applied to a thickness of about several hundreds (nm), and a silicon carbide film 4 serving as a hard mask is formed to a thickness of about several tens (nm).
[0042]
Subsequently, by photolithography and subsequent etching, a portion to be a wiring pattern is first formed in the silicon carbide film 4 to form a hard mask. Subsequently, a via hole 5 is formed in the low dielectric constant film 3 so that a part of the surface of the lower layer Cu wiring 1 is exposed. At this time, the silicon carbide film 2 is left extremely thin on the lower layer Cu wiring 1 without completely exposing a part of the surface of the lower layer Cu wiring 1, that is, a state in which a part of the surface is almost exposed. You may make it become.
[0043]
Then, the low dielectric constant film 3 is etched using the silicon carbide film 4 as a hard mask to form a wiring groove 6 that follows the shape of the wiring pattern of the hard mask. Here, the etching is performed using CF gas, NH._ThreeSystem gas and N₂/ H₂This is performed as plasma etching using a system gas.
[0044]
Subsequently, as shown in FIG. 7B, a barrier metal film covering the inner walls of the wiring trench 6 and the via hole 5 is formed by the two-step sputtering of the present invention.
The two-step sputtering is performed twice in the same chamber. As the sputtering chamber, as shown in FIG. 8, a self-sputtering method or a chamber mainly using a self-sputtering method is used. In this chamber, a stage bias power source for applying an RF bias to the semiconductor substrate is connected to the substrate stage 21, and a target 22 is provided so as to face the substrate stage 21. A target power supply 24 is connected via the assembly 23. A shield 25 is provided on the side surface in the chamber, and a sputtering gas (here, Ar and N) is provided in the chamber.₂) Is provided, and an exhaust port 27 is provided.
[0045]
Specifically, first, as the first sputtering in the step (1), here, the non-bias sputtering, the DC power is 10 (kW) to 15 (kW), and the discharge pressure is 5 × 10.^-2A positive potential, for example, about 100 (V) is applied to the shield 25 at about (Pa), the Ar flow rate is set to 5 (sccm) to 50 (sccm), and sputtering is performed using a Ta target.
[0046]
Next, the second sputtering in step (2), in this case, bias sputtering is performed in the same chamber as in step (1). In this case, although the first state in the deposition mode and the second state in the etching mode coexist, the conditions in which the first state is dominant, specifically, the bias power is 350 W, and the bias application time is 10 seconds. And sputtering using a Ta target with an Ar flow rate of 5 (sccm) to 50 (sccm).
The barrier metal film 7 having a thickness of about 10 (nm) to 35 (nm) is formed by the above two-step sputtering.
[0047]
Subsequently, as shown in FIG. 7C, a Cu film 8 is deposited and formed as a seed metal film to a thickness of about 40 (nm) to 200 (nm) by a sputtering method so as to cover the barrier metal film 7. As sputtering conditions, the target power is 5 (kW) to 30 (kW), and the RF bias is 0.32 (W / cm).²) To 1.6 (W / cm²), Ar flow rate is 5 (sccm) to 50 (sccm).
In this case, the Cu film 8 may also be formed by the two-step sputtering of the present invention, like the barrier metal film 7.
[0048]
Subsequently, as shown in FIG. 7D, the current density is set to 7 (A / cm) in a copper sulfate bath by electrolytic plating using the Cu film 8 as an electrode.²) To 30 (A / cm²), The Cu film 9 is formed to have a film thickness that fills the wiring trench 6 and the via hole 5, in this case, about 500 (nm) to 2000 (nm).
[0049]
Then, as shown in FIG. 7E, the Cu films 8 and 9 and the barrier metal film 7 are polished by CMP using an organic acid slurry, so that the Cu film 8 is only in the wiring trench 6 and the via hole 5. 9 and the barrier metal film 7 are left, and the upper Cu wiring 11 is formed.
[0050]
Thus, a wiring structure in which the lower layer Cu wiring 1 and the upper layer Cu wiring 11 are electrically connected through the via hole 5 is completed. Furthermore, the damascene method described above may be repeated to form a wiring structure connected to the upper Cu wiring 11.
[0051]
Thereafter, through further formation of interlayer insulating films, via holes, wirings, etc., a MOS transistor having the wiring structure is completed.
[0052]
(Second Embodiment)
FIG. 9 is a schematic cross-sectional view illustrating the method for forming the wiring structure according to the present embodiment in the order of steps.
In forming this wiring structure, a MOS transistor structure (not shown) having a gate electrode and a source / drain is formed on a silicon semiconductor substrate. The present invention is applied to a wiring structure electrically connected to, for example, a gate electrode of this MOS transistor structure.
[0053]
First, as shown in FIG. 9A, a lower layer Cu wiring 1 is formed above a silicon semiconductor substrate (not shown) by a so-called damascene method.
[0054]
Subsequently, an upper layer Cu wiring that is electrically connected to the lower layer Cu wiring 1 through the via hole is formed.
Specifically, after forming a silicon carbide film 2 serving as an etching stopper so as to cover the surface of the lower Cu wiring 1 to a film thickness of about several tens (nm), an interlayer insulating film such as an organic SOD film, here polyaryl An ether-based low dielectric constant film 3 is applied to a thickness of about several hundreds (nm), and a silicon carbide film 4 serving as a hard mask is formed to a thickness of about several tens (nm).
[0055]
Subsequently, by photolithography and subsequent etching, a portion to be a wiring pattern is first formed in the silicon carbide film 4 to form a hard mask. Subsequently, a via hole 5 is formed in the low dielectric constant film 3 so that a part of the surface of the lower layer Cu wiring 1 is exposed. At this time, the silicon carbide film 2 is left extremely thin on the lower layer Cu wiring 1 without completely exposing a part of the surface of the lower layer Cu wiring 1, that is, a state in which a part of the surface is almost exposed. You may make it become.
[0056]
Then, the low dielectric constant film 3 is etched using the silicon carbide film 4 as a hard mask to form a wiring groove 6 that follows the shape of the wiring pattern of the hard mask. Here, the etching is performed using CF gas, NH._ThreeSystem gas and N₂/ H₂This is performed as plasma etching using a system gas.
[0057]
Subsequently, as shown in FIG. 9B, a barrier metal film that covers the inner walls of the wiring trench 6 and the via hole 5 is formed by the three-step sputtering of the present invention. In the three-step sputtering, three times of sputtering are continuously performed in the same chamber, the substrate temperature during sputtering is −30 ° C. to 200 ° C., and the pressure in the chamber is 5.0 × 10.^-3It is desirable that Pa to 1.0 Pa and the distance between the semiconductor substrate and the cathode electrode in the chamber be 150 mm or more.
[0058]
Specifically, first, the first sputtering, non-bias or bias sputtering in the step (1) is performed. In this case, a Ta target is used, the target power is 5 (kW) to 30 (kW), and the RF bias is 0 (W / cm).²) To 0.96 (W / cm²), Ar flow rate is set to 5 (sccm) to 50 (sccm), and sputtering is performed to a film thickness of about 10 (nm) to 20 (nm).
[0059]
Next, the second sputtering in step (2), in this case, bias sputtering is performed in the same chamber as in step (1). Here, a Ta target is used, the target power is 5 (kW) to 30 (kW), and the RF bias is 0.96 (W / cm).²) To 1.6 (W / cm²), The Ar flow rate is set to 5 (sccm) to 50 (sccm), and sputtering is performed to a film thickness (−5 (nm) to 5 (nm)) with local etching.
[0060]
The third sputtering, non-bias or bias sputtering in step (3) is performed. In this case, a Ta target is used, the target power is 5 (kW) to 30 (kW), and the RF bias is 0 (W / cm).²) To 0.96 (W / cm²), Ar flow rate is set to 5 (sccm) to 50 (sccm), and sputtering is performed to a film thickness of about 5 (nm) to 10 (nm).
The barrier metal film 7 having a film thickness of about 10 (nm) to 35 (nm) is formed by the above three-step sputtering.
[0061]
Subsequently, as shown in FIG. 9C, a Cu film 8 is deposited and formed as a seed metal film to a thickness of about 40 (nm) to 200 (nm) by a sputtering method so as to cover the barrier metal film 7. As sputtering conditions, the target power is 5 (kW) to 30 (kW), and the RF bias is 0.32 (W / cm).²) To 1.6 (W / cm²), Ar flow rate is 5 (sccm) to 50 (sccm).
In this case, the Cu film 8 may also be formed by the two-step sputtering of the present invention, like the barrier metal film 7.
[0062]
Subsequently, as shown in FIG. 9D, the current density is set to 7 (A / cm) in a copper sulfate bath by electrolytic plating using the Cu film 8 as an electrode.²) To 30 (A / cm²), The Cu film 9 is formed to have a film thickness that fills the wiring trench 6 and the via hole 5, in this case, about 500 (nm) to 2000 (nm).
[0063]
Then, as shown in FIG. 9 (e), the Cu films 8 and 9 and the barrier metal film 7 are polished by CMP using an organic acid slurry, and the Cu film 8 only in the wiring trench 6 and the via hole 5. 9 and the barrier metal film 7 are left, and the upper Cu wiring 11 is formed.
[0064]
Thus, a wiring structure in which the lower layer Cu wiring 1 and the upper layer Cu wiring 11 are electrically connected through the via hole 5 is completed. Furthermore, the damascene method described above may be repeated to form a wiring structure connected to the upper Cu wiring 11.
[0065]
Thereafter, through further formation of interlayer insulating films, via holes, wirings, etc., a MOS transistor having the wiring structure is completed.
[0066]
Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.
[0067]
(Appendix 1) A method of forming a wiring structure through a base film in an insulating film above a substrate,
When forming the base film by sputtering,
A first sputtering step performed under conditions depending on a state in which the material of the base film is deposited;
A condition in which the first state in which the material of the base film is deposited and the second state in which the deposited material of the base film is etched are mixed, and the first state is stronger than the second state. A second sputtering step performed in
A method for forming a wiring structure comprising:
[0068]
(Supplementary note 2) The method for forming a wiring structure according to supplementary note 1, wherein the first sputtering step is performed with a low bias, and the second sputtering step is performed with a high bias in a short time.
[0069]
(Additional remark 3) The formation method of the wiring structure of Additional remark 2 characterized by performing said 1st sputtering process on the conditions of no bias application.
[0070]
(Additional remark 4) The formation method of the wiring structure of Additional remark 1 or 2 characterized by performing the said 1st and 2nd sputtering process continuously in the same chamber.
[0071]
(Supplementary Note 5) A sputtering apparatus having a chamber structure mainly composed of a self-sputtering method or a self-sputtering method and having a positive electrode having a positive potential with respect to the side surface of the chamber shield. The method for forming a wiring structure according to any one of appendices 1 to 4, wherein the wiring structure is formed by using the wiring structure.
[0072]
(Supplementary note 6) The supplementary notes 1 to 5, wherein the first and second sputtering steps are performed using a sputtering apparatus in which a substrate holding means for holding the substrate has a mechanism for applying an RF bias. The method for forming a wiring structure according to any one of the above.
[0073]
(Appendix 7) The wiring structure has a damascene structure in which connection holes and wiring grooves formed in the insulating film are filled with a material containing copper through the base film. 7. A method for forming a wiring structure according to any one of 6 above.
[0074]
(Supplementary Note 8) The base film includes at least one selected from a refractory metal, a nitrogen compound of a refractory metal, and a silicon compound, and has a diffusion preventing function and an adhesion function of the material containing copper. The method for forming a wiring structure according to appendix 7, wherein:
[0075]
(Additional remark 9) The said base film contains copper at least, and functions as a seed layer at the time of plating-forming the material containing the said copper, The formation method of the wiring structure of Additional remark 7 or 8 characterized by the above-mentioned.
[0076]
(Supplementary Note 10) A method of forming a wiring structure through a base film in an insulating film above a substrate,
When forming the base film by sputtering,
A first sputtering step performed under conditions for depositing the material of the base film;
A condition in which the first state in which the material of the base film is deposited and the second state in which the deposited material of the base film is etched are mixed, and the second state is stronger than the first state. A second sputtering step performed in
A third sputtering step performed under conditions for depositing the material of the base film;
A method for forming a wiring structure comprising:
[0077]
(Supplementary note 11) The method for forming a wiring structure according to supplementary note 10, wherein the first and third sputtering steps are performed with a low bias, and the second sputtering step is performed with a high bias.
[0078]
(Supplementary note 12) The method for forming a wiring structure according to supplementary note 10, wherein the first and third sputtering steps are performed under a condition in which no bias is applied.
[0079]
(Supplementary Note 13) The supplementary note is characterized in that the first sputtering step is performed under a condition in which no bias is applied, and the third sputtering step is performed under a condition in which the first state is stronger than the second state. The method for forming the wiring structure according to 10.
[0080]
(Supplementary Note 14) The supplementary note is characterized in that the first sputtering step is performed under a condition that the first state is stronger than the second state, and the third sputtering step is performed under a condition in which no bias is applied. The method for forming the wiring structure according to 10.
[0081]
(Supplementary note 15) The method for forming a wiring structure according to supplementary note 10, wherein the first and third sputtering steps are performed under the condition that the first state is stronger than the second state.
[0082]
(Supplementary note 16) The method for forming a wiring structure according to any one of supplementary notes 10 to 15, wherein the first, second, and third sputtering steps are continuously performed in the same chamber.
[0083]
(Supplementary Note 17) The base film is at least one selected from Ta, Ti, W, Zr, at least one nitride selected from Ta, Ti, W, Zr, or Ta, Ti, W, Zr. 17. The method for forming a wiring structure according to any one of appendices 10 to 16, comprising at least one compound selected from the above as a material.
[0084]
(Supplementary note 18) The method for forming a wiring structure according to any one of supplementary notes 10 to 17, wherein the base film is formed at a substrate temperature of -30 ° C to 200 ° C.
[0085]
(Supplementary note 19) The base film is subjected to a chamber internal pressure of 5.0 × 10.^-3The method for forming a wiring structure according to any one of appendices 10 to 18, wherein the wiring structure is formed at Pa to 1.0 Pa.
[0086]
(Supplementary note 20) The wiring structure according to any one of supplementary notes 10 to 19, wherein when forming the base film, a distance between the substrate and the cathode electrode in the chamber is 150 mm or more. Method.
[0087]
(Appendix 21) The wiring structure has a damascene structure in which connection holes and wiring grooves formed in the insulating film are filled with a material containing copper through the base film. 21. The method for forming a wiring structure according to any one of 20 above.
[0088]
(Supplementary Note 22) Etching the base film material deposited on the bottom portion in the second sputtering step under the condition that the base film material is deposited on the bottom portion of the connection hole in the first sputtering step. 22. The method for forming a wiring structure according to appendix 21, wherein the third sputtering step is performed under conditions such that the material for the base film is deposited on the bottom portion.
[0089]
【The invention's effect】
According to the method for forming a wiring structure of the present invention, it is possible to surely obtain a sufficient coverage (coverage) of a barrier metal film corresponding to a high aspect ratio of a via hole, and further miniaturization and heightening of a semiconductor device. The wiring reliability and the initial yield can be improved while supporting the integration.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view for explaining a configuration of a two-step sputtering according to the present invention.
FIG. 2 is a characteristic diagram showing an initial yield of chain resistance in the two-step sputtering of the present invention.
FIG. 3 is a characteristic diagram showing wiring reliability in two-step sputtering according to the present invention.
FIG. 4 is a schematic diagram showing the results of examining the thicknesses of barrier metal films at the shoulder A, the side wall B, and the bottom C of the inner wall of the via hole.
FIG. 5 is a schematic cross-sectional view for explaining the configuration of the three-step sputtering of the present invention.
FIG. 6 is a schematic view showing a combination of barrier metal film materials in the three-step sputtering of the present invention.
FIG. 7 is a schematic cross-sectional view showing the method of forming the wiring structure according to the first embodiment in the order of steps.
FIG. 8 is a schematic diagram showing a schematic configuration of a sputtering chamber used in various embodiments.
FIG. 9 is a schematic cross-sectional view showing a method of forming a wiring structure according to a second embodiment in the order of steps.
FIG. 10 is a schematic cross-sectional view for explaining the configuration of a conventional one-step sputtering.
FIG. 11 is a schematic cross-sectional view for explaining the configuration of a conventional two-step sputtering.
[Explanation of symbols]
1,101 Lower layer Cu wiring
2,4 Silicon carbide film
3 Low dielectric constant film
5,103 Via hole
6,104 Wiring groove
7 Barrier metal film
8,9 Cu film
11 Upper layer Cu wiring
102 Interlayer insulation film
106 Cu material
107,108 Void

Claims (5)

A method of forming a wiring structure having a wiring material and a barrier metal film for preventing diffusion of the wiring material in a connection hole disposed in an insulating film above a substrate,
When forming the barrier metal film by sputtering,
A first sputtering step performed under the condition of no bias application ;
After the first sputtering step, a first state in which the material of the barrier metal film is deposited and a second state in which the deposited material of the barrier metal film is etched coexist at the bottom of the connection hole. And a second sputtering step of 3 to 12 seconds performed by applying a bias so that the first state is stronger than the second state. The wiring structure according to claim 1, characterized in that it comprises a damascene structure formed by filling with the wiring material containing copper the formed insulating film was the connection hole and the wiring groove through the barrier metal film A method of forming a wiring structure as described in 1. A method of forming a wiring structure having a wiring material and a barrier metal film for preventing diffusion of the wiring material in a connection hole disposed in an insulating film above a substrate,
When forming the barrier metal film by sputtering,
A first sputtering step ;
After the first sputtering step, a first state in which the material of the barrier metal film is deposited and a second state in which the deposited material of the barrier metal film is etched coexist at the bottom of the connection hole. A second sputtering step that is performed under a condition that the second state is stronger than the first state;
Look including a third sputtering step performed after the second sputtering step,
The first and third sputtering steps include
Performing the first and third sputtering steps under the condition of no bias applied;
The first sputtering step is performed under a condition in which no bias is applied, and the third sputtering step is performed under a condition where the first state is stronger than the second state,
Performing the first sputtering step under a condition in which the first state is stronger than the second state, and performing the third sputtering step under a condition in which no bias is applied,
A method of forming a wiring structure, wherein the first and third sputtering steps are each performed under a condition in which the first state is stronger than the second state . The wiring structure according to claim 3, characterized in that it comprises a damascene structure formed by filling with the wiring material containing copper said insulating the connection holes and the wiring grooves formed in the film through the barrier metal film A method of forming a wiring structure as described in 1. The first sputtering step is performed under conditions for depositing the material of the barrier metal film on the bottom portion of the connection hole, and the second sputtering step is performed under conditions for etching the material of the barrier metal film deposited on the bottom portion. 5. The method of forming a wiring structure according to claim 4 , wherein the third sputtering step is performed under the condition that the material of the barrier metal film is deposited on the bottom portion.

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