JP4230468B2 - Inductance element formed on a semiconductor substrate - Google Patents

Description

  The present invention relates to an inductance element formed on a semiconductor substrate that constitutes an integrated circuit, and more particularly to an inductance element having a structure with low loss and low inductance reduction.

  In recent years, downsizing of mobile communication devices such as mobile phones has been promoted. There is an increasing demand for configuring a high-frequency circuit used in such a small portable communication device with an integrated circuit using a silicon semiconductor. A high-frequency circuit requires an inductance element such as a coil or a transformer in addition to a transistor, a resistor, and a capacitor. Therefore, it is necessary to form an inductance element on the silicon semiconductor substrate together with an integrated circuit using transistors, resistors, and the like.

  Such an inductance element is generally realized by forming a strip-like conductive film such as aluminum in a spiral shape or a winding shape on an insulating film formed on the surface of a semiconductor substrate. However, in such a configuration, there is a semiconductor substrate in the immediate vicinity of the inductance element, and an eddy current that prevents a change in magnetic flux generated when a current is passed through the inductance element is generated in the semiconductor substrate, resulting in loss of characteristics. Are known.

  That is, when the band-shaped conductive layer formed in a winding shape is considered as a primary coil in a transformer, the semiconductor substrate containing impurities itself has a low resistance value, and thus acts like a short-circuited secondary coil in a high-frequency region. The loss due to the presence of the secondary coil is particularly noticeable in the high frequency region, and proposals have been made to prevent the generation of such eddy currents in the semiconductor substrate. For example, Patent Document 1 shows that a plurality of PN junctions are formed on the surface of a silicon semiconductor substrate, and eddy currents are suppressed by a depletion layer generated at the junctions. That is, the eddy current path on the substrate surface is divided by a plurality of depletion layers to suppress the eddy current. Alternatively, in Patent Document 2, by forming a plurality of PN junctions on the surface of a silicon semiconductor substrate and further applying a controlled reverse bias voltage to the PN junctions, the capacitance due to the depletion layer formed at the junctions is increased. It has been proposed to form LC composite circuit elements by using them. This known example also shows that the generation of eddy currents can be suppressed by the depletion layer formed on the substrate surface.

  FIG. 6 is a diagram showing the structure of such a known inductance element. An N-type impurity region 14 is formed on the surface of the P-type semiconductor substrate 10, and a plurality of PN junctions are formed on the substrate surface. A spiral belt-like conductive film 16 is formed on the insulating film 12 formed on the surface of the substrate 10. One end 16 A of the strip-like conductive film 16 is connected to a wiring (not shown), and the other end 16 B is connected to a lower wiring 18 formed in the insulating film 12. When a current is passed in the direction of the arrow 22 in the figure from one end to the other end of the strip-like conductive film 16, a magnetic flux is thereby generated in the spiral wiring.

In the configuration shown in FIG. 6, since a depletion layer is formed in a plurality of PN junctions, a large number of depletion layers are formed on the surface side of the substrate 10, and the magnetic flux generated by the inductance element made of the strip-like conductive film 16 is reduced. The resistance of the eddy current generated in the semiconductor substrate 10 can be increased, the eddy current can be suppressed, and the loss and inductance reduction due to the eddy current can be prevented.
JP 7-183468 A JP-A-7-235640

  However, in the above conventional example, only a plurality of depletion layers are formed on the surface of the semiconductor substrate 10, and eddy currents are still generated on the substrate surface. Further, since there is a semiconductor region that is not depleted between the primary coil of the belt-like conductive film and the secondary coil of the eddy current in the substrate, the mutual inductance between the coils is not low. Although it is conceivable that the entire surface region of the semiconductor substrate is depleted, when the impurity region 14 having a conductivity type opposite to that of the substrate is formed on the surface of the silicon semiconductor substrate 10 on which the integrated circuit is actually formed, fine processing is required. Naturally there is a limit. Therefore, it is difficult to form a plurality of PN junctions close enough to completely deplete the substrate surface. Furthermore, since the semiconductor substrate 10 on which the integrated circuit is formed itself has a high impurity concentration, the width of the depletion layer that naturally extends between the PN junctions formed on the surface is not so large. As a result, only a thin depletion layer is formed along the PN junction. Therefore, the substrate surface is not completely depleted, and as described above, the conventional example has only an effect of increasing the resistance in the region where the eddy current is generated.

  Furthermore, as shown in the equivalent circuit diagram of FIG. 7, the impurity concentration of the substrate 10 is relatively high, and the resistance Rs in the substrate is relatively low. Similarly, the resistance rn of the N-type impurity region 14 formed on the surface is relatively low. For this reason, the capacitance C formed by the PN junction is electrically connected to the inductance element L and affects the characteristics of the inductance element.

  As described above, the inductance element by the strip-like conductive film 16 becomes the primary coil, and the path of the eddy current in the substrate becomes the secondary coil. In order to eliminate the loss of the inductance element and improve the characteristics, It is necessary to increase the insulation of the coil to reduce the effective mutual inductance between the two coils.

  Further, as shown in FIG. 5, by passing a current 22 through the strip-shaped conductive film 16, an eddy current 20 is generated not only in the substrate but also in the strip-shaped conductive film 16 itself. In particular, since a large amount of magnetic flux is generated in the strip-shaped conductive film 16 wound inside, generation of the eddy current 20 is increased. Such eddy currents also cause loss and are required to be avoided. In that case, it is conceivable to reduce the wiring width of the strip-like conductive film 16, but if the wiring width is narrowed, the resistance increases and the inductance component of itself increases, which is not preferable.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an inductance element having a structure in which insulation between a band-shaped conductive film formed on the surface of a semiconductor substrate and a region in the semiconductor substrate is further increased.

  Another object of the present invention is to provide an inductance element having a structure in which eddy currents generated in a strip-like conductive film itself formed on the surface of a semiconductor substrate are suppressed.

  In order to achieve the above object, according to the first aspect of the present invention, a plurality of PN junctions are formed on the surface of a semiconductor substrate under a winding band-like conductive film constituting an inductance element, and a reverse bias is applied to the PN junctions. A voltage is applied to completely deplete the substrate surface. By applying a reverse bias to the PN junction, even if the impurity concentration on the surface of the substrate is high and adjacent PN junctions are separated to some extent, the extension of the depletion layer can be increased, and it can be completely depleted. become.

  Furthermore, in order to achieve the above object, the second invention provides a thick insulating region formed by an oxygen ion implantation method on the surface of the semiconductor substrate under the wound strip-shaped conductive film constituting the inductance element. Form. This insulating region has a larger film thickness than a thin insulating film for wiring formed on a normal integrated circuit element region. Due to the presence of the thick insulating region, the effective mutual inductance between the primary coil of the inductance element and the secondary coil due to the eddy current in the semiconductor substrate can be reduced. In addition, since more reliable insulation can be obtained than in the case of complete depletion using a plurality of PN junctions, the loss of the inductance element is small.

  Furthermore, in order to achieve the above object, in the third invention, a slit extending in the winding direction is formed in the strip-shaped conductive film formed in a winding shape, and a plurality of strips extending in the winding direction are formed in the strip-shaped conductive film. Use parallel wiring. By adopting such a configuration, it is possible to eliminate the path of eddy current generated in the strip-shaped conductive film, suppress eddy current, and suppress characteristic loss.

  Furthermore, in order to achieve the above object, according to the fourth aspect of the present invention, a strip-shaped conductive film formed in a winding shape is anisotropic in which the conductivity in the winding direction is higher than the conductivity in the direction perpendicular to the winding direction. It is made of a material having conductive conductivity. For example, by using an oxide superconductor or an organic conductive material, it is possible to form a strip-shaped conductive film having high conductivity in the winding direction and low conductivity in the direction perpendicular to the winding direction. In the case of such a material, an eddy current generated inside can be suppressed while preventing an increase in resistance in the winding direction of the belt-like conductive film.

  According to the present invention, eddy current generated in an inductance element can be suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

  FIG. 1 is a structural diagram of an inductance element according to an embodiment. In this example, a plurality of N-type impurity regions 14 are formed on the surface of a P-type semiconductor substrate 10, and a plurality of PN junctions are formed on the surface. Further, an N-type buried impurity region 30 having a higher concentration is formed inside the semiconductor substrate 10. The buried impurity region 30 can be formed by, for example, a high energy ion implantation method. The buried impurity region 30 is led to the substrate surface by an N-type impurity region 32 formed simultaneously with the N-type impurity region 14.

  A reverse bias voltage V is applied to the PN junction between the semiconductor substrate 10 and the N-type impurity cool air 14. The reverse bias voltage V is such a voltage that a depletion layer extending from the PN junction on the substrate surface is connected.

  FIG. 2 is a detailed cross-sectional view when a reverse bias voltage is applied to the inductance element of FIG. Like the impurity concentration distribution shown on the right side of the figure, the impurity concentration distribution 14N of the N-type impurity region 14 has a low concentration on the substrate surface and a high concentration toward the inside of the substrate. Further, the impurity concentration distribution 30N of the buried impurity region 30 is higher than that of the N-type impurity region 14 as shown in the drawing.

  The reverse bias voltage V applied between the PN junctions in the surface region of the substrate 10 is transmitted from the conductive layer 33 on the substrate surface through the N-type impurity region 32 and the N-type buried impurity region 30 to the inductance element. Applied to the N-type impurity region 14 forming the lower PN junction. Therefore, the depletion layer extending from the PN junction spreads as shown by the broken line. That is, the extension of the depletion layer on the surface side of the substrate 10 is large, the depletion layers extending from the adjacent PN junctions are connected, and the substrate surface is completely depleted. Further, the extension of the depletion layer extending from the PN junction inside the substrate having a high impurity concentration is less than that on the substrate surface. Accordingly, the voltage applied from the embedded impurity region 30 inside the substrate is effectively applied to the substrate surface via the non-depletion region (N-type semiconductor region) in the vertical direction of the impurity region 14, and the substrate surface is completely depleted. Can be realized.

  In the example of FIG. 1, a plurality of N-type impurity regions 14 are formed on the surface of the P-type semiconductor substrate 10 in a plan view. However, the present invention is not limited to such a shape. Or the shape which has arrange | positioned the micro area | region in the matrix form may be sufficient. If the structure is such that more PN junctions terminate on the substrate surface, the substrate surface is likely to be completely depleted by the depletion layer extending from the PN junction.

  In the present embodiment, the wound belt-like conductive film 16 constituting the inductance element is formed on the insulating film 12 on the region where the PN junction is formed. As shown in FIG. 1, the strip-like conductive film 16 has a slit 34 extending in the winding direction. Therefore, the strip-shaped conductive film 16 has a plurality of parallel-connected wiring structures extending in the winding direction.

  By forming the slit 34 in the strip-shaped conductive film 16, even when a current is passed between the both ends 16A and 16B of the strip-shaped conductive film 16, eddy currents generated in the strip-shaped conductive film 16 can be reduced. The strip-shaped conductive film 16 constituting the inductance element needs to have a certain width so as not to have an inductance component. However, if the line width is too large, a large amount of magnetic flux penetrates especially in the inner periphery of the winding shape, and an eddy current is generated in the strip-like conductive film 16. Therefore, in this embodiment, a slit 34 is formed in the strip-like conductive film 16 to suppress the eddy current. A path through which the eddy current flows in the width direction of the strip-shaped conductive film 16 disappears, and the eddy current generated correspondingly becomes only a smaller region. Even if the slit 34 is formed, the strip-like conductive film 16 is connected in parallel, so that the resistance in the winding direction does not decrease.

  It is effective to form the slit 43 only in the winding portion on the inner periphery of the wound belt-like conductive film 16. Since more magnetic flux penetrates in the inner peripheral portion than the outer periphery of the winding, eddy current can be effectively suppressed only by forming a slit in the strip-like conductive film 16 in that portion.

  FIG. 3 is a cross-sectional view of an inductance element according to another embodiment. FIG. 3 shows a strip-like conductive film 16 constituting an inductance element and a MOS transistor 42 constituting an integrated circuit. The normal MOS transistor 42 is led out on the N-type source / drain region 43 formed on the surface of the P-type substrate, the gate electrode 44 formed on the gate oxide film, and the insulating film 12 formed on the substrate surface. The wiring layer 45 and the like are included. The insulating film 12 is a silicon oxide film formed by, for example, a CVD method, but its film thickness is about 5000 angstroms at the whole.

  On the other hand, a thick insulating region 40 is formed from the surface of the substrate 10 to the inside under the region where the strip-like conductive film 16 constituting the inductance element is formed. The insulating region 40 is formed by a method used for forming an SOI (Silicon on Insulator) structure on a semiconductor substrate called, for example, the Simox method. That is, according to this simox method, a thick region extending inward from the surface of the semiconductor silicon substrate can be changed to the silicon oxide region 40 by implanting oxygen ions into the substrate surface. Therefore, the insulating region 40 has a film thickness of, for example, 10,000 angstroms or more, and can be made considerably thicker than the film thickness of the insulating film 12 for wiring on a normal integrated circuit element.

  In this way, by forming the thick insulating region 40 extending from the surface of the substrate 10 to the inside in addition to the insulating film 12 for wiring under the strip-like conductive film 16 constituting the inductance element, It is completely insulated from the semiconductor region inside the substrate immediately below. Further, the distance is increased, and the mutual inductance between the primary coil formed of the strip-like conductive film 16 and the secondary coil generated by the eddy current generated inside the substrate can be reduced. In addition, the generation of eddy current in the substrate itself is suppressed.

  4 is a partial cross-sectional perspective view of the inductance element of FIG. As shown in FIG. 4, a thick insulating region 40 is formed under the strip-like conductive film 16. Further, a plurality of slits 34 are formed in the inner peripheral portion of the winding of the strip-like conductive film 16 of FIG. By providing a plurality of slits 34 in the inner peripheral portion of the winding having a higher magnetic flux density generated when a current flows through the strip-shaped conductive film 16, eddy currents generated in the strip-shaped conductive film 16 are more efficiently suppressed. be able to.

FIG. 5 is a plan view showing the structure of still another inductance element. In this example, in order to suppress the eddy current generated in the strip-shaped conductive film constituting the inductance element, the strip-shaped conductive film is made to have an anisotropic conductivity in which the conductivity in the winding direction is larger than the conductivity in the vertical direction. It is made of a material with a rate. Such a material is, for example, Y ₂ Ba ₄ Cu ₇ O ₁₅ or LaBa ₂ Cu ₃ O ₇ which is a ceramic oxide superconductor. Alternatively, another material is an organic conductive material such as polyacetylene. These materials are formed in a certain direction by, for example, forming a thin film of these materials by a sputtering method or a reactive vapor deposition method and then processing them into an arbitrary shape by a chemical etching or an ion etching method. Can be made larger than the conductivity in the direction perpendicular thereto.

  In the example shown in FIG. 5, the wound belt-like conductive film is made up of the lower layer wirings 161, 163, 165, 167 in the horizontal direction in the figure and the upper layer wirings 160, 162, 164, 166 in the vertical direction in the figure. And consist of First, an anisotropic conductive material layer for a lower layer wiring is formed by the above-described method, and etched into a horizontal pattern in the figure to form lower layer wirings 161, 163, 165, and 167. Furthermore, an insulating layer is formed thereon, a via hole for connecting the upper layer and the lower layer is formed, an anisotropic conductive material layer for upper wiring is further formed, and etched into a vertical pattern in the figure, Upper layer wirings 160, 162, 164, 166 are formed. As a result, a wound belt-like conductive film from one end 16A to the other end 16B is formed.

  The lower wirings 161, 163, 165, and 167 have a higher conductivity in the winding direction indicated by an arrow (horizontal direction in the drawing) than in a direction perpendicular thereto. Similarly, the upper wirings 160, 162, 164, and 166 have higher conductivity in the winding direction indicated by arrows (vertical direction in the figure) than in the direction perpendicular thereto. Therefore, the strip-shaped conductive film having inductance shown in FIG. 5 can suppress the eddy current generated in itself without sacrificing the conductivity in the winding direction.

  As described above, according to the present invention, in the inductance element formed on the semiconductor substrate, a plurality of PN junctions are formed on the substrate surface under the strip-like conductive film constituting the inductance element, and the reverse bias is applied to the PN junction. Since a voltage is applied so that the substrate surface is completely depleted, eddy currents generated on the substrate surface can be suppressed. Furthermore, it is possible to reduce the mutual inductance between the primary coil due to the strip-like conductive film on the substrate surface and the secondary coil due to the eddy current generated inside the substrate. Therefore, the loss of the characteristic of the inductance element can be reduced.

  According to the present invention, in the inductance element formed on the semiconductor substrate, a thick insulating region is formed inside the substrate surface under the strip-shaped conductive film constituting the inductance, so that eddy currents generated in the substrate are suppressed. be able to. In addition, due to the thick insulating region, the mutual inductance between the primary coil due to the strip-like conductive film on the substrate surface and the secondary coil due to the eddy current generated inside the substrate can be reduced. Therefore, the loss of the characteristic of the inductance element can be reduced.

  According to the present invention, in the inductance element formed on the semiconductor substrate, since the slit is formed in the strip-shaped conductive film constituting the inductance, the eddy current generated in the strip-shaped conductive film itself can be suppressed. Therefore, the loss of the characteristic of the inductance element can be reduced.

  Furthermore, according to the present invention, in the inductance element formed on the semiconductor substrate, the strip-shaped conductive film constituting the inductance has an anisotropic conductivity in which the conductivity in the winding direction is higher than the conductivity in the direction perpendicular thereto. Since it is made of a material, eddy currents generated in the strip-shaped conductive film itself can be suppressed. Therefore, the loss of the characteristic of the inductance element can be reduced.

It is a structure figure of the inductance element of the example of an embodiment. FIG. 2 is a detailed cross-sectional view when a reverse bias voltage is applied to the inductance element of FIG. 1. It is sectional drawing of the inductance element of another embodiment. FIG. 4 is a partial cross-sectional perspective view of the inductance element of FIG. 3. It is a top view which shows the structure of another inductance element. It is a figure which shows the structure of the inductance element of a well-known example. FIG. 7 is an equivalent circuit diagram of FIG. 6.

Explanation of symbols

10 P-type semiconductor substrate 12 Insulating film 14 for wiring N-type impurity region 16 Winding strip-like conductive film 20 Eddy current 30 N-type buried impurity region 32 N-type impurity region 34 Slit 40 Thick insulating region 160 167 Wiring film having anisotropic conductivity

Claims (2)

In an inductance element formed on a semiconductor substrate,
An insulating film formed on the surface of the semiconductor substrate;
A wound belt-shaped conductive film formed on the insulating film and constituting the inductance element;
The inductance element according to claim 1, wherein the strip-shaped conductive film is formed of a material having a conductivity anisotropy higher in conductivity in the winding direction than in a direction perpendicular to the winding direction. The inductance element according to claim 1 , wherein the strip-shaped conductive film includes an oxide superconductor or an organic conductive material.

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