JP4230307B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to an insulating gate type transistor (TFT) formed on an insulating surface such as an insulating material such as glass or a material in which an insulating film such as silicon oxide is formed on a silicon wafer, and a method for manufacturing the same. The present invention is particularly effective for a TFT formed on a glass substrate having a glass transition point (also referred to as strain temperature or strain point) of 750 ° C. or lower. The semiconductor device according to the present invention is used for an active matrix such as a liquid crystal display, a driving circuit such as an image sensor, or a three-dimensional integrated circuit.

  2. Description of the Related Art Conventionally, it is widely known that a TFT (Thin Film Transistor) is formed for the purpose of driving an active matrix type liquid crystal display device or an image sensor. In particular, recently, due to the necessity of high-speed operation, a crystalline silicon TFT having higher electric field mobility has been developed in place of an amorphous silicon TFT using amorphous silicon as an active layer. However, when more advanced characteristics are required, a structure (such as a salicide structure such as a salicide structure) that reduces the sheet resistance of the portion by configuring the source / drain with silicide as used in semiconductor integrated circuit technology. H. Kaneko et al., IEEE Trans. Electron Devices, ED-33, 1702 (1986)).

However, unlike the known semiconductor integrated circuit technology, the TFT has many problems to be solved. In particular, since the element is formed on the insulating surface and reactive ion anisotropic etching cannot be performed sufficiently, there is a great restriction that a fine pattern cannot be formed.
FIG. 6 shows a cross-sectional view of a typical process for producing a salicide used up to now. First, a base film 602 is formed on a substrate (which may be glass or a silicon wafer) 601, and an active layer is formed using crystalline silicon 603. Then, an insulating film 604 is formed on the active layer with a material such as silicon oxide. (Fig. 6 (A))

  Next, the gate electrode 605 is formed of polycrystalline silicon (doped with an impurity such as phosphorus), tantalum, titanium, aluminum, or the like. Further, an impurity element (phosphorus or boron) is introduced by means such as ion doping using the gate electrode as a mask, and an impurity region 606 is formed in the active layer 603 in a self-aligning manner. The active layer region under the gate electrode into which no impurity is introduced becomes a channel formation region. (Fig. 6 (B))

Next, an insulating film 607 such as silicon oxide is formed by means of plasma CVD, APCVD or the like (FIG. 6C), and this is anisotropically etched, so that the side wall 608 is adjacent to the side surface of the gate electrode. Form. (Fig. 6 (D))
Then, a metal film for forming a silicide such as titanium, chromium, tungsten, molybdenum, or the like is formed over the entire surface (FIG. 6E), and this is reacted with the impurity region 606 to form a silicide region 610. Since the silicide is not formed in the impurity region 606 at the lower portion (width x) of the side wall, it becomes a normal source / drain 611. (Fig. 6 (F))
Finally, an interlayer insulator 612 is formed, contact holes are formed in the source / drain regions through the interlayer insulator, and wiring / electrodes 613 connected to the source / drain are formed of a metal material such as aluminum. (Fig. 6 (G))

The above method follows the salicide fabrication process in the conventional semiconductor integrated circuit as it is, and is a process that is difficult to apply to the TFT fabrication process on the glass substrate as it is or is not preferable in terms of productivity. There is.
First, the active layer surface must be etched after doping. It is known that the thinner the active layer of the TFT, the better characteristics can be obtained. Therefore, when forming the side wall 608 in the step (D) of FIG. 6, it is necessary to pay attention to overetching of the active layer.

  However, since the thickness of the active layer is 150 nm or less, preferably 80 nm or less, the thickness of the insulating film 607 for forming the side wall needs to be the same as that of the gate electrode 605. It is 300 to 800 nm, and some over-etching is inevitable. In addition, an active layer doped with impurities (doped silicon) is much easier to etch than intrinsic silicon. Therefore, under normal conditions, there has been a problem that the active layer is also greatly etched during the formation of the side wall, or cannot be etched with good reproducibility.

Second, it is difficult to form the side wall. The insulating film 607 has a thickness of 500 to 2000 nm. Usually, since the thickness of the base film 602 provided on the substrate is 100 to 300 nm, the base film is often mistakenly etched in this etching process, and the substrate is often exposed, resulting in a decrease in yield. . In particular, a glass substrate used for manufacturing a TFT contains many elements harmful to a silicon semiconductor, and thus it is necessary to avoid such over-etching.
In addition, it is difficult to finish the width of the side wall uniformly. This is because, in plasma dry etching such as reactive ion etching (RIE), unlike the silicon substrate used in the semiconductor integrated circuit, the substrate surface is insulative, so that it is difficult to delicately control the plasma. It is.
An object of the present invention is to provide a method for forming a salicide structure by solving the above problems and further simplifying the process.

The present invention is characterized in that silicide is formed without using a side wall as used conventionally. That is, the present invention is basically based on the source / drain doping after forming a metal film for forming silicide.
The first aspect of the present invention is: (A) a semiconductor active layer on an insulating surface, a first insulating film on the active layer, and a gate electrode material film formed on the first insulating film by an anodizable material. (B) A step of selectively providing a mask film on the gate electrode material, and etching the gate electrode material using the mask film to form a gate electrode. (C) Electrolytically forming the gate electrode. A step of forming a porous first anodic oxide mainly on a side surface of the gate electrode by applying a current in the solution; and (D) a step of removing the mask film. (E) an electrolytic solution on the gate electrode. Forming a barrier type second anodic oxide on the side and top surfaces of the gate electrode by applying a current therein (F) using the first anodic oxide as a mask, the first insulating film Etching (G) a step of selectively removing the first anodic oxide; and (H) covering the gate electrode and the gate insulating film, exposing the surface of the active layer and simultaneously forming the gate insulating film. Step of forming a metal film for forming silicide (I) Step of selectively introducing N-type or P-type impurity element into the active layer through the metal film using the gate electrode and the gate insulating film as a mask And (J) a step of selectively forming a silicide region in the active layer by selectively reacting the metal coating with the active layer. (K) removing the metal coating that has not reacted in the step (J). Process.

Of these, the order cannot be changed up to the steps (A) to (H), but the steps (I) to (K) can be changed, and the following two types of configurations are possible by combining them. . That is,
First configuration Step I → Step J → Step K
Second configuration Step J → Step I → Step K
It is. Here, in the first configuration, it is possible to activate the N-type or P-type impurity doped in the step I in the step J, but in the second configuration, between the step I and the step K. Alternatively, it is desirable to provide a separate activation step after the step K.
In the step (J) or after the step, the N-type or P-type impurity may be activated by irradiating with a laser or equivalent intense light. The step (J) may be performed by thermal annealing at 300 to 500 ° C.

  In the first aspect of the present invention, the barrier type anodic oxide is generally an anodic oxide obtained by gradually increasing the applied voltage in a substantially neutral electrolytic solution, and is dense and has a high withstand voltage. On the other hand, the porous anodic oxide is an anodic oxide obtained by performing anodic oxide formation and local etching in parallel. Generally, in an acidic electrolyte having a hydrogen ion concentration pH of less than 2, It is obtained by applying a constant low voltage.

  In particular, so-called barrier type anodic oxide is difficult to etch, whereas porous type anodic oxide is selectively etched by an etchant such as phosphoric acid. For this reason, it can be processed without giving any damage (damage) to other materials constituting the TFT, for example, silicon and silicon oxide. In addition, both the barrier type and the porous type are extremely difficult to be etched by dry etching. In particular, the etching ratio with silicon oxide is also characterized by a sufficiently high selectivity.

The second of the present invention is
(A) Step of forming a semiconductor active layer on an insulating surface (b) Step of selectively providing a doping mask on the active layer (c) Metal for covering the active layer and the doping mask to form silicide (D) a step of selectively introducing an N-type or P-type impurity element into the active layer through the metal film (e) by selectively reacting the metal film with the active layer, A step of selectively forming a silicide region in the active layer; (f) a step of removing the metal film that has not reacted in the step (e);

Of these, the order cannot be changed up to the steps (a) to (c), but the steps (d) to (f) can be changed, and the following two types of configurations are possible by combining them. . That is,
Third configuration Step d → Step e → Step f
Fourth configuration Step e → Step d → Step f
It is.
More generally, in the present invention, step (c) is before steps (d) and (f), and step (d) is before step (e). .
Here, in the third configuration, it is possible to activate the N-type or P-type impurity doped in step d in step e. However, in the fourth configuration, steps d and f are performed. It is desirable to provide an activation step during or after step f.

  In the step (e) or after the step, the N-type or P-type impurity may be activated by irradiating with a laser or equivalent intense light. Moreover, the said process (e) may be performed by 300-500 degreeC thermal annealing.

Further, the second of the present invention may be a bottom gate type TFT or a top gate type TFT. In particular, in the top gate type TFT, it is preferable to use a gate electrode and a gate insulating film as the doping mask. On the other hand, in a bottom gate type TFT, a mask for source / drain doping may be used as a doping mask.
In the second step (d) of the present invention, a part of the lower portion of the doping mask is irradiated by irradiating ions containing an N-type or P-type impurity element with an inclination of 30 ° or more with respect to the substrate. It is good to dope up to.

  As described above, in the first and second embodiments of the present invention, a salicide structure can be obtained without using a side wall obtained by anisotropic etching. A feature of the present invention is that after forming a metal film, impurity ions are implanted through the metal film to form a source / drain. That is, since the gate insulating film containing silicon oxide as a main component is etched in the state of intrinsic silicon having a high etching selectivity with silicon oxide or the like, there is no overetching of the active layer. Further, N-type / P-type impurities are implanted into the silicide region, and an ohmic contact between the silicide region and the metal electrode can be obtained even at a lower concentration.

In the present invention, since there is no step of etching silicon oxide on a doped silicon surface having a low selectivity with respect to silicon oxide, a TFT can be manufactured with high yield. The characteristics of the TFT obtained by the present invention are of course not different from those of the conventional salicide structure TFT.
In the present invention, the width of the source / drain (region 113 in FIG. 1 or region 310 in FIG. 3) is formed with extremely high accuracy by means such as anodic oxidation and rotational oblique ion implantation. A TFT circuit is obtained.

  In the embodiments, the TFT on the glass substrate has been mainly described. However, the TFT of the present invention is formed on glass or organic resin even when a three-dimensional integrated circuit is formed on the substrate on which the semiconductor integrated circuit is formed. Needless to say, it is formed in the same manner in any case, but in any case, it is formed on the insulating surface.

  FIG. 1 shows this embodiment. First, a silicon oxide film having a thickness of 100 to 300 nm was formed as a base oxide film 102 on a substrate (Corning 7059, 300 mm × 400 mm or 100 mm × 100 mm) 101. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere was used. However, in order to further increase mass productivity, a film obtained by decomposing and depositing TEOS by plasma CVD may be used.

  Thereafter, an amorphous silicon film was deposited by plasma CVD or LPCVD to a thickness of 30 to 500 nm, preferably 50 to 100 nm, and allowed to stand in a reducing atmosphere at 550 to 600 ° C. for 24 hours for crystallization. This step may be performed by laser irradiation. Then, the island film 103 was formed by patterning the silicon film crystallized in this manner. Further, a silicon oxide film 104 having a thickness of 70 to 150 nm was formed thereon by sputtering.

  Thereafter, an aluminum film (containing 1 to 5 wt% Zr (zirconium) or 0.1 to 0.3 wt% Sc (scandium)) having a thickness of 100 to 3000 nm was formed by an electron beam evaporation method or a sputtering method. A photoresist (for example, OFPR 800/30 cp, manufactured by Tokyo Ohka) was formed by spin coating. In addition, a material that can be etched with photosensitive polyimide or ordinary polyimide may be used as the material of the mask film.

If an aluminum oxide film having a thickness of 10 to 100 nm is formed on the surface by anodic oxidation before the formation of the photoresist, the adhesion with the photoresist is good and current leakage from the photoresist is suppressed. Thus, it was effective in forming the porous anodic oxide only on the side surface in the subsequent anodic oxidation step.
Thereafter, the photoresist and the aluminum film were patterned to form a mask 106, which was used to etch the aluminum film to form the gate electrode 105. The mask 106 is left as it is, and the process proceeds to the next step. (Fig. 1 (A))

  Further, this was anodized through an electric current in an electrolytic solution to form an anodic oxide 107 having a thickness of 300 to 600 nm, for example, a thickness of 500 nm. Anodization is performed using 3 to 20% of an acidic aqueous solution such as citric acid or succinic acid, phosphoric acid, chromic acid, sulfuric acid, etc., and a constant current of 10 to 30 V may be applied to the gate electrode. The hydrogen ion concentration pH of the solution is desirably less than 2. The optimum pH depends on the type of the electrolytic solution, but in the case of oxalic acid, it is 0.9 to 1.0. In this case, a thick anodic oxide of 500 nm or more can be formed at a low voltage of about 10 to 30V. In this example, the voltage was set to 10 V in an oxalic acid solution (30 ° C.) having a pH of 0.9 to 1.0, and anodization was performed for 20 to 40 minutes. The thickness of the anodic oxide was controlled by the anodic oxidation time. (Fig. 1 (B))

  Next, the mask 106 was removed, and a current was applied to the gate electrode so that the voltage rose again at 1 to 10 V / min in the electrolytic solution. This time, an ethylene glycol ammonia solution having a pH of 6.9 to 7.1 and containing at least one of 3 to 10% tartaric acid, boric acid and nitric acid was used. A better oxide film was obtained when the temperature of the solution was lower than room temperature of around 10 ° C. For this reason, the barrier type anodic oxide 108 was formed on the upper surface and the side surface of the gate electrode. The thickness of the anodic oxide 108 was proportional to the applied voltage, and an anodic oxide of 200 nm was formed at an applied voltage of 150V. (Figure 1 (C))

  It should be noted that, despite the fact that barrier type anodic oxidation is a later process, the barrier type anodic oxide 108 is not formed on the outside of the porous anodic oxide. It is formed between the porous anodic oxide 107 and the gate electrode 105. For phosphoric acid-based etchants, the etching rate of the porous anodic oxide is 10 times or more that of the barrier type anodic oxide. For this reason, the inner gate electrode can be protected by the barrier type anodic oxide 108 when the porous anodic oxide is etched later by a phosphoric acid-based etchant.

Thereafter, the silicon oxide film 104 was etched by a dry etching method. In this etching, a plasma mode of isotropic etching or a reactive ion etching mode of anisotropic etching may be used. However, it is important to prevent the active layer from being etched deeply by sufficiently increasing the selection ratio between silicon and silicon oxide. In the present invention, since the active layer is intrinsic silicon, the etching selectivity with silicon oxide is sufficiently large. For example, if CF ₄ is used as an etching gas, the anodic oxide is not etched and only the silicon oxide film 104 is etched. The silicon oxide film (gate insulating film) 110 under the porous anodic oxide 107 remained without being etched. (Figure 1 (D))

In this embodiment, the gate electrode is aluminum. However, even if other materials (for example, tantalum and titanium are the main components), when the insulating film 104 is mainly composed of silicon oxide, the fluorine-based electrode is used. When dry etching is performed using an etching gas (for example, NF ₃ , SF ₆ ), the insulating film 104 made of silicon oxide is quickly etched, but the etching rate of tantalum oxide and titanium oxide is sufficiently low, so that the insulating film 104 can be selectively etched.

Wet etching can also be used, and a hydrofluoric acid-based etchant such as 1/100 hydrofluoric acid may be used. Also in this case, the insulating film 104 made of silicon oxide is etched quickly, but the insulating film 104 can be selectively etched because the etching rate of aluminum oxide, tantalum oxide, titanium oxide or the like is sufficiently low.
Thereafter, the porous anodic oxide 107 was etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. In this etching, only the anodic oxide 107 was etched, and the etching rate was about 60 nm / min. The underlying gate insulating film 110 remains as it is.

Further, an appropriate metal such as titanium, chromium, nickel, molybdenum, tungsten, platinum, palladium, or the like, for example, a titanium film 111 having a thickness of 20 to 200 nm was formed on the entire surface by sputtering. (Figure 1 (E))
Then, by ion doping, impurities were implanted into the TFT active layer 103 in a self-aligned manner using the gate electrode portion (that is, the gate electrode and its surrounding anodic oxide film) and the gate insulating film 110 as a mask.

In this example, phosphine (PH ₃ ) was used as the doping gas. The dose was 5 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage was 60 to 120 kV. For this reason, the doping impurity is mainly implanted into the region 113 having the width y, which becomes an N-type impurity region. On the other hand, many impurities passed through the region 112, and the impurity concentration was rather low. In order to form a P-type impurity region, diborane (B ₂ H ₆ ) may be used as a doping gas. (Fig. 1 (F))

In this embodiment, the doping is performed only once. However, the doping may be performed twice by adjusting the voltage so that the region 112 is also doped. Further, doping may be performed so that the impurity concentration of the region 113 is 1 to 3 digits lower than the impurity concentration of the region 112.
Thereafter, thermal annealing at 450 ° C. was performed for 1 to 5 hours. As a result, the doping impurities are activated and the titanium film 111 and the silicon in the region 112 react to form a silicide region 114. Since doped silicon has high reactivity, silicidation could be sufficiently performed even at a low temperature of 450 ° C. On the other hand, the region 113 not in contact with the titanium film became the source / drain.

  In this process, an infrared laser such as a Nd: YAG laser (preferably Q-switched pulse oscillation) or a visible light laser such as a second harmonic thereof, various ultraviolet lasers using excimers such as KrF, XeCl, and ArF are used. Although a so-called optical annealing method of irradiating can be used, when laser irradiation is performed from the upper surface of the metal film, it is necessary to select a laser having a wavelength that is not reflected by the metal film. However, there is almost no problem when the metal film is extremely thin. Moreover, you may irradiate a laser beam from the board | substrate side. In this case, it is necessary to select a laser beam that passes through the underlying silicon semiconductor film.

  Further, lamp annealing by irradiation with non-coherent visible light or near infrared light may be used. When lamp annealing is performed, lamp irradiation is performed for several minutes at 600 ° C. and for several tens of seconds at 1000 ° C. so that the surface to be irradiated has a temperature of about 600 to 1000 ° C. Annealing with near infrared rays (for example, infrared rays of 1200 nm) selectively absorbs near infrared rays into the silicon semiconductor, does not heat the glass substrate so much, and shortens the time of one irradiation, thereby suppressing the heating of the glass substrate. Can be extremely useful.

  After the silicide region 114 was formed as described above, the unreacted titanium film was etched with an etching solution in which hydrogen peroxide, ammonia, and water were mixed at a ratio of 5: 2: 2. Titanium films (for example, titanium films present on the gate insulating film 110 and the anodic oxide film 108) other than the portions in contact with the exposed active layer remained in the metal state as they were, but could be removed by this etching. On the other hand, the titanium silicide in the silicide region 112 was not etched and could remain.

  Finally, a silicon oxide film having a thickness of 300 nm was formed as an interlayer insulator 115 on the entire surface by a CVD method. Then, contact holes were formed in the source / drain of the TFT, and aluminum wiring / electrodes 116 and 117 were formed. Thus, an N-channel TFT was completed. The contact portion of the aluminum wiring is titanium silicide, and the stability of the interface with aluminum is better than that of silicon, so that a highly reliable contact was obtained.

Further, if, for example, titanium nitride is formed as a barrier metal between the aluminum electrodes 116 and 117 and the silicide region 114, the reliability can be further improved. In this example, the sheet resistance of the silicide region was 10 to 50Ω / □. As a result, a TFT having good frequency characteristics and low hot carrier deterioration even at a high drain voltage could be produced. (Fig. 1 (G))
Similarly, a P-channel TFT or a CMOS circuit can be manufactured by the method disclosed in this embodiment.

The present embodiment will be described with reference to FIG. First, a base silicon oxide film 302 was deposited on a glass substrate 301, and an amorphous silicon film having a thickness of 50 nm was formed from crystalline silicon. Thereafter, this was left to stand in a reducing atmosphere at 550 to 600 ° C. for 8 to 24 hours to cause crystallization. At this time, a small amount of a catalyst element that promotes crystallization, such as nickel, may be added. The silicon film thus crystallized was irradiated with a KrF excimer laser (wavelength 248 nm) to further improve the crystallinity. Although the energy density of the laser depends on the crystallinity of the silicon film, preferable results were obtained at 200 to 350 mJ / cm ² . The optimum energy density also depended on the substrate temperature during laser irradiation. The crystalline silicon film thus obtained was etched to form an active layer 303.

Further, a silicon oxide gate insulating film 304 having a thickness of 150 nm was formed to cover the active layer 303. Then, an aluminum film having a thickness of 500 nm having 0.1 to 0.3 wt% of Sc was formed by sputtering, and this was etched to form a gate electrode 305. Thereafter, this was anodized to form an anodic oxide 306 on the upper surface and side surfaces thereof.
Anodization was performed by immersing the substrate in a 1 to 3% ethylene glycol tartrate solution adjusted to pH≈7 with ammonia, using platinum as a cathode and aluminum gate electrode 305 as an anode. The anodic oxidation was terminated by first raising the voltage to a specific voltage with a constant current and holding it in that state for 1 hour. The thickness of the anodic oxide 306 was 200 nm. (Fig. 3 (A)))

Next, the silicon oxide film 304 was etched using the gate electrode and the anodic oxide as a mask. A dry etching method was used for etching, and CHF ₃ was used as an etching gas at that time. Aluminum oxide which is an anodic oxide is preferable because it is hardly etched by the dry etching method and only the silicon oxide film is selectively etched. Of course, a wet etching method may be used. In this way, the active layer of the N-channel TFT was exposed. Then, a platinum (platinum) film 308 having a thickness of 20 to 200 nm was formed by sputtering. (Fig. 3 (B))

  Next, impurity regions 107 were formed by irradiating impurity ions obliquely. As a result, the impurity region also goes under the anodic oxide 306. In each of the above steps, the impurity region is formed by irradiating the substrate with accelerated impurity ions from an oblique direction. At that time, a method (rotating oblique ion implantation method) was used in which the substrate was rotated while being tilted with respect to the direction of the ion source.

  The rotating oblique ion implantation method used the apparatus shown in FIG. The apparatus shown in FIG. 2 includes a chamber 201 and a sample holder (substrate holder) 202 disposed therein, an anode electrode 203, a power source 204 for supplying a high voltage to the anode electrode 203, and a grid electrode 205. . The angle θ of the sample holder 202 can be freely changed so that ion implantation from an oblique direction is possible. Further, the sample holder is provided with a rotating mechanism so that it can be rotated during ion implantation. (Figure 2)

  The anode electrode 203 has a structure that can apply a high voltage. As the maximum voltage, for example, a voltage of 120 kV or more is applied. Impurity ions 206 ionized by RF discharge or the like in the vicinity of the grid electrode 205 are accelerated in the direction of the substrate 207 (sample) disposed on the sample holder 202 by the voltage applied to the anode. As a result, accelerated impurity ions are implanted into the substrate. (Figure 2)

In this embodiment, the dose is 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ² , the acceleration voltage is 60 to 120 kV, for example, the dose is 4 × 10 ¹³ atoms / cm ² , and the acceleration voltage is 110 kV. As a result, an N-type impurity region 309 was formed, and this region was formed so as to overlap the gate electrode 305. (Figure 3 (C))

  And it annealed at 400-550 degreeC, for example, 450 degreeC for 1 hour. As a result, silicide was formed in the portion where the platinum film and the silicon film were in close contact, and at the same time, the doped impurities were activated. Further, since the platinum film, silicon oxide, and aluminum oxide did not react, the platinum film on the silicon oxide and the anodic oxide remained unreacted. This was easily removed. In this way, a silicide region 311 was formed in a portion corresponding to the source / drain. Further, in the N-type impurity region 309, the portion of the width x that did not become silicide remained as the source / drain region 310 in the gate electrode portion. (Fig. 3 (D))

  Next, a silicon oxide film having a thickness of 300 nm was formed as the interlayer insulating film 312 by plasma CVD. Then, the interlayer insulating film 312 was etched to form contact holes in the source / drain of the TFT. Then, an aluminum film was formed by a sputtering method, and patterning / etching was performed to form source / drain electrodes 313 and 314. (Figure 3 (E))

  In the above silicidation process, depending on the progress of the silicidation, silicide may be formed up to the bottom of the active layer as shown in FIGS. 3D and 3E, or the active layer as shown in FIG. In some cases, silicide is formed only on the surface. As a matter of course, the former has a smaller sheet resistance corresponding to the source / drain, but the latter has a sufficiently low resistance. Therefore, in any case, the sheet resistance of the source / drain is substantially determined by the width x of the impurity region 310.

In connection with the above, the thickness of the silicide is selected by the sheet resistance required for the region corresponding to the source / drain. If the sheet resistance is 10 to 100Ω / □, the specific resistance of the silicide is 0.1 to 1 mΩ · cm, and therefore the thickness of the silicide is suitably 10 to 1000 nm.
Further, when the silicide is formed, the metal film may be irradiated with strong light such as a laser in addition to the thermal annealing and reacted with the underlying silicon semiconductor film to form the silicide. Moreover, you may irradiate a laser beam from the board | substrate side. If a laser is used, a pulsed laser is preferred. Since the continuous wave laser has a long irradiation time, there is a danger that the irradiated object will be peeled off due to the expansion due to the heat, and there is also a thermal damage to the substrate.

This embodiment will be described with reference to FIG. A base film 402, an active layer 403, a silicon oxide film 404 functioning as a gate insulating film, and a gate electrode 405 capable of anodization are formed on a glass substrate 401, and the top and side surfaces of the gate electrode are anodized to be anodized. Product 406 was obtained.
Further, the gate oxide film 407 was obtained by etching the silicon oxide film 404. Then, a palladium film 408 having a thickness of 100 nm was formed over the entire surface by sputtering. (Fig. 4 (B))

Then, using the gate electrode and the anodic oxide as a mask, the impurity region 409 is provided in the active layer by irradiating impurity ions from an oblique direction using the apparatus of FIG. At this time, the concentration of unseen trees was lowered compared to the normal case. For example, the dose is 1 × 10 ^{12 to} 5 × 10 ¹⁴ atoms / cm ² . (Fig. 4 (C))
Next, ions of the same conductivity type were irradiated from a substantially vertical direction, and the impurity concentration was made higher than that of the impurity region 409 formed earlier. The dose amount at this time was suitably 1 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² . As a result, a low-concentration impurity region having a width x remains under the anodic oxide, and the other regions become high-concentration impurity regions 410. (Fig. 4 (D))

Thereafter, the palladium film and the impurity region were reacted to form a silicide region 412. However, the silicide reaction does not reach the impurity region 409 below the anodic oxide, and the impurity region remains as it is. Moreover, since the metal film formed on the anodic oxide remained in a state of hardly reacting, the unreacted one of the palladium film 408 could be easily etched. (Fig. 4 (E))
Thereafter, an interlayer insulator 413 was deposited, a contact hole was formed in the silicide region, and metal wiring / electrodes 414 and 415 were formed to complete the TFT. (Fig. 4 (F))

  In this embodiment, low concentration impurities are doped as the source / drain regions. In a normal TFT, doping with such a low concentration of impurities alleviates the electric field in the vicinity of the drain, reduces deterioration due to hot carrier injection, and also reduces the leakage current between the source and drain. For example, in the case where the impurity region 310 in FIG. 3 has a low concentration, since the impurity concentration is low, the NI junction (PI junction in the case of a P-channel TFT) is shallow, and the distance between the silicide regions is small. Since it is short, when the drain voltage is high, the leakage current between the source and drain tends to increase. In order to prevent this, it is effective to perform doping at a high concentration as shown in FIG.

FIG. 5 shows this embodiment. First, gate wiring / electrodes 502 and 503 were formed on a substrate (Corning 7059, 100 mm × 100 mm) 501. As the gate wiring / electrode, tantalum having a thickness of 300 nm was used. The surface of the gate electrode may be treated by anodic oxidation to improve insulation.
Thereafter, a silicon nitride film 504 having a thickness of 300 to 600 nm, for example, 400 nm was deposited by plasma CVD. This also functions as a gate insulating film. Then, an amorphous silicon film having a thickness of 30 to 100 nm, for example, 50 nm was formed by a plasma CVD method. And this was etched and the active layer 505 was formed. (Fig. 5 (A))

Further, a silicon oxide film having a thickness of 300 to 600 nm, for example, 200 nm was deposited by plasma CVD. Then, a photoresist was applied to the entire surface and exposed from the back surface of the substrate, and patterning was performed using the gate electrodes / wirings 502 and 503 as a mask. Then, using this pattern, the silicon oxide film was etched to form doping masks 506 and 507. (Fig. 5 (B))
Thereafter, a titanium film 508 having a thickness of 50 nm was formed by sputtering. (Fig. 5 (C))

Next, an N-type impurity region (source / drain region) 509 was formed by implanting an N-type impurity into the active layer 505 by a rotating oblique ion doping method using the apparatus of FIG. As the doping gas, phosphine (PH ₃ ) was used. The dose was 5 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage was 60 to 90 kV. (Fig. 5 (D))

Then, by performing thermal annealing at 300 to 450 ° C., for example, 350 ° C. for 10 to 60 minutes, titanium and silicon were reacted to form a silicide region 510. Thereafter, the remaining titanium film was etched. (Fig. 5 (E))
Further, an aluminum film having a thickness of 500 nm was formed on the entire surface by sputtering, and this was etched to form wirings 511 and 512. The wirings 511 and 512 are in contact with the previously formed silicide region. Thus, the TFT was completed. (Fig. 5 (F))

FIG. 7 shows this embodiment. In the same manner as in Example 1, a base oxide film 702, an island-shaped region 703 of a crystalline silicon film, a silicon oxide gate insulating film 704 having a thickness of 150 nm, aluminum (1-5 wt% Zr (zirconium) ), A barrier type anodic oxide 706, and a porous anodic oxide 707. (Equivalent to FIGS. 7A and 1D)
Thereafter, the porous anodic oxide 707 was etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. Further, a chromium film having a thickness of 20 to 200 nm was formed on the entire surface by sputtering. Chromium reacted with silicon in the active layer during sputtering film formation, and 2 to 10 nm on the surface of the active layer became silicide (not shown). (Fig. 7 (B))

Thereafter, thermal annealing at 450 ° C. was performed for 1 to 5 hours. As a result, the chromium film 708 and the silicon of the active layer 703 reacted to form a silicide region 709. On the other hand, no silicide was formed in a region of the active layer that was not in contact with the chromium film. (Fig. 7 (C))
In this process, an infrared laser such as a Nd: YAG laser (preferably Q-switched pulse oscillation) or a visible light laser such as a second harmonic thereof, various ultraviolet lasers using excimers such as KrF, XeCl, and ArF are used. Although a so-called optical annealing method of irradiating can be used, when laser irradiation is performed from the upper surface of the metal film, it is necessary to select a laser having a wavelength that is not reflected by the metal film. However, there is almost no problem when the metal film is extremely thin. Moreover, you may irradiate a laser beam from the board | substrate side. In this case, it is necessary to select a laser beam that passes through the underlying silicon semiconductor film.

  Further, lamp annealing by irradiation with non-coherent visible light or near infrared light may be used. When lamp annealing is performed, lamp irradiation is performed for several minutes at 600 ° C. and for several tens of seconds at 1000 ° C. so that the surface to be irradiated has a temperature of about 600 to 1000 ° C. Annealing with near infrared rays (for example, infrared rays of 1200 nm) selectively absorbs near infrared rays into the silicon semiconductor, does not heat the glass substrate so much, and shortens the time of one irradiation, thereby suppressing the heating of the glass substrate. Can be extremely useful.

Then, by ion doping, impurities were implanted into the TFT active layer 703 in a self-aligned manner using the gate electrode portion (that is, the gate electrode and its surrounding anodic oxide film) and the gate insulating film 704 as a mask.
In this example, phosphine (PH ₃ ) was used as the doping gas. The dose was 5 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage was 60 to 120 kV. Therefore, the doping impurity is mainly implanted into the active layer region 710 under the gate insulating film 704, and this region becomes an N-type impurity region. (Fig. 7 (D))

In this embodiment, the doping is performed only once. However, the doping may be performed twice by adjusting the voltage so that the region 709 is also doped. Further, doping may be performed so that the impurity concentration in the region 710 is lower by 1 to 3 digits than the impurity concentration in the region 709.
Then, the doped impurities were activated. In this example, thermal annealing at 300 to 500 ° C., for example, 450 ° C. was performed for 0.1 to 2 hours, for example, 1 hour. This step may be performed using the laser or RTA method as described above. As described above, since the activation was performed with the chromium film provided, the formation of silicide could be further promoted.

Thereafter, the unreacted chromium film was etched, and a silicon oxide film having a thickness of 300 nm was formed as an interlayer insulator 711 on the entire surface by a CVD method. Then, contact holes were formed in the source / drain of the TFT, and aluminum wiring / electrodes 712 and 713 were formed. Thus, an N-channel TFT was completed.
In this embodiment, the doped impurities are activated before removing the chromium film, but may be performed after removing the chromium film. In this case, in particular, when using a laser or RTA method, it is not necessary to consider the reflection of light by the chromium film, so that activation can be performed effectively.

A method for manufacturing a TFT according to Example 1 will be described. The conceptual diagram of the doping apparatus used for Examples 2-4 is shown. A method for manufacturing a TFT according to Example 2 will be described. A method for manufacturing a TFT according to Example 3 will be described. A method for manufacturing a TFT according to Example 4 will be described. A method for manufacturing a TFT by a conventional method will be described. A method for manufacturing a TFT according to Example 5 will be described.

Explanation of symbols

101 Insulating substrate 102 Base oxide film (silicon oxide)
103 Active layer 104 Insulating film (silicon oxide)
105 Gate electrode (aluminum)
106 Mask film (photoresist)
107 Anodic oxide (porous)
108 Anodic oxide (barrier type)
109 Gate insulating film edge 110 Gate insulating film 111 Metal coating (titanium)
112, 113 N-type impurity region 114 Silicide region 115 Interlayer insulator 116, 117 Metal wiring / electrode (aluminum)

Claims (7)

Forming a silicon film on the insulating surface ;
Forming an insulating film on the silicon film;
Forming a gate electrode on the insulating film;
Anodizing the gate electrode to form an anodic oxide on the top and side surfaces of the gate electrode;
Using the anodic oxide and the gate electrode as a mask, the insulating film is removed to expose the silicon film,
Forming a metal film covering the exposed silicon film , the anodic oxide and the gate electrode;
Through the metal film, a source region and a drain region are formed by selectively introducing impurity ions of a conductive type into the silicon film by ion implantation obliquely with respect to the insulating surface ;
By annealing , the source region and the drain region of the exposed silicon film and the metal film are reacted to form a silicide region to the bottom of the exposed silicon film ,
Removing the metal coating remaining unreacted ,
The portion of the source and drain regions, the method for manufacturing a semiconductor device, characterized in that overlaps with the gate electrodes. Forming a silicon film on the insulating surface ;
Forming an insulating film on the silicon film;
Forming a gate electrode on the insulating film;
Anodizing the gate electrode to form an anodic oxide on the top and side surfaces of the gate electrode;
Using the anodic oxide and the gate electrode as a mask, the insulating film is removed to expose the silicon film,
Forming a metal film covering the exposed silicon film , the anodic oxide and the gate electrode;
By reacting the exposed silicon film with the metal film by annealing, a silicide region is formed to the bottom of the exposed silicon film ,
Through the metal film remaining unreacted, a source region and a drain region are formed by selectively introducing impurity ions of conductivity type into the silicon film and the silicide region obliquely with respect to the insulating surface . And
Removing the metal film remaining unreacted ,
The portion of the source and drain regions, the method for manufacturing a semiconductor device, characterized in that overlaps with the gate electrodes. Forming a silicon film on the insulating surface ;
Forming an insulating film on the silicon film;
Forming a gate electrode on the insulating film;
Anodizing the gate electrode to form an anodic oxide on the top and side surfaces of the gate electrode;
Using the anodic oxide and the gate electrode as a mask, the insulating film is removed to expose the silicon film,
Forming a metal film covering the exposed silicon film , the anodic oxide and the gate electrode;
Through the metal film, a conductive impurity ion is selectively introduced into the silicon film obliquely with respect to the insulating surface by ion implantation, thereby forming a pair of low-concentration impurity regions,
Through the metal film, a source region and a drain region were formed by introducing impurity ions of the same conductivity type as the impurity ions of the conductivity type selectively into the silicon film by ion implantation perpendicular to the insulating surface . rear,
By annealing , the source region and the drain region of the exposed silicon film and the metal film are reacted to form a silicide region to the bottom of the exposed silicon film ,
Removing the metal coating remaining unreacted ,
Wherein a portion of the pair of low-concentration impurity regions, a method for manufacturing a semiconductor device, characterized in that overlaps with the gate electrodes. Forming a silicon film on the insulating surface ;
Forming an insulating film on the silicon film;
Forming a gate electrode on the insulating film;
Anodizing the gate electrode to form an anodic oxide on the top and side surfaces of the gate electrode;
Using the anodic oxide and the gate electrode as a mask, the insulating film is removed to expose the silicon film,
Forming a metal film covering the exposed silicon film , the anodic oxide and the gate electrode;
By reacting the exposed silicon film with the metal film by annealing, a silicide region is formed to the bottom of the exposed silicon film ,
A pair of low-concentration impurity regions are introduced by selectively implanting impurity ions of a conductive type into the silicon film and the silicide region obliquely with respect to the insulating surface through the metal film remaining unreacted. Form the
Through the metal film remaining unreacted, the source region is selectively introduced into the silicide region by ion implantation of the same conductivity type impurity ions as the conductivity type impurity ions perpendicularly to the insulating surface . And a drain region,
Removing the metal film remaining unreacted ,
Wherein a portion of the pair of low-concentration impurity regions, a method for manufacturing a semiconductor device, characterized in that overlaps with the gate electrodes. Forming a gate electrode on the insulating surface ;
Forming a first insulating film on the gate electrode;
Forming a silicon film on the first insulating film;
A portion of the first insulating film is exposed by selectively removing the silicon film;
Covering the silicon film and the first insulating film to form a second insulating film;
Forming a photoresist on the second insulating film, and forming a pattern by exposing the gate electrode as a mask;
Removing the second insulating film using the pattern as a mask to expose a portion of the silicon film;
Covering the exposed silicon film, the first insulating film, and the second insulating film to form a metal film;
Through the metal film, a source region and a drain region are formed by selectively introducing impurity ions of a conductive type into the silicon film by ion implantation obliquely with respect to the insulating surface ;
By annealing , the source region and the drain region of the exposed silicon film and the metal film are reacted to form a silicide region to the bottom of the exposed silicon film ,
Removing the metal coating remaining unreacted ,
The portion of the source and drain regions, the method for manufacturing a semiconductor device, characterized in that overlaps with the gate electrodes. Forming a gate electrode on the insulating surface ;
Forming a first insulating film on the gate electrode;
Forming a silicon film on the first insulating film;
A portion of the first insulating film is exposed by selectively removing the silicon film;
Covering the silicon film and the first insulating film to form a second insulating film;
Forming a photoresist on the second insulating film, and forming a pattern by exposing the gate electrode as a mask;
Removing the second insulating film using the pattern as a mask to expose a portion of the silicon film;
Covering the exposed silicon film, the first insulating film, and the second insulating film to form a metal film;
By reacting the exposed silicon film with the metal film by annealing, a silicide region is formed to the bottom of the exposed silicon film ,
Through the metal film remaining unreacted, a source region and a drain region are formed by selectively introducing impurity ions of conductivity type into the silicon film and the silicide region obliquely with respect to the insulating surface . And
Removing the metal film remaining unreacted ,
The portion of the source and drain regions, the method for manufacturing a semiconductor device, characterized in that overlaps with the gate electrodes. A source region and a drain region formed on the insulating surface , a pair of low-concentration impurity regions formed between the source region and the drain region, and a channel formation region formed between the pair of low-concentration impurity regions And a semiconductor film having
A gate insulating film formed on the pair of low-concentration impurity regions and the channel formation region ;
A gate electrode formed on the gate insulating film;
In the semiconductor device having the anodic oxide of the gate electrode formed on the upper surface and the side surface of the gate electrode ,
The concentration of impurity ions in the source region and drain region is higher than the concentration of impurity ions in the low concentration impurity region ,
Silicide region is formed on the entire front Symbol source and drain regions,
The semiconductor device, wherein the silicide region is connected to a metal wiring.

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