JP4229157B2 - Drive circuit, electro-optical device, and electronic apparatus - Google Patents

Description

  The present invention relates to a drive circuit, an electro-optical device, and an electronic apparatus.

  Conventionally, as a liquid crystal display (LCD) panel (display panel in a broad sense, an electro-optical device in a broad sense) used for an electronic device such as a cellular phone, a simple matrix type LCD panel and a thin film transistor ( 2. Description of the Related Art An active matrix type LCD panel using a switching element such as a thin film transistor (hereinafter abbreviated as TFT) is known.

  The simple matrix method is easier to reduce power consumption than the active matrix method, but it is difficult to increase the number of colors and display a moving image. On the other hand, the active matrix method is suitable for multicolor and moving image display, but it is difficult to reduce power consumption.

  In a simple matrix type LCD panel and an active matrix type LCD panel, driving is performed so that an applied voltage to liquid crystal (electro-optical material in a broad sense) constituting a pixel is an alternating current. As such AC driving methods, line inversion driving and field inversion driving (frame inversion driving) are known. In line inversion driving, driving is performed so that the polarity of the voltage applied to the liquid crystal is inverted every one or more scanning lines. In the field inversion driving, driving is performed so that the polarity of the voltage applied to the liquid crystal is inverted for each field (for each frame).

  At that time, the voltage level applied to the pixel electrode is lowered by changing the counter electrode voltage (common voltage) supplied to the counter electrode (common electrode) facing the pixel electrode constituting the pixel in accordance with the inversion drive timing. Can be made.

Even when such AC driving is performed, an increase in power consumption accompanying charging / discharging of the liquid crystal is caused. Therefore, for example, in Patent Document 1, during inversion driving, the electric charge accumulated in the liquid crystal is initialized by short-circuiting the two electrodes sandwiching the liquid crystal, and the transition is made to the intermediate voltage of the voltage before the short-circuiting of the electrode, thereby reducing the consumption. A technique for achieving electric power is disclosed.
JP 2002-244622 A

  However, the technique disclosed in Patent Document 1 has a problem that the power consumption reduction effect depends on the voltage applied to the source line. Therefore, the effect of reducing the amount of charge for charging and discharging the counter electrode whose polarity is reversed cannot be expected so much. Further, in the technique disclosed in Patent Document 1, depending on the relationship between the voltage applied to the source line and the polarity of the counter electrode voltage, the amount of charge to be charged / discharged can be reduced by short-circuiting the two electrodes sandwiching the liquid crystal. There is a problem that the effect of lowering power consumption may be diminished.

  The present invention has been made in view of the technical problems as described above, and the object of the present invention is to further reduce power consumption by reusing charges without consuming as much power as possible. It is an object to provide a drive circuit, an electro-optical device, and an electronic apparatus that can be realized.

In order to solve the above problems, the present invention
A drive circuit for driving a source line of an electro-optical device based on gradation data,
A source line driver for supplying a gradation voltage corresponding to gradation data to the source line;
A source output switching unit for short-circuiting the source line with a common line connected to a capacitor before the source line is driven by the source line driving unit;
A charge reuse control unit that controls the source output switching unit,
The charge reuse controller
For each source output, according to the first gradation voltage supplied to the source line in the immediately preceding horizontal scanning period and the second gradation voltage supplied to the source line in the horizontal scanning period, the source line Whether or not to short-circuit the common line,
The source output switching unit is
The present invention relates to a drive circuit that short-circuits the source line with the shared line based on a determination result of the charge reuse control unit.

  In the present invention, the charge of the source line can be reused before the driving circuit drives the source line. The reuse of electric charge is realized by short-circuiting the source line to a shared line having a capacitor connected to one end. By reusing the charge on the source line, the potential of the source line to be driven can be set to a given level without external charge / discharge. When such charge is reused, no power is consumed. For this reason, the drive circuit only needs to drive the source line from the given level to the level of the grayscale voltage corresponding to the grayscale data by reusing the electric charge. Can often be reduced. However, depending on the level of the gradation voltage set for the source line in the horizontal scanning period immediately before the horizontal scanning period, it may be necessary to charge / discharge extra charges if the charge is not reused as described above. There is.

  Therefore, according to the present invention, for each source output, the first gradation voltage supplied to the source line during the immediately preceding horizontal scanning period and the second gradation voltage supplied to the source line during the horizontal scanning period. Therefore, it is determined whether or not the source line is short-circuited with the shared line, and according to the determination result, the source line and the shared line are short-circuited. It can be controlled not to recycle the charge when it is accompanied by discharge. Therefore, it is possible to provide a drive circuit that can realize further lower power consumption by reusing charges without consuming as much power as possible.

In the driving circuit according to the present invention,
The charge reuse controller
For each source output, determine whether the first and second gradation voltages are both higher potential side or lower potential side than a given reference voltage,
The source output switching unit is
When the charge recycle control unit determines that the first and second gradation voltages are both higher or lower than the reference voltage, the source line is short-circuited to the shared line. Instead, a short circuit can be made when it is determined that one of the first and second gradation voltages is higher than the reference voltage and the other is lower than the reference voltage .

In the present invention, it is determined whether the first and second gradation voltages are both higher potential side or lower potential side than a given reference voltage. When driving a source line whose first and second grayscale voltages are both higher potential side or lower potential side than the reference voltage , at the time of reusing charges prior to driving the source line by the drive circuit. Once the potential of the source line reaches a given level, it becomes necessary to charge / discharge excess charges. According to the present invention, the source line and the common line are short-circuited on the condition that the determination is made as described above for each source output, so that the charge can be reused without consuming unnecessary power. Thus, it is possible to provide a drive circuit that can realize further lower power consumption.

In the driving circuit according to the present invention,
The charge reuse controller
The most significant bit data of the first gradation data for generating the first gradation voltage and the most significant bit data of the second gradation data for generating the second gradation voltage And based on the comparison result, it can be determined whether or not the source line is short-circuited with the shared line.

In the driving circuit according to the present invention,
The reference voltage is
It may be a gradation voltage corresponding to the intermediate gradation value.

  According to any one of the above-described inventions, since the gradation voltage corresponding to the intermediate gradation value is used as the reference voltage, the charge can be reused with a simple configuration without consuming unnecessary power. A drive circuit capable of realizing power consumption can be provided. In this case, since the determination can be made as described above using only the most significant bit data of the gradation data, the configuration of the drive circuit can be further simplified.

In the driving circuit according to the present invention,
The charge reuse controller
A first comparison result of comparing the first gradation data for generating the first gradation voltage and given reference data, and a second comparison result for generating the second gradation voltage Whether or not the source line is short-circuited to the shared line can be determined based on the second comparison result obtained by comparing the gradation data and the reference data.

In the driving circuit according to the present invention,
The charge reuse controller
For each source output, determine whether the first and second gradation data are both larger or smaller than the reference data,
The source output switching unit is
When the charge reuse controller determines that the first and second gradation data are both larger or smaller than the reference data, the source line is not short-circuited with the shared line, and the first When one of the second gradation voltages is determined to be higher than the reference data and the other is determined to be lower than the reference data, a short circuit can be made.

According to any one of the above inventions, whether the gradation voltage in two consecutive horizontal scanning periods is higher or lower than the settable voltage between the highest voltage _VH and the lowest voltage _VL. This makes it possible to re-use charges and to omit re-use of charges. Therefore, for example, even when the gradation characteristics of the electro-optical device showing the relationship between the gradation data and the gradation voltage with the horizontal axis as the gradation data and the vertical axis as the gradation voltage have no linear relationship, the charge Since it is possible to change the reference for determining whether or not to recycle, it can be applied to driving circuits for driving various electro-optical devices. That is, even when various electro-optical devices are driven, it is possible to provide a drive circuit that can further reduce power consumption by reusing charges without consuming unnecessary power.

In the driving circuit according to the present invention,
A first source short-circuit switch provided between a first source output node to which an output voltage to the first source line of the electro-optical device is supplied and the shared line;
A source charge storage switch provided between a second capacitor element connection node to which one end of the second capacitor element is connected and the shared line;
After the first source output node and the second capacitor element connection node are electrically connected once by the first source short circuit switch and the source charge storage switch, the first source short circuit switch or the source charge A voltage corresponding to grayscale data is supplied to the first source output node in a state where the first source output node and the second capacitor element connection node are electrically cut off by a storage switch, The first source line can be driven.

  In the present invention, after the first source output node and the second capacitor element connection node are electrically connected via the first source short-circuit switch and the source charge storage switch, the first source A voltage corresponding to the gradation data is supplied to the output node. At this time, one end of the second capacitor element and the first source output node are at the same potential, and accumulated in the parasitic capacitance of the first source output node or the source line connected to the first source output node. The charge is supplemented to one end of the second capacitor element, or the charge accumulated in the second capacitor element is supplemented to a parasitic capacitor such as the first source output node. Therefore, the potential of the first source output node or the like can be changed without replenishing charges from the external power supply at all. Therefore, after that, it is only necessary to charge the first source output node with reference to the potential changed as described above, so that power consumption can be reduced.

In the driving circuit according to the present invention,
A first capacitor element connection node to which one end of the first capacitor element is connected and a counter electrode voltage output node to which a voltage of a counter electrode facing the pixel electrode of the electro-optical device is supplied via an electro-optical material. A counter electrode charge storage switch provided therebetween;
After the counter electrode voltage output node and the first capacitor element connection node are electrically connected once by the counter electrode charge storage switch, the counter electrode voltage is supplied to the counter electrode voltage output node and the counter The electrode can be driven.

  In the present invention, the counter electrode voltage output node and the first capacitor element connection node are once electrically connected via the counter electrode charge storage switch, and then the counter electrode is supplied to the counter electrode voltage output node. The At this time, one end of the first capacitor element and the counter electrode have the same potential, and the charge accumulated in the parasitic capacitance of the counter electrode supplements one end of the first capacitor element, or the first capacitor element The charge accumulated in the capacitor is supplemented to the parasitic capacitance of the counter electrode. Therefore, it is possible to change the potential of the counter electrode without replenishing charges from the external power supply at all. Therefore, after that, it is only necessary to replenish charges to the counter electrode based on the potential changed as described above, so that power consumption can be reduced. In addition, since the counter electrode is set to either the high potential side voltage or the low potential side voltage, the power consumption can be reliably reduced with a simple configuration without depending on the gradation data. The effect of low power consumption through reuse is remarkable.

The present invention also provides
Multiple source lines,
Multiple gate lines,
A plurality of pixel electrodes in which each pixel electrode is specified by each gate line and each source line;
A counter electrode facing the plurality of pixel electrodes;
The present invention relates to an electro-optical device including any one of the drive circuits described above for driving the plurality of source lines.

The present invention also provides
The present invention relates to an electro-optical device including any one of the drive circuits described above.

  According to any one of the above-described inventions, it is possible to provide an electro-optical device capable of realizing further lower power consumption by reusing charges without consuming as much power as possible.

The present invention also provides
The present invention relates to an electronic device including any one of the drive circuits described above.

The present invention also provides
The present invention relates to an electronic apparatus including the electro-optical device described above.

  According to any one of the above-described inventions, it is possible to provide an electronic device that can realize further lower power consumption by reusing charges without consuming as much power as possible.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Liquid Crystal Device FIG. 1 shows an example of a block diagram of a liquid crystal device of this embodiment.

  The liquid crystal device 10 (liquid crystal display device; display device in a broad sense) includes a display panel 12 (LCD (Liquid Crystal Display) panel in a narrow sense), a source line drive circuit 20 (a source driver in a narrow sense), and a gate line drive circuit 30. (Gate driver in a narrow sense), a display controller 40, and a power supply circuit 50 are included. Note that it is not necessary to include all these circuit blocks in the liquid crystal device 10, and some of the circuit blocks may be omitted.

  Here, in the display panel 12 (electro-optical device in a broad sense), a plurality of gate lines (scanning lines), a plurality of source lines (data lines), and each pixel electrode are specified by each gate line and each source line. A plurality of pixel electrodes are included. In this case, an active matrix liquid crystal device can be configured by connecting a thin film transistor TFT (Thin Film Transistor, switching element in a broad sense) to a source line and connecting a pixel electrode to the TFT.

More specifically, the display panel 12 is formed on an active matrix substrate (for example, a glass substrate). In this active matrix substrate, a plurality of gate lines G _{1 to} G _M (M is a natural number of 2 or more) arranged in the Y direction and extending in the X direction, and a plurality of sources arranged in the X direction and extending in the Y direction, respectively. Lines S _{1 to} S _N (N is a natural number of 2 or more) are arranged. The thin film transistor TFT _KL (switching in a broad sense) is provided at a position corresponding to the intersection of the gate line G _K (1 ≦ K ≦ M, K is a natural number) and the source line S _L (1 ≦ L ≦ N, L is a natural number). Element).

The gate electrode of the thin film transistor TFT _KL is connected with the gate line _{G K,} a source electrode of the _{thin film transistor TFT KL} is connected with the source line _{S L,} the drain electrode of the _{thin film transistor TFT KL} is connected with a pixel electrode _{PE KL.} A liquid crystal capacitor CL _KL (liquid crystal element) is _disposed between the pixel electrode PE _KL and the counter electrode CE (common electrode, common electrode) opposed to the pixel electrode PE _KL with the liquid crystal (electro-optical material in a broad sense) interposed therebetween. In addition, an auxiliary capacitor CS _KL is formed. Then, liquid crystal is formed between the active matrix substrate on which the TFT _KL , the pixel electrode PE _{KL, and the} like are formed and the counter substrate on which the counter electrode CE is formed, and the pixel electrode PE _KL , the counter electrode CE, The transmittance of the pixel is changed in accordance with the applied voltage between.

  Note that the voltage level (high potential side voltage VCOMH, low potential side voltage VCOML) of the counter electrode voltage VCOM applied to the counter electrode CE is generated by a counter electrode voltage generation circuit included in the power supply circuit 50. Further, the counter electrode CE may be formed in a strip shape so as to correspond to each gate line without being formed on the entire surface of the counter substrate.

The source line driving circuit 20 drives the source lines S _{1 to} S _N of the display panel 12 based on the gradation data. On the other hand, the gate line driver circuit 30 scans the gate lines _G 1 ~G _M of the display panel 12 (sequential drive).

  The display controller 40 controls the source line driving circuit 20, the gate line driving circuit 30, and the power supply circuit 50 according to the contents set by a host such as a central processing unit (CPU) (not shown). More specifically, the display controller 40 sets, for example, an operation mode and supplies an internally generated vertical synchronization signal and horizontal synchronization signal to the source line drive circuit 20 and the gate line drive circuit 30 to supply power. For the circuit 50, the polarity inversion timing of the voltage level of the common electrode voltage VCOM applied to the common electrode CE is controlled.

  The power supply circuit 50 generates various voltage levels (grayscale voltages) necessary for driving the display panel 12 and the voltage level of the counter electrode voltage VCOM of the counter electrode CE based on a voltage supplied from the outside.

  In the liquid crystal device 10 having such a configuration, the source line driving circuit 20, the gate line driving circuit 30, and the power supply circuit 50 cooperatively display based on gradation data supplied from outside under the control of the display controller 40. The panel 12 is driven.

  Further, in FIG. 1, a source driver circuit 20, a gate line driver circuit 30, and a power supply circuit 50 can be integrated to form a display driver (driving circuit in a broad sense) 60 as a semiconductor device (integrated circuit, IC). . The display driver 60 in FIG. 1 may have a configuration in which the gate line driving circuit 30 is omitted. In FIG. 1, the display driver 60 in the present embodiment may be configured to include the source line driving circuit 20 and the common electrode voltage generation circuit of the power supply circuit 50.

The display driver 60 further includes a plurality of source output switching circuits (source output switching units) SSW _{1 to} SSW in which each source output switching circuit is provided between the source line and an output buffer that drives the source line. _N is included. The output of each output buffer is connected to the first terminal of each source output switching circuit. Each source line is connected to the second terminal of each source output switching circuit. One end of the shared line COL is connected to the third terminal of each source output switching circuit. The plurality of source output switching circuits SSW _{1 to} SSW _N are individually turned on / off by a control signal (not shown). That is, each source output switching circuit is on / off controlled for each source output.

The display driver 60 includes a second capacitor element connection terminal TL2 for storing source charge and a source charge storing switch CSW. The source charge storage switch CSW is provided between the other end of the shared line COL and the second capacitor element connection terminal TL2. When the source charge storage switch CSW is set to the conductive state, each source output switching circuit of the source output switching circuits SSW _{1 to} SSW _N can electrically connect each source line to the common line COL.

  It can be said that the shared line COL includes a second capacitor element connection node. One end of the second capacitor element CCS is electrically connected to the second capacitor element connection terminal TL2. A predetermined power supply voltage (for example, the system ground power supply voltage VSS) is supplied to the other end of the second capacitor element CCS. In FIG. 1, the second capacitor element CCS is provided outside the display driver 60, but the second capacitor element CCS may be built in the display driver 60.

  The display driver 60 can further include a first capacitor element connection terminal TL1 and a counter electrode charge storage switch VSW. The common electrode charge storage switch VSW is connected between the output of the common electrode voltage generation circuit of the power supply circuit 50 (the common electrode voltage output node to which the common electrode voltage VCOM is supplied) and the first capacitor element connection terminal TL1. Provided. One end of the first capacitor element CCV is electrically connected to the first capacitor element connection terminal TL1. A predetermined power supply voltage (for example, the system ground power supply voltage VSS) is supplied to the other end of the first capacitor element CCV. In FIG. 1, the first capacitor element CCV is provided outside the display driver 60, but the first capacitor element CCV may be built in the display driver 60.

  When the common electrode charge storage switch VSW is set to the conductive state, the output of the common electrode voltage generation circuit of the power supply circuit 50 is set to the high impedance state.

  In FIG. 1, the liquid crystal device 10 includes the display controller 40, but the display controller 40 may be provided outside the liquid crystal device 10. Alternatively, the host may be included in the liquid crystal device 10 together with the display controller 40. Further, part or all of the source line driver circuit 20, the gate line driver circuit 30, the display controller 40, and the power supply circuit 50 may be formed on the display panel 12.

  FIG. 2 is a block diagram showing another configuration example of the liquid crystal device according to this embodiment.

  In FIG. 2, a display driver 60 including a source line driving circuit 20, a gate line driving circuit 30, and a power supply circuit 50 is formed on the display panel 12 (panel substrate). As described above, the display panel 12 includes a plurality of gate lines, a plurality of source lines, a plurality of pixels (pixel electrodes) specified by the gate lines of the plurality of gate lines and the source lines of the plurality of source lines. A source line driving circuit for driving a plurality of source lines and a gate line driving circuit for scanning the plurality of gate lines can be included. A plurality of pixels are formed in the pixel formation region 44 of the display panel 12. Each pixel can include a TFT having a source connected to the source and a gate line connected to the gate, and a pixel electrode connected to the drain of the TFT.

  In FIG. 2, at least one of the gate line driving circuit 30 and the power supply circuit 50 may be omitted on the display panel 12.

  In FIG. 1 or FIG. 2, the display driver 60 may incorporate the display controller 40. Alternatively, in FIG. 1 or FIG. 2, the display driver 60 may be a semiconductor device in which one of the source line driver circuit 20 and the gate line driver circuit 30 and the power supply circuit 50 are integrated.

2. Display Driver Next, a configuration main part of the display driver 60 as the drive circuit of FIG. 1 or FIG. 2 will be described.

  FIG. 3 is a block diagram showing a configuration example of the source line driver circuit 20 shown in FIG.

  The source line drive circuit 20 includes a shift register 22, line latches 24 and 26, a DAC 28 (Digital-to-Analog Converter) (data voltage generation circuit in a broad sense), and an output buffer (source line drive unit in a broad sense) 29. .

  The shift register 22 includes a plurality of flip-flops provided corresponding to each source line and sequentially connected. When the shift register 22 holds the enable input / output signal EIO in synchronization with the clock signal CLK, the shift register 22 sequentially shifts the enable input / output signal EIO to the adjacent flip-flops in synchronization with the clock signal CLK.

  Gradation data (DIO) is input to the line latch 24 from the display controller 40 in units of 18 bits (6 bits (gradation data) × 3 (each RGB color)), for example. The line latch 24 latches the gradation data (DIO) in synchronization with the enable input / output signal EIO sequentially shifted by each flip-flop of the shift register 22.

  The line latch 26 latches the grayscale data for one horizontal scan latched by the line latch 24 in synchronization with the horizontal synchronization signal LP supplied from the display controller 40.

  The gradation voltage generation circuit 27 generates 64 kinds of gradation voltages. The 64 types of gradation voltages generated by the gradation voltage generation circuit 27 are supplied to the DAC 28.

  A DAC (data voltage generation circuit) 28 generates an analog data voltage to be supplied to each source line. Specifically, the DAC 28 selects any one of the gradation voltages from the gradation voltage generation circuit 27 based on the digital gradation data from the line latch 26, and analog data corresponding to the digital gradation data. Output voltage.

The output buffer 29 buffers the data voltage from the DAC 28 and outputs it to the source line to drive the source line. Specifically, the output buffer 29 includes operational amplifier circuit blocks OPC _{1 to} OPC _N each including a voltage follower-connected operational amplifier circuit provided for each source line, and these operational amplifier circuit blocks are connected to the DAC 28. Is converted to impedance and output to each source line.

  In FIG. 3, the digital gradation data is converted from digital to analog and output to the source line via the output buffer 29. However, the analog video signal is sampled and held and output. A configuration of outputting to the source line via the buffer 29 can also be adopted.

  FIG. 4 shows a configuration example of the gradation voltage generating circuit 27, the DAC 28, and the output buffer 29 in FIG. In FIG. 4, gradation data is 6-bit data D0 to D5, and inverted data of the data of each bit is indicated as XD0 to XD5. In FIG. 4, the same parts as those in FIG.

The gradation voltage generating circuit 27 generates 64 kinds of gradation voltages by dividing the voltages VDDH and VSSH generated by the power supply circuit 50 by resistance. Each gradation voltage corresponds to each gradation value represented by 6-bit gradation data. Each gradation voltage is supplied in common to each source line of the source lines S _{1 to} S _N.

The DAC 28 includes a decoder provided for each source line, and each decoder outputs a gradation voltage corresponding to the gradation data to the operational amplifier circuit blocks OPC _{1 to} OPC _N.

  3 and 4 show an example of a configuration in which gradation data is supplied line by line, the display driver 60 may incorporate a display memory that stores gradation data for at least one screen. .

  FIG. 5 shows a configuration example of the gate line driving circuit 30 of FIG. 1 or FIG.

  The gate line driving circuit 30 includes an address generation circuit 32, an address decoder 34, a level shifter 36, and an output circuit 38.

Address generating circuit 32 generates an address corresponding to the gate line to be selected among the gate lines G ₁ ~G _M. Address generating circuit 32 can generate an address to scan and select the gate line G ₁ ~G _M one by one.

The address decoder 34 decodes the address generated by the address generation circuit 32 selects the decoded signal lines corresponding to the gate lines G ₁ ~G _M based on the decoding result.

  The level shifter 36 shifts the voltage level of the signal on the decode signal line from the address decoder 34 to a voltage level corresponding to the liquid crystal element of the display panel 12 and the transistor capability of the TFT. Since this voltage level requires a high voltage level, a high breakdown voltage process different from other logic circuit units is used.

  The output circuit 38 buffers the scanning voltage shifted by the level shifter 36 and outputs it to the gate line to drive the gate line.

  FIG. 6 shows a configuration example of the power supply circuit 50 of FIG. 1 or FIG.

  The power supply circuit 50 includes a positive direction double boosting circuit 52, a scanning voltage generation circuit 54, and a counter electrode voltage generation circuit 56. The power supply circuit 50 is supplied with a system ground power supply voltage VSS and a system power supply voltage VDD.

  The system ground power supply voltage VSS and the system power supply voltage VDD are supplied to the positive direction double booster circuit 52. Then, the positive direction double boosting circuit 52 generates a power supply voltage VDDHS obtained by boosting the system power supply voltage VDD twice in the positive direction on the basis of the system ground power supply voltage VSS. That is, the positive direction double boosting circuit 52 boosts the voltage difference between the system ground power supply voltage VSS and the system power supply voltage VDD twice. Such a positive direction double boosting circuit 52 can be constituted by a known charge pump circuit. The power supply voltage VDDHS is supplied to the source line drive circuit 20, the scan voltage generation circuit 54, and the counter electrode voltage generation circuit 56. It is desirable that the positive direction double booster circuit 52 outputs a power supply voltage VDDHS obtained by boosting the system power supply voltage VDD twice in the positive direction by adjusting the voltage level with a regulator after boosting at a boosting factor of 2 or more. .

  The scan voltage generation circuit 54 is supplied with the system ground power supply voltage VSS and the power supply voltage VDDHS. The scan voltage generation circuit 54 generates a scan voltage. The scanning voltage is a voltage applied to the gate line selected by the gate line driving circuit 30. The high potential side voltage of this scanning voltage is VDDHG, and the low potential side voltage is VEE.

  The counter electrode voltage generation circuit 56 generates a counter electrode voltage VCOM. The common electrode voltage generation circuit 56 outputs the high potential side voltage VCOMH or the low potential side voltage VCOML as the common electrode voltage VCOM based on the polarity inversion signal POL. The polarity inversion signal POL is generated by the display controller 40 in accordance with the polarity inversion timing.

  FIG. 7 shows an example of the drive waveform of the display panel 12 shown in FIG.

  A gradation voltage DLV corresponding to the gradation value of the gradation data is applied to the source line. In FIG. 7, a gradation voltage DLV having an amplitude of 5 V is applied with respect to the system ground power supply voltage VSS (= 0 V).

  A scanning voltage GLV of a low potential side voltage VEE (= −10 V) when not selected and a high potential side voltage VDDHG (= 15 V) when selected is applied to the gate line.

  The counter electrode CE is applied with the counter electrode voltage VCOM of the high potential side voltage VCOMH (= 3 V) and the low potential side voltage VCOML (= −2 V). The polarity of the voltage level of the counter electrode voltage VCOM with respect to a given voltage is inverted in accordance with the polarity inversion timing. FIG. 7 shows the waveform of the counter electrode voltage VCOM during so-called scanning line inversion driving. In accordance with the polarity inversion timing, the polarity of the grayscale voltage DLV of the source line is also inverted with reference to a given voltage.

  By the way, the liquid crystal element has a property that it deteriorates when a DC voltage is applied for a long time. For this reason, a driving method is required in which the polarity of the voltage applied to the liquid crystal element is inverted every predetermined period. Such driving methods include frame inversion driving, scanning (gate) line inversion driving, data (source) line inversion driving, dot inversion driving, and the like.

  Among these, data line inversion driving and dot inversion driving have good image quality, but have the disadvantage that a high voltage is required for driving the display panel. On the other hand, the frame inversion drive has a disadvantage that the image quality is not so good, but can reduce power consumption. For example, focusing on the frequency of the counter electrode voltage, the frame inversion driving can significantly reduce the frequency of the counter electrode voltage. Therefore, compared with data line inversion driving and dot inversion driving, frame inversion driving can greatly reduce the power consumption associated with driving the counter electrode. Therefore, in this embodiment, frame inversion driving is adopted.

  Thus, by reversing the polarity of the counter electrode voltage VCOM, the voltage necessary for driving the display panel can be lowered. As a result, the withstand voltage of the drive circuit can be lowered, and the manufacturing process of the drive circuit can be simplified and the cost can be reduced.

2.1 Charge Reuse By the way, in this embodiment, the source output switching circuits SSW _{1 to} SSW _N , the source charge storage switch CSW, and the second capacitor element CCS are used to store in the second capacitor element CCS. Using the generated charge, the source line can be driven with low power consumption without charging or discharging the source line from the outside. In other words, charging / discharging of extra charges from the outside is reduced, and further reduction in power consumption is realized.

  Furthermore, in this embodiment, by using the counter electrode charge storage switch VSW and the first capacitor element CCV, the charge stored in the first capacitor element CCV is used to charge the counter electrode from the outside. The counter electrode can be driven with low power consumption without charging and discharging. In other words, charging / discharging of extra charges from the outside is reduced, and further reduction in power consumption is realized.

  FIG. 8 shows a principle configuration diagram of the liquid crystal device 10 of the present embodiment.

In FIG. 8, the same parts as those in FIG. 1 or FIG. In Figure 8, the gate lines G _K and the electrical equivalent circuit of a pixel provided at the intersection of the source line S _L, the gate line G _{K + 1} and the source line S _{L + 1} of the electrical equivalent circuit of a pixel provided at the intersection The same applies to the electrical equivalent circuits of other pixels. Further, FIG. 8 shows only the source output switching circuit, the source charge storage switch CSW, and the counter electrode charge storage switch VSW of the source line driving circuit 20.

  FIG. 9 shows a waveform diagram of an operation example of the liquid crystal device 10 of FIG.

In Figure 9, the gate line G _K, G _K + _1, but shows a change in potential of the source line S _L, the other gate line, is the same source line. 9 is a select period of the pixels is connected with the gate line G _K within one horizontal scanning period (1H), the scan voltage is applied to the gate line G _K, the selection of pixels is connected with the gate line G _{K + 1} A scanning voltage is applied to the gate line _{GK + 1} within one horizontal scanning period. Each horizontal scanning period includes a charge recycling period provided in the first half part and a driving period provided in the second half part. When the transition from the charge recycle period to the drive period and the transition from the drive period to the charge recycle period, switching control of the source output switching circuits SSW _L and SSW _{L + 1} and the source charge storage switch CSW is performed.

When the charge is reused, in the charge reuse period (TT1), in the source output switching circuits SSW _L and SSW _{L + 1} , the source lines S _L and S _{L + 1} are connected to the shared line COL including the second capacitor element connection node. Each is electrically connected. Further, the source charge storage switch CSW becomes conductive, and the shared line COL is electrically connected to one end of the second capacitor element CCS via the second capacitor element connection terminal TL2. Therefore, in the charge recycle period, one end of the second capacitor element CCS and the source lines S _L and S _{L + 1} have the same potential, and the charge accumulated in the parasitic capacitance of the source line is in accordance with the law of charge conservation. The charge is replenished to one end of the capacitive element CCS, or the charge accumulated in the second capacitive element CCS is supplemented to the parasitic capacitances of the source lines S _L and S _{L + 1} . That is, in the charge recycle period, the potential of the source line is changed without replenishing charges from the power supply circuit 50 at all.

Next, in the drive period (TT2) after the charge recycle period, in the source output switching circuits SSW _L and SSW _{L + 1} , the source lines S _L and S _{L + 1} are output buffers (source line drive units) of the source line drive circuit 20. Are respectively electrically connected to the outputs of the. Further, the source charge storage switch CSW is set in a non-conductive state. Therefore, in the driving period, the source lines S _L and S _{L + 1} are driven by the output buffer of the source line driving circuit 20. At this time, the output buffer of the source line driver circuit 20 charges and discharges the source line charge until each source line becomes a potential corresponding to each gradation data with reference to the potential after the change in the charge reuse period TT1. . Therefore, in the driving period after the charge recycling period, the voltage of the source line to be changed by the output buffer of the source line driving circuit 20 is often low. That is, based on the potential of the source line in the immediately preceding horizontal scanning period (selection period of pixels connected to the gate line _GK-1 ), the horizontal scanning period (selection period of pixels connected to the gate line _GK) is used as it is. 9), the output buffer of the source line driver circuit 20 needs to charge / discharge the source line charges by ΔVs1 as shown in FIG. On the other hand, by providing the above-described charge recycling period, the output buffer of the source line driver circuit 20 may charge and discharge the source line charge by ΔVs2 (ΔVs2 <ΔVs1) as shown in FIG.

  In the next horizontal scanning period, a charge recycling period and a driving period are provided, and the same is performed in each period.

  The voltage applied to the source line depends on the type of display image. Therefore, the voltage applied to the source line depends on the gradation data of the source line to be reused. In general, when charging and discharging of the charge to and from the second capacitor element CCS are repeated, the voltage corresponding to the charge accumulated by the second capacitor element CCS converges to the gradation voltage corresponding to the intermediate gradation value. I will do it. For example, in the case of 64 gradations, it converges to a gradation voltage corresponding to the gradation value “32” which is an intermediate gradation value.

  FIG. 10 shows a waveform diagram of another operation example of the liquid crystal device 10 of FIG.

  FIG. 10 shows a change in potential of the counter electrode CE. In FIG. 10, one vertical scanning period (1V) includes a charge recycle period provided in the first half portion and a drive period provided in the second half portion. When the transition from the charge recycle period to the drive period and the transition from the drive period to the charge recycle period, switching control of the common electrode charge storage switch VSW is performed.

  In the charge recycle period (TT10), the output of the common electrode voltage generation circuit (not shown) is set to a high impedance state, and the common electrode charge storage switch VSW is set to a conductive state. Therefore, the counter electrode CE is electrically connected to one end of the first capacitor element CCV via the first capacitor element connection terminal TL1. Therefore, in the charge recycling period, one end of the first capacitor element CCV and the counter electrode CE have the same potential, and the charge accumulated in the parasitic capacitance of the counter electrode CE supplements one end of the first capacitor element CCV. Or charge accumulated in the first capacitor element CCV is supplemented to the parasitic capacitance of the counter electrode CE. That is, in the charge recycling period, the potential of the counter electrode CE is changed without replenishing charges from the power supply circuit 50 at all.

  Next, in the drive period (TT20) after the charge recycle period, the common electrode charge storage switch VSW is set in a non-conductive state, and the common electrode CE is electrically connected to the output of the common electrode voltage generation circuit 56 of the power supply circuit 50. Connected. Therefore, in the driving period, the common electrode voltage VCOM is supplied to the common electrode CE and the common electrode voltage generation circuit 56. At this time, the common electrode voltage generation circuit 56 charges and discharges the common electrode CE until the high potential side voltage VCOMH is reached with reference to the potential after the change in the charge recycle period TT10. Therefore, in the driving period after the charge recycling period, the voltage of the counter electrode CE that should be changed by the counter electrode voltage generation circuit 56 may be low. That is, when the potential of the counter electrode CE in the vertical scanning period is set as it is based on the potential of the counter electrode CE in the immediately preceding vertical scanning period, the counter electrode voltage generation circuit 56 is opposed by ΔVc1 as shown in FIG. It is necessary to charge / discharge the electric charge of the electrode CE. On the other hand, by providing the above-described charge recycling period, the counter electrode voltage generation circuit 56 only needs to charge / discharge the charge of the counter electrode CE by ΔVc2 (ΔVc2 <ΔVc1) as shown in FIG.

  In the next vertical scanning period, a charge recycling period and a driving period are provided, and the same is performed in each period.

2.2 Charge Reuse Control By the way, since the counter electrode CE is set to either the high potential side voltage VCOMH or the low potential side voltage VCOML, it is reliably reduced with a simple configuration without depending on the gradation data. Power consumption can be reduced, and the effect of reducing power consumption by reusing charges is remarkable. On the other hand, the power consumption associated with the driving of the source line in the charge recycling period as shown in FIG. 9 depends on the voltage (that is, the gradation data) to be set by the source line driving circuit 20 in the driving period. In addition, the effect of reducing power consumption due to the reuse of electric charge is diminished. Therefore, in the present embodiment, it is determined whether to recycle charges for each source line based on the gradation voltage corresponding to the gradation data in two consecutive horizontal scanning periods, and the determination result is Based on this, the above-described charge re-use is performed for each source line, or the re-use is omitted.

  FIG. 11 shows a main configuration part of the source line driving circuit 20 of FIG.

In Figure 11, there is shown an exemplary configuration of a per output of the source line driving circuit 20 for driving the source line S _L, another source output have the same configuration. In Figure 11, the source line driver circuit 20, is intended to include common line COL, the same parts as FIG. 3, accompanied corresponding to the source line S _L to the same reference numerals are denoted by the letter "L", it will not be further described .

In FIG. 11, the source line drive circuit 20 includes a charge recycle control unit 100 ₁ provided for each source output, in addition to the shift register 22, the line latches 24 and 26, the gradation voltage generation circuit 27, the DAC 28, and the output buffer 29. Contains ~ 100 _L. Source output switching circuits SSW _{1 to} SSW _{N in} FIG. 8 are provided in the output buffer 29.

Figure in 11, grayscale data D taken into constituted by flip-flops provided corresponding to the source line S _L line latch 24 L _(not shown) of the flip-flop of the line latch 24 [5: 0 ] Is taken into the line latch 26 _L constituted by the flip-flop provided corresponding to the source line S _L among the flip-flops of the line latch 26 at the change timing of the horizontal synchronizing signal LP. Gray-scale data D taken the line latch 26 _L [5: 0] is output to the DAC 28 _L. The DAC 28 _L outputs a gradation voltage that is an analog voltage corresponding to the gradation data D [5: 0] from the line latch 26 _L. Operational amplifier of the operational amplifier circuit block OPC _L can drive the source line _{S L} and the gray scale voltage impedance conversion from DAC 28 _L. A source output switching circuit SSW _L is provided between the operational amplifier circuit block OPC _L and the source line S _L of the display panel 12.

Further, in FIG. 11, the source line _{S L} to the charge corresponding reusable controller 100 _L are provided. The charge reuse control unit 100 _L performs switching control of the source output switching circuit SSW _L.

Therefore, the source line driving circuit 20, prior the output buffer (source line driver section) to the source line S _L is driven, the source output switch circuit for short-circuiting the common line COL to the source line S _L SSW _L and a charge reuse control unit 100 _L that controls the source output switching circuit SSW _L. The shared line COL is electrically connected to one end of the second capacitor element (capacitor in a broad sense) CCS. For each source output, the charge reuse control unit _100L includes a first gradation voltage supplied to the source line during the immediately preceding horizontal scanning period and a second gradation voltage supplied to the source line during the horizontal scanning period. Accordingly, it is determined whether or not the source line is short-circuited (electrically connected) to the shared line COL. The source output switch circuit SSW _L is short-circuited with the common line COL source line _{S L,} based on the charge recycle control section 100 _L of the determination result.

More specifically, if the charge recycle control section 100 _L, for each source output, first and second grayscale voltages are both high potential side or both the low potential side than a given reference voltage not Determine whether. The source output switching circuit SSW _L , when the charge reuse control unit _100L determines that the first and second gradation voltages are both higher or lower than the reference voltage, without shorting the source line S _L and the common line COL, shorted when the other is determined to the reference voltage the low potential side in the first and one high potential than the reference voltage of the second gradation voltage. More specifically, the charge reuse control unit _100L includes the most significant bit (MSB) data of the first grayscale data for generating the first grayscale voltage, and the second comparing the most significant bit of the second tone data for generating the gradation voltage data, it determines whether or not short-circuited with the common line COL source line S _L, based on the comparison result.

Thus, the charge recycle control section 100 _L may include a latch 110 _L, and a grayscale data determination unit 120 _L. Latch 110 _L is a change in the timing of the horizontal synchronization signal LP, latches the D [5] is the data of MSB of the grayscale data from the line latch 26 _L. Gradation data determination unit 120 _L compares the D [5] from D [5] and the line latch 26 _L from the latch 110 _L. D from latch 110 _L [5] is data of MSB of the grayscale data in the horizontal scanning period immediately before (immediately preceding line) of the horizontal scanning period (current line).

Comparison result signal of the gradation data determination unit 120 _L is supplied to the source output switch circuit SSW _L. The source output switching circuit SSW _L is switch-controlled based on the comparison result signal from the gradation data determination unit 120 _L.

Figure 12 is a diagram illustrative of a control example of the charge recycle control section 100 _L of FIG.

In grayscale data determination unit 120 _L, "0" data is the MSB of the grayscale data of the immediately preceding line, when the data of the MSB of the grayscale data in the present line is determined to be "0", the charge recycle The control unit 100 _L controls the source output switching circuit SSW _L so as not to short-circuit the source line S _L and the shared line COL so as not to perform charge reuse.

In grayscale data determination unit 120 _L, "0" data is the MSB of the grayscale data of the immediately preceding line, when the data of the MSB of the grayscale data in the present line is determined to be "1", the charge recycle The control unit 100 _L controls the source output switching circuit SSW _L so as to short-circuit the source line S _L and the common line COL in order to reuse the charge.

In grayscale data determination unit 120 _L, data is "1" in the MSB of the grayscale data of the immediately preceding line, when the data of the MSB of the grayscale data in the present line is determined to be "0", the charge recycle The control unit 100 _L controls the source output switching circuit SSW _L so as to short-circuit the source line S _L and the common line COL in order to reuse the charge.

In grayscale data determination unit 120 _L, data is "1" in the MSB of the grayscale data of the immediately preceding line, when the data of the MSB of the grayscale data in the present line is determined to be "1", the charge recycle The control unit 100 _L controls the source output switching circuit SSW _L so as not to short-circuit the source line S _L and the shared line COL so as not to perform charge reuse.

The gradation voltage generation circuit 27 generates 64 kinds of gradation voltages corresponding to the gradation data. Therefore, determining whether the MSB of the gradation data is “0” or “1” means that the gradation voltage corresponding to the 6-bit gradation data is the highest voltage V _H (for example, 6-bit gradation voltage). The voltage corresponding to the gradation data “111111”) and the lowest voltage V _L (for example, the voltage corresponding to the 6-bit gradation data “000000”) are higher or lower than the intermediate voltage. It means to judge.

  FIG. 13A and FIG. 13B are explanatory diagrams of the effect of charge recycle control according to this embodiment. 13A and 13B, it is determined in FIG. 12 that the MSB data of the gradation data of the immediately preceding line is “0” and the MSB data of the gradation data of the current line is “0”. The effect when it is done.

When the MSB data of the gradation data is “0”, the gradation voltage corresponding to the gradation data (the voltage driven by the source line driver) is the gradation corresponding to the intermediate gradation value as described above. It is on the lower potential side than the reference voltage Vref which is a voltage. That is, there than the reference voltage Vref driving voltage of the source line S _L in the horizontal scanning period immediately before the low-potential side drive voltage of the source line S _L in the horizontal scanning period is also a low-potential side of the reference voltage Vref .

Therefore, as shown in FIG. 13A, when the charge reuse control is performed as described above in the charge reuse period in the first half of the horizontal scanning period, the voltages of the source lines S _{1 to} S _N once become substantially the reference. The voltage becomes Vref. For this reason, the source line S _L is once charged from the outside by a charge amount corresponding to ΔV _L 1 (for example, positive charge) in the charge recycling period, and then again becomes ΔV _L 2 in the driving period. A corresponding amount of charge is discharged. This means that an extra charge corresponding to the difference between ΔV _L 1 and ΔV _L 2 was charged / discharged.

Therefore, in this embodiment, as shown in FIG. 13B, charge recycle control is not performed in the case of FIG. 13A. Thereby, when switching from horizontal scanning period immediately before to the horizontal scanning period, is directly supplied to the drive voltage source line S _L of the horizontal scanning period can be omitted charging and discharging of excess charge, low Electricity can be achieved.

  FIG. 14A and FIG. 14B are explanatory diagrams of the effect of charge recycle control according to this embodiment. 14A and 14B, it is determined in FIG. 12 that the MSB data of the gradation data of the immediately preceding line is “1” and the MSB data of the gradation data of the current line is “1”. The effect when it is done.

When the MSB data of the gradation data is “1”, the gradation voltage corresponding to the gradation data (voltage driven by the source line driver) is the gradation corresponding to the intermediate gradation value as described above. It is on the higher potential side than the reference voltage Vref which is a voltage. That is, the driving voltage of the source line S _L in the horizontal scanning period immediately before there from the high potential side reference voltage Vref, the driving voltage of the source line S _L in the horizontal scanning period is also in the high-potential side of the reference voltage Vref .

Therefore, as shown in FIG. 14A, when the charge reuse control is performed as described above in the charge reuse period in the first half of the horizontal scanning period, the voltages of the source lines S _{1 to} S _N once become substantially the reference voltage. Vref. For this reason, the source line S _L is once discharged to the outside by a charge amount corresponding to ΔV _L 10 (for example, positive charge) in the charge recycle period, and then again becomes ΔV _L 20 in the drive period. The corresponding charge amount is charged. This means that an extra charge corresponding to the difference between ΔV _L 10 and ΔV _L 20 was charged / discharged.

Therefore, in this embodiment, as shown in FIG. 14B, charge recycle control is not performed in the case of FIG. Thereby, when switching from horizontal scanning period immediately before to the horizontal scanning period, is directly supplied to the drive voltage source line S _L of the horizontal scanning period can be omitted charging and discharging of excess charge, low Electricity can be achieved.

  FIG. 15 is an explanatory diagram of the effect of charge recycle control according to the present embodiment. FIG. 15 shows the effect when it is determined in FIG. 12 that the MSB data of the gradation data of the previous line is “0” and the MSB data of the gradation data of the current line is “1”.

That is, there driving voltage of the source line S _L in the horizontal scanning period immediately before is the reference voltage Vref to the low potential side, the driving voltage of the source line S _L in the horizontal scanning period is on the higher potential side than the reference voltage Vref.

Therefore, in the case shown in FIG. 15, charge recycle control is performed as described above. In this way, when switching from the immediately preceding horizontal scanning period to the horizontal scanning period, the charge is reused and once adjusted to the reference voltage Vref without charge being charged or discharged from the outside, and then the source line S _L In addition, since it is only necessary to supply a driving voltage for the horizontal scanning period, power consumption can be reduced due to charge recycling.

  FIG. 16 is an explanatory diagram of the effect of charge recycle control according to the present embodiment. FIG. 16 shows the effect when it is determined in FIG. 12 that the MSB data of the gradation data of the previous line is “1” and the MSB data of the gradation data of the current line is “0”.

That is, the driving voltage of the source line S _L in the horizontal scanning period immediately before there from the high potential side reference voltage Vref, the driving voltage of the source line S _L in the horizontal scanning period is than the reference voltage Vref to the low potential side.

Therefore, in the case shown in FIG. 16, the charge recycle control is performed as described above. In this way, when switching from the immediately preceding horizontal scanning period to the horizontal scanning period, the charge is reused and once adjusted to the reference voltage Vref without charge being charged or discharged from the outside, and then the source line S _L In addition, since it is only necessary to supply a driving voltage for the horizontal scanning period, power consumption can be reduced due to charge recycling.

2.3 Specific Configuration Example Next, a specific configuration example for reusing charges will be described.

2.3.1 Charge Reuse of Source Line FIG. 17 shows a configuration example of the operational amplifier circuit block and the common line COL of FIG.

The configuration of each of the operational amplifier circuit blocks OPC _{1 to} OPC _N is the same, and the operational amplifier circuit block OPC ₁ will be described below.

The operational amplifier circuit block OPC ₁ includes a voltage follower-connected operational amplifier VOP ₁ and a source output switching circuit SSW ₁ . The source output switching circuit SSW ₁ includes a first source output switch SS ₁ and a first source short-circuit switch C ₂ SW ₁ . The first source output switch SS ₁ is on-off controlled by a control signal c1, xc1. The control signal xc1 is an inverted signal of the control signal c1. The first source short circuit switch C2SW ₁ is ON / OFF controlled by control signals cc and xcc. The control signal xcc is an inverted signal of the control signal cc. The output of the operational amplifier VOP ₁ is connected to the _first source output node SND ₁ via the _first source output switch SS ₁ . The first source output node SND ₁ is connected to a given source voltage output node SVND via a _first source short circuit switch CS2SW ₁ . The source voltage output node SVND is connected to the second capacitor element connection node C2ND via the source charge storage switch CSW. The source charge storage switch CSW is on / off controlled by control signals cs and xcs. The control signal xcs is an inverted signal of the control signal cs.

Thus, the first source short-circuit switch CS2SW ₁ is provided between the source voltage output node SVND and the first source output node SND ₁ . The source charge storage switch CSW is provided between the source voltage output node SVND and the second capacitor element connection node C2ND to which one end of the second capacitor element CCS is connected. Then, the first source output node SND ₁ and the second capacitor element connection node C2ND are temporarily electrically connected by the first source short circuit switch C2SW ₁ and the source charge storage switch CSW. Thereafter, the first source output node SND ₁ and the second capacitor element connection node C 2 ND are electrically cut off by the first source short-circuit switch C ₂ SW ₁ and the source charge storage switch CSW, and the first source output A voltage corresponding to the gradation data is supplied to the node SND ₁ .

More specifically, the first source short-circuit switch C2SW ₁ and the source charge storage are used in a state where the output of the operational amplifier VOP ₁ (source line drive circuit) is set to the high impedance state by the first source output switch SS ₁ . The first source output node SND ₁ , the source voltage output node SVND, and the second capacitor element connection node C 2 ND are electrically connected by the switch CSW. After that, the operational amplifier VOP ₁ is electrically disconnected from the first source output node SND ₁ and the second capacitor element connection node C2ND by the first source short circuit switch C2SW ₁ and the source charge storage switch CSW. The first source output switch SS ₁ supplies a voltage corresponding to the gradation data to the first source output node SND ₁ (source line S ₁ ).

  By the way, the common line COL including the source voltage output node SVND is similarly connected to the source short circuit switch of each operational amplifier circuit block.

That is, the display driver 60 is connected a source voltage output node SVND electrically, the common line COL having one end electrically connected to the source charge storage switch CSW, a second to the source line S ₂ A second source short-circuit switch C2SW ₂ provided between the second source output node SND _{2 to} which the output voltage is supplied and the common line COL can be included. A first source short-circuit switch C2SW ₁ is provided between the first source output node SND ₁ and the shared line COL. A second source short circuit switch C2SW ₂ is provided between the second source output node SND ₂ and the shared line COL.

  Further, the display driver 60 can include a discharge transistor DisTr. A control signal dis is supplied to the gate of the discharging transistor DisTr. A discharge voltage (for example, the system ground power supply voltage VSS) is supplied to the source of the discharge transistor DisTr, and the drain of the discharge transistor DisTr is electrically connected to the common line COL. Then, the voltage of the shared line COL is set to the discharge voltage by the control signal dis. Such a discharge transistor DisTr is commonly used for discharging the first and second source lines.

Note that, during the pixel electrode selection period of the display panel 12, the first and second source short-circuit switches C2SW ₁ and C2SW ₂ are set in a conductive state, and the discharge transistor DisTr is turned on, so that The two source lines S ₁ and S ₂ can be discharged. By so doing, so-called off-writing can be performed with a very simple configuration. Here, off writing means giving a given off voltage to the source line in order to shift to the display off state.

In addition, the operational amplifier circuit block OPC ₁ can further include a _first bypass switch BSW ₁ . The first bypass switch BSW ₁ is on / off controlled by control signals c2 and xc2. The control signal xc2 is an inverted signal of the control signal c2. In the operational amplifier circuit block OPC ₁ , after the charge recycling as described above is performed in the first half of one horizontal scanning period as a pixel selection period, the first source output is performed in the second driving period of the horizontal scanning period. The drive control of the source line S ₁ is performed by the switch SS ₁ and the first bypass switch BSW ₁ .

That is, in the first half of the driving period, the first source output switch SS ₁ is set in the conductive state and the first bypass switch BSW ₁ is set in the non-conductive state, and the operational amplifier VOP ₁ sets the first source output node SND. ₁ is driven. Thereafter, in the second half of the driving period, the operational amplifier is connected to the first source output node SND ₁ with the first source output switch SS _{1 set} in a non-conductive state and the first bypass switch BSW ₁ set in a conductive state. It provides an input voltage of VOP _1. Thus, the voltage set at the first source output node SND ₁ can be set at high speed and with high accuracy.

FIG. 18 shows a timing chart of a control example of the operational amplifier circuit block OPC ₁ of FIG.

In FIG. 18, when the control signals c1, c2, cc, cs, and dis in FIG. 17 are at the H level, each switch is set to ON (conductive state). In the example of FIG. 18, it is assumed that the control signal dis is always at the L level. In FIG. 18, only a control example of the operational amplifier circuit block OPC ₁ is described, but the operational amplifier circuit blocks OPC _{2 to} OPC _N are also controlled by the same control signal as the operational amplifier circuit block OPC ₁ .

In the charge recycling period, which is the first half of one horizontal scanning period, the control signals cc and cs are set to the H level, and the control signals c1 and c2 are set to the L level. As a result, the source charge storage switch CSW is set in a conductive state. Then, the first source output node SND ₁ and one end of the second capacitor element CCS connected to the second capacitor element connection terminal TL2 are set to the same potential. As a result, the charge of the second capacitor element CCS is reused, and the potential of the first source output node SND ₁ varies.

In the pre-buffer driving period of the subsequent driving period, the control signals cc and cs are at the L level, and the control signal c1 is at the H level. Note that, within the driving period, the source charge storage switch CSW is set to OFF (non-conducting state). As a result, the first source output node SND ₁ whose potential has changed within the charge recycling period is driven by the operational amplifier VOP ₁ . The operational amplifier VOP ₁ is supplied with the data voltage selected by the DAC 28. The operational amplifier VOP ₁ consumes an operating current, but can change the potential of the first source output node SND ₁ at high speed with high driving capability.

Next, in the DAC driving period of the driving period, the control signal c1 becomes L level and the control signal c2 becomes H level. Thus, the first source output node SND ₁ is electrically disconnected from the output of the operational amplifier VOP ₁ and the data voltage from the DAC 28 is directly supplied. Thereby, the voltage of the first source output node SND ₁ can be set to a highly accurate data voltage from the DAC 28. In the DAC drive period, the operation of the operational amplifier VOP ₁ can be stopped, so that power consumption can be reduced.

  By individually generating the control signals cc, xcc, c1, xc1, c2, and xc2 for each operational amplifier circuit block, as described above, it is possible to individually control whether or not charges can be reused for each source output. Become.

FIG. 19 shows a timing chart of another control example of the operational amplifier circuit block OPC ₁ of FIG.

  FIG. 19 shows a timing chart of a so-called off write control example. Control of the charge recycle period and switch control of the source charge storage switch CSW are the same as in FIG.

In the pre-buffer period and the DAC driving period of the driving period, the control signal cc is at the H level and the control signal dis is at the H level. As a result, the common line COL is set to the system ground power supply voltage VSS by the discharging transistor DisTr. Then, the first source output node SND ₁ whose potential has fluctuated within the charge reuse period is set to the system ground power supply voltage VSS via the _first source short-circuit switch C2SW ₁ set to the conductive state. The first voltage source output node SND ₁ is supplied to the first source line S _1, so-called off-writing control is performed. Thus, in the display panel 12, the voltage of the _first source output node SND ₁ supplied to the source line need only be written to the pixel electrode in the same manner as in the normal display operation.

The off-write control as described above is similarly performed in the operational amplifier circuit blocks OPC _{2 to} OPC _N. In this way, display off control can be performed with a very simple configuration without supplying a predetermined off voltage from the DAC.

2.3.2 Charge Reuse of Counter Electrode FIG. 20 shows a diagram of a configuration example of the counter electrode voltage generation circuit 56 of FIG.

  The counter electrode voltage generation circuit 56 generates a counter electrode voltage VCOM applied to the counter electrode CE facing the pixel electrode of the display panel (electro-optical device) 12 and the liquid crystal element (electro-optical material). The counter electrode voltage generation circuit 56 includes first and second operational amplifiers OP1 and OP2 that are operational amplifiers connected in voltage follower, and a switching circuit SEL. The first operational amplifier OP1 outputs a high potential side voltage VCOMH of the common electrode voltage VCOM. The second operational amplifier OP2 outputs a low potential side voltage VCOML of the common electrode voltage VCOM. The switching circuit SEL outputs one of the high potential side voltage VCOMH and the low potential side voltage VCOML as the counter electrode voltage VCOM in accordance with the polarity inversion timing for inverting the polarity of the voltage applied to the liquid crystal element (electro-optical material). To do. Note that the first and second operational amplifiers OP1 and OP2 may be operated as regulators.

  The switching circuit SEL includes a P-type (first conductivity type) metal oxide semiconductor (MOS) transistor (hereinafter simply referred to as a transistor) PTr and an N-type (second conductivity type) transistor NTr. Can do. The source of the transistor PTr is connected to the output of the first operational amplifier OP1. The drain of the transistor PTr is electrically connected to the counter electrode CE. A control signal XPOLc is supplied to the gate of the transistor PTr. The source of the transistor NTr is connected to the output of the second operational amplifier OP2. The drain of the transistor NTr is electrically connected to the counter electrode CE. A control signal POLc is supplied to the gate of the transistor NTr.

  The control signals XPOLc and POLc are generated based on the polarity inversion signal POL that defines the polarity inversion timing. The switching circuit SEL can output the high potential side voltage VCOMH or the low potential side voltage VCOML based on the control signals XPOLc and POLc. The switching circuit SEL can set its output to a high impedance state based on the control signals XPOLc and POLc.

  Such a counter electrode voltage generation circuit 56 can include a VCOMH generation circuit (counter electrode high potential side voltage generation circuit) 62 and a VCOML generation circuit (counter electrode low potential side voltage generation circuit) 64. The VCOMH generation circuit 62 can generate the voltage VCOMH0 by a known charge pump operation based on, for example, the system ground power supply voltage VSS and the power supply voltage VDDHS. The voltage VCOMH0 is supplied to the input of the first operational amplifier OP1. The VCOML generation circuit 64 can generate the voltage VCOML0 by a known charge pump operation based on, for example, the system ground power supply voltage VSS and the power supply voltage VDDHS. The voltage VCOML0 is supplied to the input of the second operational amplifier OP2.

  When the switching circuit SEL outputs the high potential side voltage VCOMH as the common electrode voltage VCOM, the common electrode voltage generation circuit 56 performs control to stop or limit the operating current of the second operational amplifier OP2 by a control signal (not shown). Do. In addition, when the switching circuit SEL outputs the low potential side voltage VCOML as the common electrode voltage VCOM, the common electrode voltage generation circuit 56 performs control to stop or limit the operating current of the first operational amplifier OP1 by a control signal (not shown). .

  Thus, when one of the high potential side voltage VCOMH and the low potential side voltage VCOML of the common electrode voltage VCOM is applied to the common electrode CE, an operational amplifier that outputs the other of the high potential side voltage VCOMH and the low potential side voltage VCOML. Therefore, it is possible to reduce current consumption unnecessary for generating the common electrode voltage VCOM.

  The output of the switching circuit SEL is electrically connected to the common electrode voltage output node VND. The common electrode voltage output node VND is electrically connected to the first capacitor element connection node C1ND to which one end of the first capacitor element is connected. The first capacitor element connection node C1ND is electrically connected to the counter electrode CE of the display panel 12 through the counter electrode voltage output terminal TL3.

  The common electrode charge storage switch VSW is provided between the first capacitor element connection node C1ND and the common electrode voltage output node VND via the electro-optic material. The common electrode charge storage switch VSW is on / off controlled by control signals cv and xcv. The control signal xcv is an inverted signal of the control signal cv.

  When the common electrode voltage VCOM is changed, the common electrode voltage output node VND and the first capacitor element connection node C1ND are once electrically connected by the common electrode charge storage switch VSW and then the common electrode voltage output node. The counter electrode voltage VCOM is supplied to VND. More specifically, with the output of the common electrode voltage generation circuit 56 (switching circuit SEL) set to a high impedance state, the common electrode voltage output node VND is connected to the first capacitor element by the common electrode charge storage switch VSW. After electrically connecting the node C1ND, the common electrode voltage generation circuit 56 (switching circuit SEL) supplies the common electrode voltage VCOM to the common electrode CE.

In the present embodiment, the gradation voltage corresponding to the intermediate gradation value is employed as the reference voltage Vref, but is not limited to this. For example, ideally, the reference voltage may be an intermediate voltage (= (V _H + V _L ) / 2) between the highest voltage V _H and the lowest voltage V _L of the gradation voltage. By using the intermediate voltage as the reference voltage Vref, the circuit configuration can be simplified.

2.4 Modification In the present embodiment, the reference voltage Vref has been described as a fixed voltage having a gradation voltage corresponding to the intermediate gradation value, but the present invention is not limited to this. It is possible to change the level of the reference voltage Vref by fetching all 6 bits of gradation data from the line latch 26 _L and comparing it with given reference data to determine whether it is larger than the reference data. .

  FIG. 21 shows a main configuration part of the source line drive circuit 20 in a modification of the present embodiment. In FIG. 21, the configuration per output is shown in the same manner as in FIG. 11. In FIG. 21, the same parts as those in FIG.

In Figure 21, it is provided charge recycle control section 200 _L in place of the charge recycle control section 100 _L of FIG. The charge reuse control unit 200 _L includes a threshold value determination unit 210 _L , a latch 220 _L , and a gradation data determination unit 230 _L. The threshold value determination unit 210 _L, the reference data is input as the threshold data. Threshold determination unit 210 _L is the grayscale data D from the reference data and the line latch 26 _L [5: 0] are compared, and outputs a comparison result signal of the comparison result. Latch 220 _L is a change in the timing of the horizontal synchronization signal LP, latches the comparison result signal from the threshold determination unit 210 _L. Gradation data determination unit 230 _L compares the comparison result signal latched comparison result signal and the latch 220 _L from the threshold determination unit 210 _L. That is, the comparison result is latched by the latch 220 _L signal is a first comparison result obtained by comparing the first gray-scale voltage supplied to the source line in the horizontal scanning period immediately before and the given reference data. Comparison result from the threshold determination unit 210 _L signal, second comparing the second tone data and the reference data to generate a second gradation voltage supplied to the source line to the horizontal scanning period It is a comparison result.

Based on the output from the grayscale data determination unit 230 _L, the switch control of the source output switch circuit SSW _L is performed.

With this configuration, threshold decision unit 210 _L is, the reference data and the gray scale data D: comparing the [5 0], for example, the grayscale data D [5: 0] is determined whether greater than the reference data smaller Thus, it can be determined whether the gradation voltage corresponding to the gradation data D [5: 0] is on the higher potential side or the lower potential side than the gradation voltage corresponding to the reference data. As a result, captured by the latch 220 _L, by the gradation data determination unit 230 _L, in two consecutive horizontal scanning periods, the gray-scale data D [5: 0] grayscale voltage corresponding is corresponding to the reference data in the It is determined for each source output whether both are larger or smaller than the gradation voltage. Such charge recycle control section 200 _L, in two consecutive horizontal scanning periods, the gray-scale data D [5: 0] are large or than the gradation voltage gradation voltage corresponding is corresponding to the reference data in the when it is determined that both small, the source output switch circuit SSW _L is not short-circuited with the common line COL source line S _L, higher potential than the grayscale voltage one of the two gray scale voltages corresponding to the reference data When the other side is determined to be at a lower potential side than the gradation voltage corresponding to the reference data, a short circuit occurs .

In this way, it is possible to determine whether the gradation voltage in two consecutive horizontal scanning periods is higher or lower than the settable voltage between the highest voltage V _H and the lowest voltage _VL . It becomes possible to reuse or omit the reuse of electric charge.

  In the present embodiment, the display driver 60 for driving the display panel 12 shown in FIG. 1 or 2 has been described. However, the present invention is not limited to this.

  FIG. 22 shows an outline of another configuration example of the display panel.

In FIG. 22, the same parts as those in FIG. 1 or FIG. The display panel 300 of FIG. 22 includes a demultiplexer for each source output driven by the display driver. That includes a demultiplexer DMUX _{L + 1} corresponds to correspond to the source line _{S L} demultiplexer DMUX _L, the source line _{S L + 1.} The demultiplexer DMUX divides each source output into three color component source lines. In the display panel 300, the source of the TFT is connected to each color component source line. Therefore, by outputting the data voltage corresponding to the gradation data for 3 dots to each source output in a time division manner, the demultiplexer DMUX separates the time division multiplexed data voltage to each color component source line. Can be output.

  FIG. 23 shows a main configuration part of a display driver for driving the display panel of FIG.

In FIG. 23, the same parts as those in FIG. In the display driver of FIG. 23, a data voltage of 3 dots is time-division multiplexed in advance and input to each operational amplifier block. Then, by supplying the time division multiplex timing signal to the display panel 300, each of the demultiplexers DMUX _{1 to} DMUX _N can separate each source output.

Note that the demultiplexers DMUX _{1 to} DMUX _N of FIG. 22 may be provided on the display driver side as shown in FIG. That is, the display driver 302 includes a demultiplexer for separating the time-divided voltage of each source output node into a plurality of output voltages, and supplies each output voltage of the plurality of output voltages to each source line of the display panel. To do. In this case, it is not necessary to supply a time division multiplexed timing signal of the data voltage to the display panel, so that the mounting area can be further reduced.

3. Electronic Device FIG. 25 shows a block diagram of a configuration example of an electronic device in the present embodiment. Here, a block diagram of a configuration example of a mobile phone is shown as an electronic device.

  The mobile phone 900 includes a camera module 910. The camera module 910 includes a CCD camera, and supplies image data captured by the CCD camera to the display controller 540 in the YUV format. The display controller 540 has the function of the display controller 40 of FIG. 1 or FIG.

  The mobile phone 900 includes a display panel 512. The display panel 512 is driven by the source driver 520 and the gate driver 530. The display panel 512 includes a plurality of gate lines, a plurality of source lines, and a plurality of pixels. The display panel 512 has the function of the display panel 12 shown in FIG.

  The display controller 540 is connected to the source driver 520 and the gate driver 530 and supplies gradation data in RGB format to the source driver 520.

  The power supply circuit 542 is connected to the source driver 520 and the gate driver 530, and supplies a driving power supply voltage to each driver. The power supply circuit 542 has the function of the power supply circuit 50 in FIG. 1 or FIG. The display driver 544 includes a source driver 520, a gate driver 530, and a power supply circuit 542, and the display driver 544 can drive the display panel 512.

  The host 940 is connected to the display controller 540. The host 940 controls the display controller 540. In addition, the host 940 can demodulate the gradation data received via the antenna 960 by the modem 950 and then supply it to the display controller 540. The display controller 540 causes the display panel 512 to display the source driver 520 and the gate driver 530 based on the gradation data. The source driver 520 has the function of the source line driver circuit 20 shown in FIG. The gate driver 530 has a function of the gate line driving circuit 30 of FIG. 1 or FIG.

  The host 940 can instruct transmission to another communication device via the antenna 960 after the modulation / demodulation unit 950 modulates the gradation data generated by the camera module 910.

  The host 940 performs gradation data transmission / reception processing, imaging of the camera module 910, and display processing of the display panel 512 based on operation information from the operation input unit 970.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, the present invention is not limited to being applied to driving the above-described liquid crystal display panel, but can be applied to driving electroluminescence and plasma display devices.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

4 is a block diagram example of the liquid crystal device of the present embodiment. FIG. The block diagram of the other structural example of the liquid crystal device in this embodiment. FIG. 3 is a block diagram of a configuration example of the source line driver circuit in FIG. 1 or FIG. 2. FIG. 4 is a diagram illustrating a configuration example of a gradation voltage generation circuit, a DAC, and an output buffer in FIG. 3. FIG. 3 is a diagram illustrating a configuration example of a gate line driving circuit in FIG. 1 or FIG. 2. The figure which shows the structural example of the power supply circuit of FIG. 1 or FIG. FIG. 3 is a diagram showing an example of a drive waveform of the display panel of FIG. 1 or FIG. 2. FIG. 2 is a diagram illustrating a principle configuration of a liquid crystal device according to an embodiment. FIG. 9 is a waveform diagram of an operation example of the liquid crystal device of FIG. 8. FIG. 9 is a waveform diagram of another operation example of the liquid crystal device of FIG. 8. FIG. 4 is a diagram showing a configuration main part of the source line driver circuit of FIG. 3. FIG. 12 is an explanatory diagram of a control example of the charge reuse control unit of FIG. 11. FIG. 13A and FIG. 13B are explanatory diagrams of the effect of charge recycle control of this embodiment. FIGS. 14A and 14B are explanatory diagrams of the effect of charge recycle control according to the present embodiment. Explanatory drawing of the effect of the charge reuse control of this embodiment. Explanatory drawing of the effect of the charge reuse control of this embodiment. The figure which shows the structural example of the operational amplifier circuit block of FIG. 8, and a shared line. FIG. 18 is a timing diagram of a control example of the operational amplifier circuit block of FIG. 17. FIG. 18 is a timing chart of another control example of the operational amplifier circuit block of FIG. 17. FIG. 7 is a diagram illustrating a configuration example of the common electrode voltage generation circuit in FIG. 6. The figure which shows the structure principal part of the source line drive circuit in the modification of this embodiment. The figure which shows the outline | summary of the other structural example of a display panel. FIG. 23 is a diagram showing a main configuration part of a display driver that drives the display panel of FIG. 22; FIG. 23 is a diagram showing another configuration main part of a display driver that drives the display panel of FIG. 22; 1 is a block diagram of a configuration example of an electronic device according to an embodiment.

Explanation of symbols

10 liquid crystal device, 12 display panel, 20 source line drive circuit,
26 _L line latch, 28 _L DAC, 29 _L output buffer,
30 gate line drive circuit, 40 display controller, 50 power supply circuit,
60 display driver, 100 _L charge recycle control unit, 110 _L latch,
120 _L gradation data determination unit, CCS second capacitor element, CCV first capacitor element,
COL common line, CSW source charge storage switch, _G 1 ~G _M gate lines,
D grayscale data, OPC _L operational amplifier circuit block, _S 1 to S _N source line,
SSW _{1 to} SSW _N source output switching circuit, TL 1 first capacitor element connection terminal,
TL2 Second capacitor element connection terminal, VSW Counter electrode charge storage switch

Claims (11)

A drive circuit for driving a source line of an electro-optical device based on gradation data,
A source line driver for supplying a gradation voltage corresponding to gradation data to the source line;
A source output switching unit for short-circuiting the source line with a common line connected to a capacitor before the source line is driven by the source line driving unit;
A charge reuse control unit that controls the source output switching unit,
The charge reuse controller
For each source output, according to the first gradation voltage supplied to the source line in the immediately preceding horizontal scanning period and the second gradation voltage supplied to the source line in the horizontal scanning period, the source line Whether or not to short-circuit the common line,
The source output switching unit is
Based on the determination result of the charge recycling control unit, the source line is short-circuited with the shared line ,
A first capacitor element connection node to which one end of the first capacitor element is connected and a counter electrode voltage output node to which a voltage of a counter electrode facing the pixel electrode of the electro-optical device is supplied via an electro-optical material. A counter electrode charge storage switch provided therebetween,
After the counter electrode voltage output node and the first capacitor element connection node are electrically connected once by the counter electrode charge storage switch, the counter electrode voltage is supplied to the counter electrode voltage output node and the counter A drive circuit for driving an electrode .
A drive circuit characterized by that. In claim 1,
The charge reuse controller
For each source output, determine whether the first and second gradation voltages are both higher potential side or lower potential side than a given reference voltage,
The source output switching unit is
When the charge recycle control unit determines that the first and second gradation voltages are both higher or lower than the reference voltage, the source line is short-circuited to the shared line. And a short circuit when one of the first and second gradation voltages is determined to be higher than the reference voltage and the other is determined to be lower than the reference voltage . In claim 1 or 2,
The charge reuse controller
The most significant bit data of the first gradation data for generating the first gradation voltage and the most significant bit data of the second gradation data for generating the second gradation voltage And determining whether or not the source line is short-circuited with the shared line based on the comparison result. In claim 3,
The reference voltage is
A driving circuit having a gradation voltage corresponding to an intermediate gradation value. In claim 1 or 2,
The charge reuse controller
A first comparison result of comparing the first gradation data for generating the first gradation voltage and given reference data, and a second comparison result for generating the second gradation voltage A drive circuit that determines whether or not the source line is short-circuited to the shared line based on a second comparison result obtained by comparing gradation data and the reference data. In claim 5,
The charge reuse controller
For each source output, determine whether the first and second gradation data are both larger or smaller than the reference data,
The source output switching unit is
When the charge reuse controller determines that the first and second gradation data are both larger or smaller than the reference data, the source line is not short-circuited with the shared line, and the first And a driving circuit that is short-circuited when it is determined that one of the second gradation data is larger than the reference data and the other is smaller than the reference data . In any one of Claims 1 thru | or 6.
A first source short-circuit switch provided between a first source output node to which an output voltage to the first source line of the electro-optical device is supplied and the shared line;
A source charge storage switch provided between a second capacitor element connection node to which one end of the second capacitor element is connected and the shared line;
After the first source output node and the second capacitor element connection node are electrically connected once by the first source short circuit switch and the source charge storage switch, the first source short circuit switch or the source charge A voltage corresponding to grayscale data is supplied to the first source output node in a state where the first source output node and the second capacitor element connection node are electrically cut off by a storage switch, A driving circuit for driving a first source line. Multiple source lines,
Multiple gate lines,
A plurality of pixel electrodes in which each pixel electrode is specified by each gate line and each source line;
A counter electrode facing the plurality of pixel electrodes;
Electro-optical device which comprises a driving circuit according to any one of claims 1 to 7 for driving the plurality of source lines. Electro-optical device which comprises a driving circuit according to any one of claims 1 to 7. An electronic apparatus comprising the driving circuit according to any one of claims 1 to 7. An electronic apparatus comprising the electro-optical device according to claim 8 .

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