JP4226444B2 - Drive device and power conversion device - Google Patents

Description

  The present invention relates to a drive device for driving a switching device included in an inverter or the like and a power conversion device equipped with the drive device.

  For example, when a DC voltage source is adopted as a power source for a single-phase AC motor or a three-phase AC motor, a power converter that converts a DC voltage generated by the DC voltage source into an AC voltage is used. An example of this power conversion apparatus is an inverter configured by connecting switching devices to a totem pole connection (preparing switching devices on the low voltage side and the high voltage side and connecting them in series).

  In order to drive each switching device included in the inverter, a driving device that performs switching control of on / off of each switching device at an appropriate timing is necessary. The driving device includes a low voltage side driving circuit for driving the low voltage side switching device and a high voltage side driving circuit for driving the high voltage side switching device. In the high voltage side drive circuit, a level shift circuit is provided to convert both the on / off control signal into a high potential signal.

  An example of such a driving device is shown in Patent Document 1 below. That is, in FIG. 7 of Patent Document 1, a circuit configuration of a power conversion device including the drive device and the inverter is shown. FIG. 7 shows a half-bridge power device 19 configured by totem pole connection of power semiconductor devices 17 and 18 as switching devices. A load 21 such as a single-phase AC motor is connected between the connection point N1 of the power semiconductor devices 17 and 18 and the ground potential COM.

  Drive circuits HD and LD are connected to the power semiconductor devices 17 and 18, respectively. Of the high voltage side drive circuit HD, the pulse generation circuit 1 generates a pulse-like on / off signal in accordance with an input signal from the outside. These on and off signals are transmitted through N-type high-voltage field-effect transistors (high-voltage N-channel MOS: HNMOS transistors) 2 and 3 which are level-shifting field-effect transistors, and inverters 6 and 7, respectively. These become the set signal and reset signal for the set-reset flip-flop circuit 10 respectively.

  In the high voltage side drive circuit HD, a dv / dt transient signal that is a propagation signal of a fast voltage change is applied to the line L1 from the connection point N1 to the anodes of the diodes 8 and 9 according to the switching state of the half-bridge power device 19. Will occur. Since a parasitic capacitance C exists between the drain and source of the HNMOS transistors 2 and 3, a dv / dt current obtained by the product of the parasitic capacitance C and the dv / dt transient signal flows through the HNMOS transistors 2 and 3 simultaneously.

  Since the dv / dt current flowing through the HNMOS transistors 2 and 3 is at the same level as the current flowing during normal switching, a voltage drop occurs at the level shift resistors 4 and 5 at the same time. As a result, “H (positive value in positive logic)” is simultaneously given as the set input and reset input of the set-reset flip-flop circuit 10. In general, it is prohibited to simultaneously input “H” to the set input and the reset input of the non-inverting input type set-reset flip-flop circuit 10, and an unpredictable operation, that is, a malfunction occurs. In order to prevent this malfunction, a protection circuit 26 b as shown in FIG. 8 of Patent Document 1 is provided between the level shift circuit 25 and the set / reset flip-flop circuit 10.

  An example of realizing such a level shift circuit 25 on a semiconductor substrate is shown in Patent Document 2 below. FIG. 7 of the following Patent Document 2 is a diagram showing one circuit on the on signal side or the off signal side of the level shift circuit 25 of FIG. 8 of the following Patent Document 1, and FIG. It is sectional drawing which shows the specific structure in an apparatus.

  In addition to Patent Documents 1 and 2 listed above, Patent Document 3 exists as prior art document information related to the invention of this application.

JP 2001-196906 A JP 2001-25235 A JP-A-11-145313

  In Patent Document 2, the parasitic diode D10 between the source and drain of the level shift field effect transistor 11 and the wide pn junction surface in the semiconductor substrate 19 when the potential at the terminal VS1 becomes negative. The malfunction in the inverter (configured by transistors 14 and 15) subsequent to the level shift field effect transistor 11 due to the parasitic diode D20 in FIG.

  However, the problem caused by the parasitic diodes D10 and D20 is not limited to this. The new problem will be described with reference to the circuit diagram of FIG. 8 of Patent Document 1 and the sectional view of FIG. 8 of Patent Document 2.

When the potential at the terminal VS1 becomes negative (period B in FIG. 9 of Patent Document 2), the parasitic diode D20 at the pn junction surface between the p layer 21 and the n ⁻ layer 22 passes a current I20 to the terminal VS1. In addition, a parasitic current is passed through the drain electrode 30 via the n ⁺ region 25. That is, the parasitic diode D20 also acts as a parasitic diode between the p layer 21 and n ⁻ layer 22 which are the body of the level shift field effect transistor 11 and the drain.

  The parasitic current flowing in the body-drain parasitic diode D20 and the current I10 flowing in the parasitic diode D10 between the source and drain may be combined to reach the terminal VB1 via the resistance element 12. In this case, a voltage drop occurs in the level shift resistor 12, and the potentials at the input terminals VR1 and VR2 of the inverter circuits 6 and 7 in the circuit diagram of FIG. To rise.

Note that the value of the parasitic current flowing between the body and the drain is larger than the value of the current I10 flowing through the parasitic diode D10. This is because the pn junction surface between the p layer 21 and the n ⁻ layer 22 is wider than the pn junction surface between the p ⁺ region 24 and the n ⁻ layer 22, and the amount of current flowing in the former is larger.

  However, in this case, since the potentials at the input terminals VR1 and VR2 only rise and do not fall, "H" does not appear at the output terminals of the inverter circuits 6 and 7. Therefore, there is no problem of malfunction of the set / reset flip-flop circuit 10.

  On the other hand, when the potential at the terminal VS1 returns from negative to 0 (period after B in FIG. 9 of Patent Document 2), the parasitic diodes D10 and D20 are temporarily biased in the opposite direction. As a result, reverse recovery current flows through the parasitic diodes D10 and D20. In this case, a voltage drop in the opposite direction to that of the level shift resistor 12 temporarily occurs in the level shift resistor 12, and the potential relatively decreases at the input terminals VR1 and VR2 of the inverter circuits 6 and 7.

  Also in this case, the value of the parasitic current flowing between the body and the drain is larger than the value of the current flowing in the parasitic diode D10. Therefore, the former parasitic current has a larger contribution to the reverse voltage drop in the level shift resistor 12.

  Here, if the potential at the input terminals VR1 and VR2 falls below the “L” threshold value of the inverter circuits 6 and 7, “H” appears at the output terminals of the inverter circuits 6 and 7. When "H" appears as an in-phase pulse at the output terminals of the inverter circuits 6 and 7, the in-phase pulse can be removed by the protection circuit 26b in the subsequent stage, and the malfunction of the set / reset flip-flop circuit 10 can be prevented.

  However, when the potential drop on one side of the input terminals VR1 and VR2 is remarkable and the potential drop on the other side is not so great, a pulse appears at one output terminal of the inverter circuits 6 and 7, and the other A situation occurs in which no pulse appears at the output end. Then, an incorrect set signal or reset signal may be input to the set / reset flip-flop circuit 10.

  In other words, an incorrect set signal may be input to the set-reset flip-flop circuit 10 during the period when the high-voltage power semiconductor device 17 should be off in the circuit diagram of FIG. In this case, although the power semiconductor device 17 should be kept off, the power semiconductor device 17 shifts to the on state, and both the power semiconductor devices 17 and 18 are turned on, which may cause malfunction.

  The present invention has been made in view of the above circumstances, and even if a reverse recovery current flows through the body-drain parasitic diode of the level shift field effect transistor and a voltage drop occurs in the level shift resistor, the switching device malfunctions. An object of the present invention is to provide a drive device and a power conversion device that are difficult to generate.

  The invention according to claim 1 is a driving device for driving a switching device, comprising a level shift circuit for level-shifting the potential of at least one signal and outputting it as at least one level-shifted signal. In response to a change in the potential of one level-shifted signal, the switching device is turned on or off, and the level shift circuit has a drain, a body, a gate to which the signal is applied, and a first potential. A level-shifting field effect transistor having a given source, a level-shifting resistor having one end connected to the drain of the level-shifting field-effect transistor and the other end to which a second potential is given, and the level An input end connected to the one end of the shift resistor, and an output end; An inverter for outputting a bell-shifted signal from the output terminal, a body resistor having one end to which the first potential is applied, and the other end connected to the body of the level-shifting field effect transistor A drive unit including at least one circuit unit.

  The invention according to claim 5 includes the drive device according to claim 1 and a switching device driven by the drive device, wherein the switching device performs switching control as to whether or not power is supplied to a load. It is a conversion device.

  According to invention of Claim 1, body resistance is inserted. Therefore, the voltage between the first and second potentials can be divided by the body resistance and the level shift resistance. As a result, even when a reverse recovery current flows through the body-drain parasitic diode of the level shift field effect transistor and a voltage drop occurs in the level shift resistor, voltage fluctuation at the input terminal of the inverter can be suppressed. . Therefore, it is possible to obtain a drive device that is unlikely to cause a malfunction in the switching device.

  According to the fifth aspect of the present invention, the driving apparatus according to the first aspect and the switching device driven thereby are provided. Therefore, a power conversion device that is unlikely to cause a malfunction in the switching device can be obtained.

  The embodiment of the present invention is a drive device in which a malfunction is not generated in a switching device by inserting a body resistance into the body of a level shift field effect transistor, and a power conversion device equipped with the drive device.

  FIG. 1 is a circuit diagram showing a power conversion apparatus 100 according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing in detail the periphery of the level shift circuit LV1 and the protection circuit DV1 in the power conversion apparatus 100.

  As shown in FIG. 1, in the power conversion apparatus 100, a power supply 15 that supplies a power supply potential Vdd to a ground potential COM is provided, and a half-bridge power device 14 is provided between the power supply potential Vdd and the ground potential COM. Is provided. The half-bridge type power device 14 includes switching devices 17 and 18 such as IGBT (Insulated Gate Bipolar Transistor), and the switching devices 17 and 18 are totem pole connected.

  Further, free wheel diodes D1 and D2 are connected in reverse parallel to the switching devices 17 and 18. A load (inductive load such as a motor) 21 is connected between the connection point N1 of the switching devices 17 and 18 and the ground potential COM.

  The switching device 17 is a device that switches between the reference potential VS1 and the power supply potential Vdd supplied by the power supply 15 with the potential at the connection point N1 as a reference potential, and is called a high potential side switching device. On the other hand, the switching device 18 is called a low potential side switching device.

  The switching devices 17 and 18 have a function of performing switching control as to whether or not power is supplied to the load 21 by applying a voltage between the power supply potential Vdd and the ground potential COM, for example.

  The power conversion apparatus 100 illustrated in FIG. 1 includes a high potential side switching device driving device HD that drives the switching device 17 and a low potential side switching device driving device LD that drives the switching device 18. The low potential side switching device driving device LD is not related to the present invention and will not be described.

  The configuration of the high potential side switching device driving device HD will be described below. A pulse generating circuit 1 is provided in the high potential side switching device driving device HD, and the pulse generating circuit 1 generates a pulse in accordance with an input signal supplied from a microcomputer (not shown) provided outside. The on-state signal and the off-state signal are generated.

  The two outputs of the pulse generation circuit 1 are connected to the gates of N-type high-voltage N-channel metal oxide semiconductor transistors (HNMOS transistors) 2 and 3, which are level-shifting field-effect transistors. Yes. The drains of the HNMOS transistors 2 and 3 are connected to one ends of the level shift resistors 4 and 5, respectively, and are also connected to the input ends of the inverters 6 and 7. The ground potential COM is applied to the sources of the HNMOS transistors 2 and 3.

  HNMOS transistors 2 and 3, level shift resistors 4 and 5, and inverters 6 and 7 are all included in level shift circuit LV1. The level shift circuit LV1 shifts the potential of the on signal and the off signal of the pulse generation circuit 1 in level. Specifically, the HNMOS transistor 2, the level shift resistor 4, and the inverter 6 collectively shift the potential of the off signal IN 1 and output it as the first level shifted signal C. In addition, the HNMOS transistor 3, the level shift resistor 5 and the inverter 7 are combined to level shift the potential of the ON signal IN2 and output it as the second level shifted signal B.

  The outputs of the inverters 6 and 7 are connected to the set terminal S and the reset terminal R of the high active type set / reset flip-flop circuit 10, respectively. The output terminal Q of the set / reset flip-flop circuit 10 is connected to the gate of the NMOS transistor 12 and also to the input terminal of the inverter 11. The output terminal of the inverter 11 is connected to the gate of the NMOS transistor 13.

  The source of the NMOS transistor 13 is connected to the connection point N1. The source of the NMOS transistor 12 is connected to the drain of the NMOS transistor 13 and also to the gate electrode of the switching device 17. A high potential side DC power supply 16 is provided between the drain of the NMOS transistor 12 and the connection point N1.

  The other ends of the level shift resistors 4 and 5 are connected to the drain of the NMOS transistor 12. That is, the positive potential output VB1 of the high potential side power source 16 is supplied to the other ends of the level shift resistors 4 and 5. The source of the NMOS transistor 13 is connected to the anode of the diode 8 and the anode of the diode 9. That is, the negative potential output VS1 of the high potential side power supply 16 is applied to the source of the NMOS transistor 13 and the anodes of the diodes 8 and 9. The cathodes of diodes 8 and 9 are connected to the drains of HNMOS transistors 2 and 3, respectively.

  In such a high potential side switching device driving device HD, a rapid voltage change is propagated to a line (referred to as line L1) from the connection point N1 to the anodes of the diodes 8 and 9 depending on the switching state of the half-bridge type power device 14. A dv / dt transient signal is generated. Since a parasitic capacitance C exists between the drain and source of the HNMOS transistors 2 and 3, a current (referred to as a dv / dt current) obtained by the product of the parasitic capacitance C and the dv / dt transient signal is the HNMOS transistor 2 and 3 flows simultaneously.

  Since the dv / dt current flowing through the HNMOS transistors 2 and 3 is at the same level as the current flowing during normal switching, a voltage drop occurs at the level shift resistors 4 and 5 at the same time. As a result, “H (positive logical value High in high active)” is simultaneously given as the set input and reset input of the set-reset flip-flop circuit 10. In general, simultaneous input of “H” to the set input and reset input of the high active set-reset flip-flop circuit 10 is prohibited, and an unpredictable operation, that is, a malfunction occurs.

  In order to prevent such a malfunction, a protection circuit DV1 is inserted between the level shift circuit LV1 and the set / reset flip-flop circuit 10 using a combinational logic circuit as shown in FIG. The configuration of the protection circuit DV1 is as follows. That is, a signal obtained by level-shifting the ON signal, the first level-shifted signal B that is also the output of the inverter 7, and a signal obtained by level-shifting the OFF signal and the NAND circuit G101 that is input to both input terminals. The NAND circuit G121 to which the second level-shifted signal C, which is also the output of 6 is input to both input terminals, and the NAND circuit G111 to which the first and second level-shifted signals B and C are input are It is provided in the first stage. Inverters G102 and G104 connected in series to the NAND circuit G101, inverters G122 and G124 connected in series to the NAND circuit G121, and an inverter G112 connected to the NAND circuit G111, respectively. The outputs D and F of the inverters G104 and G112 are input to the NOR circuit G13, and the outputs E and F of the inverters G124 and G112 are input to the NOR circuit G14. The outputs G and H of these NOR circuits G13 and G14 serve as a set signal and a reset signal for the set / reset flip-flop circuit 10, respectively.

  When “H” is output from the output terminal Q of the set-reset flip-flop circuit 10, the NMOS transistor 12 is turned on and the NMOS transistor 13 is turned off. Therefore, the positive potential output VB 1 of the high potential side power supply 16 is given to the gate of the switching device 17 through the NMOS transistor 12. As a result, the switching device 17 becomes conductive.

  Further, when “L (negative logic value Low in high active)” is output from the output terminal Q of the set-reset flip-flop circuit 10, the NMOS transistor 12 is turned off and the NMOS transistor 13 is turned on. Therefore, the negative potential output VS1 of the high potential side power supply 16 is supplied to the gate of the switching device 17 via the NMOS transistor 13. As a result, the switching device 17 is turned off.

  That is, the switching device 17 becomes conductive or non-conductive in accordance with changes in the potentials of the first and second level-shifted signals B and C.

  When the dv / dt transient signal flows on the line L1, the first and second level-shifted signals are simultaneously input to the protection circuit DV1. At this time, the logical values of the signal passing through the NAND circuit G101 and the inverters G102 and G104, the signal passing through the NAND circuit G121 and the inverters G122 and G124, and the signal passing through the NAND circuit G111 and the inverter G112 are reversed. Therefore, the NOR circuit G13 prevents the set signal from being output to the set / reset flip-flop circuit 10. Similarly, the NOR circuit G14 prevents the output of the reset signal to the set / reset flip-flop circuit 10. Therefore, malfunction of the set / reset flip-flop circuit 10 can be prevented.

  In the power semiconductor device according to the present invention, body resistors R1 and R2 are respectively provided between the bodies of the HNMOS transistors 2 and 3 and the ground potential COM as shown in FIG. That is, the level shift circuit LV1 includes a circuit unit including the HNMOS transistor 2, the level shift resistor 4, the inverter 6 and the body resistor R1, and the HNMOS transistor 2, the level shift resistor 4, the inverter 6 and the body resistor R2. And other circuit parts.

  FIG. 3 is a top view showing a part of a semiconductor substrate 19 such as a silicon substrate on which the power conversion device 100 according to the embodiment of the present invention is formed. 4 is a cross-sectional view taken along section line IV-IV shown in FIG.

  In FIG. 3, in the high potential side switching device driving device HD, the formation region of the HNMOS transistors 2 and 3 and the high voltage circuit part formation region HVa are shown. Level shift resistors 4 and 5 and inverters 6 and 7 are formed in the high voltage circuit portion formation region HVa.

  Further, as shown in FIG. 3, the surface of the semiconductor substrate 19 includes conductive wirings LNa˜, such as aluminum wiring, so as to surround the formation region of the HNMOS transistors 2 and 3 and the periphery of the high voltage circuit part formation region HVa. LNd is formed. Note that a pad PD for applying a ground potential COM is connected to the conductive wiring LNa. In addition, contact plugs 80a to 80h for electrical connection to semiconductor layers in the semiconductor substrate 19 are connected to the conductive wirings LNa to LNd.

  In FIG. 4, the cross-sectional structures of the HNMOS transistor 2 and the inverter 6 are shown.

The semiconductor substrate 19 has a stacked structure of a p-type semiconductor layer 21 exposed on the lower main surface, and an n ⁻ -type semiconductor layer 22 formed thereon and exposed on the upper main surface. Circuit elements such as the HNMOS transistor 2 and the inverter 6 are formed in the n ⁻ -type semiconductor layer 22.

In the region where the HNMOS transistor 2 is formed, the n ⁺ region 25 is selectively formed on the upper main surface of the n ^{− type} semiconductor layer 22 in the central portion thereof, and the p well region 24 is formed in the n ^{− type} in the peripheral portion thereof. It is selectively formed on the upper main surface of the semiconductor layer 22. An n ⁺ region 50 and a p ⁺ region 51 are selectively formed on the exposed surface of the p well region 24. The p well region 24, the n ⁺ region 50, and the p ⁺ region 51 are formed in an annular shape centering on the n ⁺ region 25.

An exposed surface of the p well region 24 sandwiched between the n ^{− type} semiconductor layer 22 and the n ⁺ region 50 functions as a channel region 49. A gate electrode 29 is opposed to the channel region 49 with the insulating film 20 interposed therebetween. A drain electrode 30 is connected to the n ⁺ region 25, and a source electrode 28 is connected to both the n ⁺ region 50 and the p ⁺ region 51.

In the region where inverter 6 is formed, p well region 23, p ⁺ region 27, p ⁺ region 44 and n ⁺ region 43 are selectively formed on the upper main surface of n ^{− type} semiconductor layer 22. A p ⁺ region 48, an n ⁺ region 47, and an n ⁺ region 45 are selectively formed on the exposed surface of the p well region 23.

An exposed surface of p well region 23 sandwiched between n ⁺ region 47 and n ⁺ region 45 functions as a channel region of an N channel MOS transistor which is a part of CMOS constituting inverter 6. The gate electrode 41 is opposed to the channel region with the insulating film 20 interposed therebetween. On the other hand, the exposed surface of n ^{− type} semiconductor layer 22 sandwiched between p ⁺ region 27 and p ⁺ region 44 functions as a channel region of a P channel MOS transistor which is another part of the CMOS constituting inverter 6. The gate electrode 40 faces the channel region with the insulating film 20 interposed therebetween.

A drain electrode 61 of an N channel MOS transistor is connected to the n ⁺ region 45, and a terminal to which a negative potential output VS1 is applied to both the p ⁺ region 48 and the n ⁺ region 47 through the source electrode of the N channel MOS transistor. Is connected. A drain electrode 60 of a P channel MOS transistor is connected to the p ⁺ region 27, and a terminal to which a positive potential output VB1 is applied to both the p ⁺ region 44 and the n ⁺ region 43 through the source electrode of the P channel MOS transistor. Is connected. The drain electrodes 61 and 60 are connected to each other.

  The drain electrode 30, the gate electrode 41, and the gate electrode 40 are connected to each other, and are also connected to a terminal to which the positive potential output VB1 is applied through the level shift resistor 4. The source electrode 28 is given a ground potential COM. The level shift resistor 4 is composed of, for example, an aluminum wiring (not shown) formed on the high voltage circuit part formation region HVa.

Further, n ^- the type semiconductor layer 22, n ^- from the surface in the form semiconductor layer 22 n ^- p ⁺ -type contact region 26 reaching the p-type semiconductor layer 21 through the type semiconductor layer 22 is formed . In the p ^{+ -type} contact region 26, a p ⁺ region 52 is selectively formed on the upper main surface of the n ⁻ -type semiconductor layer 22. The p ⁺ region 52 contact plug 80a is connected, the contact plug 80a, the p ⁺ region 52 through the conductive wire LNa and pad PD is given the ground potential COM. Since the p ⁺ region 52 is connected to the p ⁺ contact region 26 that reaches the p type semiconductor layer 21, the ground potential COM is applied to the p type semiconductor layer 21. The same applies to the other contact plugs 80b to 80h, and p ^{+ -type} contact regions similar to the p ^{+ -type} contact region 26 are provided under the contact plugs 80b to 80h, respectively.

The resistance R1 between the portion of the p-type semiconductor layer 21 where the p ^{+ -type} contact region 26 reaches and the portion covered with the HNMOS transistor 2 functions as the body resistance R1 of the HNMOS transistor 2 shown in FIG. To do.

  4 shows the structure of the HNMOS transistor 2, the level shift resistor 4, the inverter 6, and the body resistor R1, the HNMOS transistor 3, the level shift resistor 5, the inverter 7, and the body resistor R2 are also shown. A similar structure is adopted.

  According to the high potential side switching device driving device HD and the power conversion device 100 equipped with the driving device according to the embodiment of the present invention, body resistances R1 and R2 are provided between the HNMOS transistors 2 and 3 and the ground potential COM. Has been inserted.

  Therefore, the voltage between the ground potential COM and the positive potential output VB1 can be divided by the body resistors R1 and R2 and the level shift resistors 4 and 5, respectively. As a result, even if a reverse recovery current flows through the body-drain parasitic diodes of the HNMOS transistors 2 and 3 and a voltage drop occurs in the level shift resistors 4 and 5, voltage fluctuations at the input terminals of the inverters 6 and 7 are reduced. Can be suppressed.

This will be described with reference to FIG. When the negative potential output VS1 becomes negative, the body-drain parasitic diode D20 at the pn junction surface between the p-type semiconductor layer 21 and the n ⁻ -type semiconductor layer 22 is connected to the drain electrode 30 via the n ⁺ region 25. Also causes a parasitic current I10b to flow.

  The parasitic current I10b flowing through the body-drain parasitic diode D20 and the current I10a flowing through the parasitic diode D10 between the source and drain are combined to form a current I10, and the positive potential output VB1 is output via the level shift resistor 4. A current I10d is reached at a given terminal. In this case, a voltage drop occurs in the level shift resistor 4, and in the circuit diagram of FIG. 2, the potentials at the input terminals VR1 and VR2 of the inverter circuits 6 and 7 are relatively increased as compared with the previous state.

The value of the parasitic current I10b flowing through the body-drain parasitic diode D20 is larger than the value of the current I10a flowing through the parasitic diode D10. The pn junction surface between the p-type semiconductor layer 21 and the n ^{− -type} semiconductor layer 22 is wider than the pn junction surface between the p ⁺ region 24 and the n ^{− -type} semiconductor layer 22, and the amount of current flowing in the former is greater. Because it is big.

  In this case, the potential at the input terminals VR1 and VR2 only rises and does not fall, so that “H” does not appear at the output terminals of the inverter circuits 6 and 7. Therefore, there is no problem of malfunction of the set / reset flip-flop circuit 10.

  On the other hand, when the negative potential output VS1 returns from negative to 0, the parasitic diodes D10 and D20 are temporarily biased in the opposite direction, and the reverse recovery current flows to the parasitic diodes D10 and D20. . In this case, a voltage drop in the direction opposite to that in the level shift resistor 4 temporarily occurs in the level shift resistor 4, and the potential is relatively lowered at the input terminals VR 1 and VR 2 of the inverter circuits 6 and 7.

  Also in this case, the value of the parasitic current I10b flowing through the body-drain parasitic diode D20 is larger than the value of the current I10a flowing through the parasitic diode D10. Therefore, the parasitic current I10b has a larger contribution to the reverse voltage drop in the level shift resistor 4.

  Here, if the potential at the input terminals VR1 and VR2 falls below the “L” threshold value of the inverter circuits 6 and 7, “H” appears at the output terminals of the inverter circuits 6 and 7. However, in the present invention, the voltage between the ground potential COM and the positive potential output VB1 is divided by the body resistors R1 and R2 and the level shift resistors 4 and 5, respectively. As a result, even when a reverse recovery current flows through the body-drain parasitic diodes of the HNMOS transistors 2 and 3 and a voltage drop occurs in the level shift resistors 4 and 5, the body resistors R1 and R2 exist. The voltage drop at the input terminals of the inverters 6 and 7 hardly occurs. That is, voltage fluctuations at the input terminals of the inverters 6 and 7 can be suppressed.

  Therefore, even when a reverse recovery current flows through the body-drain parasitic diode D20 of the HNMOS transistors 2 and 3 and a voltage drop occurs in the level shift resistors 4 and 5, the output terminals of the inverter circuits 6 and 7 are not connected. “H” hardly appears. As a result, it is possible to obtain the high potential side switching device driving device HD and the power conversion device 100 that are unlikely to cause a malfunction in the switching device 17.

Further, according to the present invention, the body resistances R1 and R2 are resistances from a portion of the p-type semiconductor layer 21 where the p ^{+ -type} contact region 26 reaches to a portion covered with the HNMOS transistors 2 and 3. . Therefore, a part of the p-type semiconductor layer 21 can be used for the body resistors R1 and R2, and it is not necessary to separately provide a resistor on the surface of the semiconductor substrate 19.

According to the present invention, the conductive wirings LNa to LNd are formed on the surface of the n ^{− type} semiconductor layer 22 so as to surround the formation region of the HNMOS transistors 2 and 3. The p ^{+ -type} contact region such as the p ^{+ -type} contact region 26 and the conductive wirings LNa to LNd are electrically connected by contact plugs 80a to 80h, and a ground potential COM is applied to the conductive wirings LNa to LNd. It is done. Therefore, the values of the body resistances R1 and R2 can be easily adjusted by appropriately setting the distance from the HNMOS transistors 2 and 3 to the conductive wirings LNa to LNd and the number of contact plugs 80a to 80h.

  For example, FIG. 3 shows paths P1 to P4 from the HNMOS transistor 2 to the contact plugs 80a to 80d. Among these, for example, the distance of the path P1 is defined by the distance L between the contact plug 80a and the source electrode 28 in FIG. Since the value of the resistor R1 can be adjusted by adjusting the distance L, the value of the resistor R1 can be freely set by adjusting the distances of the other paths P2 to P4 in the same manner. The same applies to the paths P5 to P8 from the HNMOS transistor 3 to the contact plugs 80e to 80h, and the value of the resistor R2 can be freely set.

  FIG. 5 is a top view similar to FIG. 3, but shows a case where the number of contact plugs is reduced. In this case, since the paths from the HNMOS transistors 2 and 3 to the respective contact plugs are reduced as compared with FIG. 3, the values of the resistors R1 and R2 can be set higher.

Further, as shown in FIG. 3, the formation region of the HNMOS transistor 2 and the formation region of the p ^{+ -type} contact region (that is, the region below the contact plugs 80a to 80d), the formation region of the HNMOS transistor 3 and the p ^{+ -type} contact region ( that the lower region) of the forming area contact plug 80e~80h, n ^- so as to be axisymmetrical to the symmetry axis AX1 of -type semiconductor layer 22 in the surface, n ^- are arranged in a plan view form the semiconductor layer 22 surface .

In this way, the distance between the portion of the p-type semiconductor layer 21 where the p ^{+ -type} contact region under the contact plugs 80a to 80h reaches and the portion covered with the respective HNMOS transistors 2 and 3 is defined as the HNMOS transistor 2. , 3 can be made equal to each other between the two circuit portions, and the body resistances R1 and R2 can be made equal between the two circuit portions.

  Therefore, when the above two circuit units are used as an on signal level shift circuit and an off signal level shift circuit, respectively, the potential drop on one side of the inverter input terminals VR1 and VR2 is remarkable between the two circuits. It is difficult to cause a situation where the potential drop on the other side is not so much. Therefore, even if they are in phase, pulses having different intensities are not output from the inverters 6 and 7. Therefore, if the protection circuit DV1 capable of removing the in-phase signal is provided in the subsequent stage of the inverters 6 and 7, the switching device 17 does not malfunction.

It is a circuit diagram showing a power converter concerning an embodiment of the invention. It is a circuit diagram which shows in detail the level shift circuit and protection circuit periphery in the power converter device which concerns on embodiment of this invention. It is a top view which shows a part of semiconductor substrate in which the high electric potential side switching device drive device was formed. FIG. 4 is a cross-sectional view taken along a cutting line IV-IV shown in FIG. 3. It is another top view which shows a part of semiconductor substrate in which the high potential side switching device drive device was formed.

Explanation of symbols

2,3 HNMOS transistor, 4,5 level shift resistor, 6,7 inverter, 17,18 switching device, 19 semiconductor substrate, 80a-80h contact plug, R1, R2 body resistance, LNa-LNd conductive wiring, HD high potential Side switching device driving device, 100 power conversion device.

Claims (5)

A driving device for driving a switching device,
A level shift circuit that level-shifts the potential of at least one signal and outputs it as at least one level-shifted signal,
In response to a change in potential of the at least one level-shifted signal, the switching device is in a conductive state or a non-conductive state,
The level shift circuit includes:
A level-shifting field effect transistor having a drain, a body, a gate to which the signal is applied, and a source to which a first potential is applied;
A level shift resistor having one end connected to the drain of the level shift field effect transistor and the other end to which a second potential is applied;
An input terminal connected to the one end of the level shift resistor, and an inverter having an output terminal, and outputting the level shifted signal from the output terminal;
A driving device including at least one circuit unit including one end to which the first potential is applied and a body resistor having the other end connected to the body of the level shift field effect transistor. The drive device according to claim 1,
a semiconductor substrate having a stacked structure of a p-type semiconductor layer and an n-type semiconductor layer;
The level shift field effect transistor is formed in the n-type semiconductor layer,
In the n-type semiconductor layer, a p-type contact region that penetrates the n-type semiconductor layer from the surface of the n-type semiconductor layer and reaches the p-type semiconductor layer is formed,
The driving device, wherein the body resistance is a resistance between a portion of the p-type semiconductor layer where the p-type contact region reaches and a portion covered with the level shift field effect transistor. The drive device according to claim 2,
Conductive wiring is formed on the surface of the n-type semiconductor layer so as to surround the formation region of the level-shifting field effect transistor,
The p-type contact region and the conductive wiring are electrically connected by a contact plug,
A driving device in which the first potential is applied to the conductive wiring. The drive device according to claim 2,
The at least one signal includes a first signal and a second signal;
The at least one level shifted signal includes a first level shifted signal and a second level shifted signal;
The level shift circuit includes two circuit portions,
One of the circuit units receives the first signal and outputs the first level-shifted signal, and the other circuit unit receives the second signal and receives the second level-shifted signal. Output
The region for forming the level-shifting field effect transistor and the region for forming the p-type contact region in the two circuit portions are symmetrical with respect to a predetermined symmetry axis in the surface of the n-type semiconductor layer. A driving device arranged in a plan view of the surface of the n-type semiconductor layer. A drive device according to claim 1;
A switching device driven by the driving device,
The said switching device is a power converter device which carries out switching control of whether electric power is given to load.

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