JP4218626B2 - Decoding device, decoding method and decoding program, playback system, playback device, playback method and playback program, and recording medium - Google Patents

Description

  The present invention relates to a decoding device, a decoding method and a decoding program, a reproduction system, a reproduction device, a reproduction method, and a decoding method capable of reproducing a video stream that has been inter-frame compressed in units of a plurality of frames at a speed equal to or less than 1 × The present invention relates to a reproduction program and a recording medium.

  A reproducing apparatus adapted to reproduce a digital video signal recorded on a recording medium is known. Since a digital video signal has an enormous data capacity, it is generally compressed and encoded by a predetermined method and recorded on a recording medium. In recent years, MPEG2 (Moving Picture Experts Group 2) system is known as a standard system for compression coding. In MPEG2, digital video signals are compressed and encoded using intra-frame compression using DCT (Discrete Cosine Transform) and interframe compression using predictive coding based on motion compensation, and data compression using variable-length codes. The rate is increasing.

  When inter-frame compression is performed, a video stream according to MPEG2 includes an I (Intra-coded) picture based on intra-frame compression, a P (Predictive-coded) picture that is a picture based on predictive coding, and B (Bi-directionally predictive coded). ) Picture. An I picture can be decoded only with its own information. On the other hand, the P picture requires a temporally previous image as a predicted image, and the B picture requires a temporally previous and subsequent image as a predicted image, and is not decoded alone.

  In order to enable random access, an I picture is periodically inserted to have a frame group structure having at least one I picture. This frame group structure is referred to as GOP (Group Of Picture). That is, the GOP is composed of at least one I picture and one or more P and B pictures. Processing for the video stream is performed in units of GOPs. For example, a video stream recorded on a recording medium is accessed in units of GOPs.

  There are two types of GOPs: a closed GOP having a closed structure that can be completely decoded within the GOP, and an open GOP that can use information of the previous GOP at the time of decoding. An open GOP can be decoded using more information than a closed GOP, so that high image quality can be obtained and is generally used. In the following, when “GOP” is simply described, this open GOP is indicated unless otherwise specified.

  Note that a GOP can be composed of only one I picture, which is referred to as a single GOP. Single GOP is advantageous when editing in units of frames. On the other hand, a GOP composed of a plurality of pictures is referred to as a long GOP. In the single GOP, the problem described later does not occur. Therefore, hereinafter, the GOP indicates a long GOP.

One GOP is composed of a total of 15 pictures, for example, one I picture, four P pictures, and 10 B pictures. As shown in FIG. 27A, the display order of the I, P, and B pictures in the GOP is “B ₀ B ₁ I ₂ B ₃ B ₄ P ₅ B ₆ B ₇ P ₈ B ₉ B ₁₀ P ₁₁ B is as ₁₂ B ₁₃ P ₁₄ ". The subscript indicates the display order.

In this example, the first two B ₀ pictures and B ₁ pictures are predicted and decoded using the last P ₁₄ picture in the previous GOP and the I ₂ picture in this GOP. It is. The first P ₅ picture in the GOP is a picture predicted from the I ₂ picture and decoded. The other P ₈ picture, P ₁₁ picture, and P ₁₄ picture are pictures predicted and decoded using the previous P picture, respectively. Each B picture after the I ₂ picture is a picture predicted and decoded from the preceding and following I and / or P pictures.

  On the other hand, because B pictures are predicted and decoded using temporally preceding and following I or P pictures, the order of arrangement of I, P, and B pictures on a stream or recording medium is the order of decoding in a decoder. It is necessary to decide in consideration. That is, an I and / or P picture for decoding a B picture must always be decoded before the B picture.

In the above-described example, the arrangement order of each picture on the stream or the recording medium is “I ₂ B ₀ B ₁ P ₅ B ₃ B ₄ P ₈ B ₆ B ₇ P ₁₁ B ₉ as illustrated in FIG. 27B. B ₁₀ P ₁₄ B ₁₂ B ₁₃ ”and are input to the decoder in this order. The subscripts correspond to FIG. 27A and indicate the display order.

As shown in FIG. 27C, the decoding process in the decoder is performed by first decoding the I ₂ picture and using the decoded I ₂ picture and the last P ₁₄ picture (display order) in the previous GOP. B ₀ picture and B ₁ picture are predicted and decoded. Then, the B ₀ picture and the B ₁ picture are output from the decoder in the decoded order, and then the I ₂ picture is output. Once the B ₁ picture is output, the P ₅ picture is then predicted and decoded using the I ₂ picture. Then, the B ₃ picture and the B ₄ picture are predicted and decoded using the I ₂ picture and the P ₅ picture. Then, the decoded B ₃ picture and B ₄ picture are output from the decoder in the order of decoding, and then the P ₅ picture is output.

Similarly, the P or I picture used for prediction of the B picture is decoded before the B picture, and the B picture is predicted and decoded using the decoded P or I picture. After outputting the B picture, the process of outputting the P or I picture used to decode the B picture is repeated. The picture arrangement as shown in FIG. 27B is generally used because the frame memory required for decoding is sufficient for four frames. Non-Patent Document 1 describes a method of decoding an MPEG2 elementary stream in this way.
Hiroshi Fujiwara, “Point Illustration / Latest MPEG Textbook”, first edition, ASCII, Inc., August 1, 1994, p. 106

  By the way, in recent years, with the improvement of the processing capability of a computer device such as a personal computer, an example in which a computer device is used to reproduce and edit a video stream compressed and encoded by the MPEG2 system is increasing. FIG. 28 schematically shows a configuration of an example computer apparatus 100 for decoding a video stream compression-encoded using the MPEG2 system or the like. A CPU (Central Processing Unit) 111, a memory 112, and a hard disk drive 113 are connected to the bus 110. The memory 112 is a memory used as a work memory for the CPU 111. The MPEG2 video stream before decoding is stored in the hard disk drive 113 in a picture arrangement as shown in FIG. 27B. Further, a decoder 114 and a buffer memory 116 are connected to the bus 110. The decoder 114 has a frame memory 115 for decoding processing.

  In such a configuration, the CPU 111 reads a video stream from the hard disk drive 113 and supplies the read video stream to the decoder 114 via the bus 110 while using the buffer memory 116 as necessary. The decoder 114 writes and decodes the I picture and P picture of the supplied stream in the frame memory 115 according to the order described with reference to FIG. 27C, and performs prediction using the I picture and / or P picture on the frame memory 115. When the B picture to be input is input, the input B picture data is decoded using the data in the frame memory 115 and output.

  When decoding a video stream by a computer device, if the processing speed of the CPU 111 is sufficiently high, it is possible to perform all the processing inside the CPU 111 without providing the decoder 114. However, when decoding higher-resolution video data, real-time performance may not be satisfied. Therefore, it is necessary to separately provide a decoder 114 as hardware as shown in FIG. For example, an expansion unit including the decoder 114 is mounted on the computer device 100.

  Here, consider a case where the above-described MPEG2 video stream is subjected to slow playback such as playback at 1/2 times the original playback speed or 1/3 speed. The conventional decoder 114 is configured such that when the input of the video stream is stopped, the frame immediately before the input is stopped is repeatedly output, and the output freezes. For example, when the input is stopped, the freeze is realized by repeatedly reading and outputting the data in the frame memory 115 at the frame timing.

When this slow playback is performed from the start of playback of the video stream, conventionally, input and decoding are performed at a slow playback speed from the picture that is first input to the decoder 114 as playback starts. This will be described with reference to FIG. In the case of an MPEG2 elementary stream, the video stream starts to be input to the decoder 114 from an I ₂ picture. In FIG. 29, the diagonal lines attached to the squares indicating pictures are for distinguishing GOPs.

In the case of performing ½-speed slow playback, conventionally, as shown in FIG. 29, the input to the decoder 114 is stopped during the next one-frame synchronization signal period in which the I ₂ picture is input, and the next The next picture (B ₀ picture) is input during the frame synchronization signal period. Thereafter, the input and stop of the picture are repeated for each frame synchronization signal, thereby realizing a 1/2 × speed slow reproduction.

That is, the decoder 114 decodes the first input I ₂ picture prior to output and writes it in the frame memory 115. Next, the input to the decoder 114 is stopped for one frame synchronization signal period in accordance with the half-speed slow playback sequence, and the next B ₀ picture is input at the timing of the next frame synchronization signal. Further, input to the decoder 114 is stopped during the next one frame synchronization signal period, and further next B ₁ picture is input at the timing of the next frame synchronization signal.

Note that the B ₀ picture and the B ₁ picture are not decoded because there is no P ₁₄ picture of the previous GOP.

Next, when a P ₅ picture is input, the P ₅ picture is decoded using the I ₂ picture that has already been decoded and written in the frame memory 115, and the I ₂ picture in the frame memory 115 is one frame. Output during the synchronization signal period. In the next one-frame synchronization signal period, the input is stopped, the I ₂ picture in the frame memory 115 is repeatedly read, and the output is frozen.

  As described above, conventionally, since slow playback is performed according to the speed of slow playback from the beginning of picture input and decoding, it takes time according to the slow playback speed until the first output picture is obtained. In other words, for example, there is a problem that the responsiveness until an actual image is output after an instruction to start slow playback is made by a user's operation on the playback device is poor.

  The example of FIG. 29 is an example of 1 / 2-speed slow reproduction, and a delay of 6 frames occurs from the start of I picture input and decoding to picture output. This delay becomes longer in accordance with the slow playback speed. For example, in the case of 1 / 5-speed slow playback, 15 frames from the start of I picture input and decoding to picture output, that is, 30 frames / second. Has a problem that it takes as much as 0.5 seconds and the response is very poor.

  Accordingly, an object of the present invention is to provide a decoding device, a decoding method and a decoding program, a playback system, a playback device, a playback method and a playback program, and a recording medium that can start slow playback with good responsiveness. It is to provide.

  In order to solve the above-described problems, the present invention provides a decoding device for decoding and outputting compressed and encoded video data, and decoding means for decoding and outputting input video data, and decoding means Video data input and control means for controlling the decoding of the input video data based on a predetermined sequence, and the control means decodes when a playback speed less than 1 × is instructed. Control is performed so that the input to the decoding means of the preceding frame input before the timing of the first frame output from the means and the decoding by the decoding means of the preceding frame are performed based on the sequence of the 1 × speed reproduction. The decoding device is characterized in that it is configured as described above.

  According to another aspect of the present invention, there is provided a decoding method for decoding and outputting compressed and encoded video data, and having a decoding step of decoding and outputting input video data, and a reproduction speed less than 1 × speed When instructed, the input to the decoding step of the preceding frame input before the timing of the first output frame from the decoding step, and the decoding by the decoding step of the preceding frame, The decoding method is characterized in that control is performed based on a sequence of 1 × speed reproduction.

  According to another aspect of the present invention, there is provided a decoding program for causing a computer apparatus to execute a decoding method for decoding and outputting compression-encoded video data. The decoding method decodes input video data and outputs the decoded data. And an input to a preceding frame decoding step that is input before the timing of the first output frame from the decoding step when a playback speed less than 1 × speed is indicated. The decoding program is characterized in that the decoding by the step of decoding the preceding frame is controlled based on the sequence of the 1 × speed reproduction.

  According to another aspect of the present invention, there is provided a recording medium readable by a computer device on which a decoding program for causing a computer device to execute a decoding method for decoding and outputting compression-encoded video data is output. A decoding step for decoding and outputting input video data is provided, and when a playback speed of less than 1 × speed is designated, it is input before the timing of the first output frame from the decoding step. The computer apparatus is characterized in that control is performed so that the input to the decoding step of the preceding frame and the decoding by the decoding step of the preceding frame are performed based on the sequence of the 1 × speed reproduction. Recording medium.

  The present invention also relates to a recording device for recording compressed and encoded video data and a playback speed of the video data in a playback device that decodes and outputs the video data that has been compressed and recorded on the recording medium. Speed information output means for outputting speed information and decoding means for decoding and outputting video data read from the recording medium, and reproduction at a speed less than 1 × speed by the speed information output from the speed information output means When the speed is instructed, the input to the decoding unit of the preceding frame input before the timing of the first frame output from the decoding unit and the decoding by the decoding unit of the preceding frame are 1 A playback apparatus characterized in that control is performed based on a double-speed playback sequence.

  According to another aspect of the present invention, there is provided a playback method for decoding and outputting video data recorded on a recording medium after being compressed and encoded, a speed information output step for outputting speed information indicating the playback speed of the video data, and compression encoding A decoding step of decoding and outputting the video data read from the recording medium on which the recorded video data is recorded, and reproduction at a speed less than 1 × speed by the speed information output from the speed information output step When the speed is instructed, the input to the decoding step of the preceding frame that is input before the timing of the first output frame from the decoding step, and the decoding by the decoding step of the preceding frame; Is a reproduction method characterized in that control is performed based on a 1 × speed reproduction sequence.

  According to another aspect of the present invention, there is provided a playback program for causing a computer apparatus to execute a playback method for decoding and outputting video data compressed and encoded and recorded on a recording medium. The playback method includes speed information indicating a playback speed of video data. A speed information output step for outputting, and a decoding step for decoding and outputting the video data read from the recording medium on which the compression-encoded video data is recorded, from the speed information output step When a playback speed less than 1 × speed is instructed by the output speed information, an input to the decoding step of the preceding frame input before the timing of the first output frame from the decoding step; In addition, it is controlled so that the decoding by the decoding step of the preceding frame is performed based on the sequence of the 1 × speed reproduction. A reproduction program characterized and.

  The present invention also relates to a playback method in a recording medium readable by a computer device on which a playback program for causing a computer device to execute a playback method for decoding and outputting video data that has been compression-encoded and recorded on a recording medium. Is a speed information output step for outputting speed information indicating the playback speed of the video data, and a decoding process for decoding and outputting the video data read from the recording medium on which the compressed and encoded video data is recorded. And when the playback speed less than 1 × is instructed by the speed information output from the speed information output step, it is input before the timing of the first output frame from the decoding step. The input to the preceding frame decoding step and the decoding by the preceding frame decoding step are 1 × speed. A computer-readable recording medium apparatus being characterized in that so as to control to perform based on the raw sequence.

  The present invention also relates to a recording system on which compression-encoded video data is recorded and a speed indicating the playback speed of the video data in a playback system that decodes and outputs video data recorded on the recording medium after being compressed and encoded. Control apparatus having speed information output means for outputting information, decoding means for decoding and outputting video data read from the recording medium, and speed information output from the speed information output means, less than 1 × speed When the playback speed is instructed, the input to the decoding means of the preceding frame input before the timing of the first frame output from the decoding means and the decoding by the decoding means of the preceding frame are performed. A decoding system comprising: a decoding device having control means for performing control based on a 1 × speed reproduction sequence.

  According to another aspect of the present invention, there is provided a reproduction method for decoding and outputting video data that has been compression-encoded and recorded on a recording medium. The video data that has been compression-encoded is input and the input video data is decoded and output. Decoding means for decoding a preceding frame input before the timing of the first frame output from the decoding means when a playback speed of less than 1 × speed is indicated by the input speed information Compression-encoded video data is recorded on a decoding device that controls the input to the means and the decoding of the preceding frame by the decoding means based on the sequence of the 1 × speed reproduction. In addition to reading and supplying video data from a recording medium, speed information indicating the playback speed of the video data is supplied. That.

  According to another aspect of the present invention, there is provided a playback program for causing a computer apparatus to execute a playback method of decoding and outputting video data recorded on a recording medium after being compressed and encoded. , Having a decoding means for decoding and outputting the input video data, and when the reproduction speed less than 1 × speed is instructed by the input speed information, the first output frame from the decoding means For a decoding apparatus that controls to input the preceding frame input before the timing to the decoding means and to decode the preceding frame by the decoding means based on the sequence of the 1 × speed reproduction In addition, the video data is read out and supplied from the recording medium on which the compressed and encoded video data is recorded, and the playback speed of the video data is indicated. A reproduction program which is characterized in that so as to provide the speed information.

  The present invention also relates to a playback method in a recording medium readable by a computer device on which a playback program for causing a computer device to execute a playback method for decoding and outputting video data that has been compression-encoded and recorded on a recording medium. Has a decoding means for decoding and outputting the input video data when the compressed and encoded video data is input, and when the playback speed less than 1 × is instructed by the input speed information The input of the preceding frame input before the timing of the first frame output from the decoding unit to the decoding unit and the decoding of the preceding frame by the decoding unit are performed based on the sequence of the 1 × speed reproduction. Video data from a recording medium on which compression-encoded video data is recorded to a decoding device controlled in such a manner. Supplies out look is a recording medium computing device readable, characterized in that it has to supply a velocity information indicating the playback speed of the video data.

  As described above, according to the first, eleventh, twelfth and thirteenth aspects of the present invention, when a playback speed less than 1 × speed is instructed, the timing of the first output frame after decoding the input video data Since the input of the preceding frame input earlier and the decoding of the preceding frame are controlled based on the sequence of the 1 × speed playback, even if the slow playback is performed from the start of the playback, The latency from the playback start instruction to frame output is reduced, the response to start slow playback is improved, and the latency is constant regardless of the slow playback speed.

  According to the invention described in claims 14, 24, 25 and 26, when the speed information indicating the playback speed of the video data is output, and the playback speed of less than 1 times is instructed by this speed information, the recording medium Control is performed so that the input of the preceding frame input before the timing of the first output frame after decoding the video data read from the video data and the decoding of the preceding frame are performed based on the sequence of the 1 × speed playback. Therefore, based on the output speed information, even when performing slow playback of video data read from the recording medium from the start of playback, the latency from the slow playback start instruction to frame output is reduced, The responsiveness at the start of slow playback is improved and the latency is constant regardless of the slow playback speed.

  The invention described in claims 27, 37, 38, and 39 has decoding means for receiving compressed video data, decoding the input video data, and outputting the decoded video data. When a reproduction speed less than 1 × speed is instructed by the information, the input to the decoding means of the preceding frame input before the timing of the first output frame from the decoding means, and the decoding of the preceding frame In contrast to a decoding device that is controlled to perform decoding by means based on a 1 × speed playback sequence, the control device receives video data from a recording medium on which compression-encoded video data is recorded. Since the read information is supplied and the speed information indicating the playback speed of the video data is supplied, the control device side stores the video data recorded on the recording medium, Even when the video data read from the recording medium is slow-played from the start of playback only by supplying speed information indicating the playback speed of the video data to the decoding device, the latency from the slow-play start instruction to frame output is reduced. As a result, the response to start slow playback is improved, and the latency is constant regardless of the slow playback speed.

  In the present invention, a frame that is input to and decoded from a decoder immediately after the start of reproduction but that is not output is input to the decoder in advance and decoded and written to the frame memory. Are input at the normal 1 × speed input timing. Therefore, even when performing slow playback from the start of playback, there is an effect that latency from the slow playback start instruction to frame output is reduced, and responsiveness at the start of slow playback is improved.

  Also, since the input to the decoder and the decoding are performed immediately after the start of the reproduction but the output is not performed, the input to the decoder and the decoding timing are limited to the normal 1 × speed, so the slow reproduction is performed. There is an effect that the latency is constant regardless of the speed.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 schematically shows the structure of an example of a playback apparatus applicable to the first embodiment of the present invention. This playback device is configured as a playback system including a computer device 1 and a decoder board 2 that is connected to the computer device 1 and provides the computer device 1 with a video stream decoding function and playback control function in hardware. The

  In the following description, it is assumed that the computer apparatus 1 is a personal computer and the decoder board 2 is a PCI board that is loaded in a slot of the personal computer and used by connecting to a PCI component (Peripheral Component Interconnect Bus). This is not limited to this example, and the playback device may be a dedicated playback device designed and manufactured for playing back a video stream, or a recording / playback device for recording and playing back a video stream It may be. Further, it may be incorporated into a device designed and manufactured for other purposes.

  In the computer apparatus 1, the north bridge 10 and the south bridge 13 are connected to each other. The north bridge 10 is connected to, for example, a CPU (Central Processing Unit) 11, a memory 12, and a graphic circuit (not shown), and controls high-speed data transfer performed between the CPU 11, the memory 12, and the graphic circuit.

  The south bridge 13 controls data transfer at a lower speed than the north bridge 10, and mainly controls the interface. For example, the south bridge 13 has an interface to a hard disk drive, and the hard disk drive 14 is connected to the south bridge 13. Also, it has an interface for a drive device that can read, for example, a CD (Compact Disc) and a DVD (Digital Versatile Disc). Further, the south bridge 13 has an interface to the PCI bus, and the PCI bus 15 is connected thereto. The PCI bus 15 has one or more connectors to which a PCI board can be connected.

  The hard disk drive 14 stores a video stream reproduced by the reproducing apparatus. The video stream stored in the hard disk drive 14 is read by the CPU 11 and transferred to the PCI bus 15 based on the control of the south bridge 13. In this embodiment, access to the video stream stored in the hard disk drive 14 is performed in units of a plurality of predetermined frames. For example, if the video stream is an MPEG2 elementary stream, access to the video stream stored in the hard disk drive 14 is performed in units of GOPs.

  The hard disk drive 14 also stores program data and the like for operating the CPU 11. The program data is provided by being recorded on a recording medium such as a CD-ROM (Compact Disc-Read Only Memory) or a DVD-ROM (Digital Versatile Disc-Read Only Memory). A recording medium on which the program data is recorded is loaded in a predetermined drive device (not shown) of the computer apparatus 1 to reproduce the recording medium, read out the program data, and is installed in the hard disk drive 14 in a predetermined manner. The program data read from the hard disk drive 14 is expanded on the memory 12, for example, and read and executed by the CPU 11. The program data and the video stream are preferably stored in separate hard disk drives from the viewpoint of accessibility.

  In the decoder board 2, the PCI bridge 20, the decoding unit 30 and the CPU 25 are connected to the control bus 22. The PCI bridge 20 is an interface to the PCI bus 15 of the computer apparatus 1. That is, the decoder board 2 is attached to a connector provided on the PCI bus 15 of the computer apparatus 1 and is used by electrically connecting the PCI bus 15 and the PCI bridge 20. The PCI bridge 20 controls the exchange of data with the PCI bus 15 using the memory 21 as a buffer.

  For example, commands and various data from the CPU 11 are supplied to the PCI bridge 20 via the PCI bus 15. The PCI bridge 20 supplies the supplied command and various data from the CPU 11 to the CPU 25 via the control bus 22. For example, the video stream read from the hard disk drive 14 is supplied to the PCI bridge 20 via the PCI bus 15. The PCI bridge 20 temporarily stores the supplied video stream in the memory 21 and then supplies it to the decoding unit 30.

  The decoding unit 40 generally includes a decoder 23 and a frame memory 24. The decoder 23 decodes the supplied video stream and writes it into the frame memory 24 in units of frames. The data written in the frame memory is read out in a predetermined manner and output as output video data.

  The CPU 25 uses the memory 26 as a work memory, controls each part of the decoder board 2 while exchanging various instructions and data with the CPU 11, and controls the decoding process in the decoder board 2. The processing on the video data in the decoder board 2 is performed with timing control based on a frame synchronization signal generated by a clock generation circuit (not shown) and synchronized with the video frame period.

  In the configuration as described above, the CPU 11 reads a video stream from the hard disk drive 14 in units of a predetermined plurality of frames, and exchanges commands and various data between the CPU 11 and the CPU 25 via the PCI bus 15. . Based on this exchange, the video stream read from the hard disk drive 14 is supplied to the PCI bridge 20 via the south bridge 13 and the PCI bus 15 and temporarily stored in the memory 21.

  Based on the instruction from the CPU 11, the CPU 25 instructs the PCI bridge 20 to read the video stream stored in the memory 21 in units of frames and supply it to the decoder 23. The video streams stored in the memory 21 are read out by being rearranged in units of frames in an order different from the supplied order in accordance with, for example, an instruction from the CPU 25 based on a playback direction instruction from the CPU 11. Further, the read timing is controlled in accordance with a command from the CPU 25 based on the speed information instructing the reproduction speed from the CPU 11.

  The decoder 23 decodes the video data in units of frames supplied from the memory 21 in accordance with a decoding start command supplied from the CPU 25 and writes it into the frame memory 24. The video data written in the frame memory 24 is read according to a display start command supplied from the CPU 25 and output as output video data.

  FIG. 2 shows an exemplary configuration of the decoder 23. The decode circuit 30 and the output address determination circuit 31 are connected to the CPU 25 via the control bus 22, respectively, and based on an instruction from the CPU 25, the video stream is decoded and the video data decoded and written in the frame memory 24. Is read out. The memory controller 32 controls access to the frame memory 24.

  The video data supplied to the decoder 23 is decoded by the decoding circuit 30, is address-controlled by the memory controller 32 based on an instruction from the CPU 25, and is written in the frame memory 24. Further, the decoding circuit 30 performs decoding of the supplied video data based on an instruction from the CPU 25 using the video data on the frame memory 24 as necessary, and the decoded video data is stored in the frame memory. 24.

  On the other hand, the CPU 25 supplies a display start instruction for instructing a frame to be output at the next timing to the output address determination circuit 31 via the control bus 22. The display start command is written in, for example, a register included in the output address determination circuit 31 and is updated by a display start command supplied next. In other words, the display start command is held until a new display start command is supplied. The output address determination circuit 31 obtains the address of the frame to be read from the frame memory 24 according to this display start command, and reads the video data from the frame memory 24 in units of frames via the memory controller 32 based on this address. The video data read from the frame memory 24 is output as output video data.

  Next, a slow playback control method according to an embodiment of the present invention will be described. First, in order to facilitate understanding, a video stream applicable to the present invention and playback control at the time of 1 × playback of the video stream will be schematically described.

In the embodiment of the present invention, the MPEG2 system already described in the background section is applied as the video data encoding system. One GOP consists of 15 frames, and the display order of I, P and B pictures is “B ₀ B ₁ I ₂ B ₃ B ₄ P ₅ B ₆ B ₇ P ₈ B ₉ B ₁₀ P ₁₁ B ₁₂ B ₁₃ P ₁₄ ”, and the arrangement of I, P, and B pictures in a video stream (hereinafter referred to as an elementary stream (ES)) is“ I ₂ B ₀ B ₁ P ₅ B ₃ B ₄ P ₈ B ₆ B ₇ and _{P 11 B 9 B 10 P 14} B 12 that B ₁₃ "is.

In this embodiment, this picture array of elementary streams read from the hard disk drive 14 and input to the decoder board 2 is as shown in the following array (1) when forward (forward) playback is performed. Are input to the decoder 23.
I ₂ P ₅ P ₈ P ₁₁ P ₁₄ B ₀ B ₁ B ₃ B ₄ B ₆ B ₇ B ₉ B ₁₀ B ₁₂ B ₁₃ (1)
In reverse (reverse direction) reproduction, data is rearranged as shown in the following array (2) and input to the decoder 23. In the case of reverse playback, the B ₁ picture and the B ₀ picture are pictures of the previous GOP in the coding order.
I ₂ P ₅ P ₈ P ₁₁ P ₁₄ (B ₁ ) (B ₀ ) B ₁₃ B ₁₂ B ₁₀ B ₉ B ₇ B ₆ B ₄ B ₃ (2)
By rearranging in this way, reverse playback of the MPEG2 video stream can be easily performed, and forward playback can be performed by the same processing as reverse playback.

  Data rearrangement is performed using the memory 21 of the decoder board 2. That is, the CPU 11 reads one or a plurality of GOP elementary streams from the hard disk drive 14 and transfers them to the decoder board 2 via the PCI bus 15. The one or more GOP elementary streams are input to the PCI bridge 20 and stored in the memory 21 in the decoder board 2. Note that the memory 21 has a capacity of at least 4 GOP.

  The CPU 25 knows the head of the GOP, the boundary of each frame (picture), and the picture type (I, P, and B) of each picture for the elementary stream in which a plurality of GOPs are stored in the memory 21. Based on this information, data can be read from the memory 21 in any picture order.

  For example, the CPU 11 searches for the GOP header in the elementary stream stored in the hard disk drive 14, reads the elementary stream from the hard disk drive 14 in units of GOP based on the search result, and stores the elementary stream in the memory 21 of the decoder board 2. Specify and write the address where the GOP head is written. The address information on the memory 21 at the head of the GOP is transmitted from the CPU 11 to the CPU 25. Based on this address information, the CPU 25 accesses the head of the GOP of the elementary stream written on the memory 21, and searches each picture head in the GOP to obtain the picture boundary and the picture type of each picture. .

  The reproduction control of forward reproduction at the time of 1 × speed reproduction will be described using FIG. 3 and FIG. FIG. 3 shows a schematic sequence of input / output and internal processing in the decoder 23. The sequence shown as an example in FIG. 3 is scheduled in advance by the CPU 25 at the start of decoding of the elementary stream.

  In FIG. 3, “ES input” indicates the picture order of the elementary stream input to the decoder 23. The elementary streams are input to the decoder 23 in the picture order according to the arrangement (1) described above. In the decoding circuit 30, the picture input in accordance with the decoding start instruction from the CPU 25 is decoded and written in the frame memory 24 in the picture order as shown in “decoding”. In the example of FIG. 3, the decoded picture is written in the frame memory 24 with a delay of one frame synchronization signal with respect to the ES input. Pictures written in the frame memory 24 can be output. A display start command is transmitted from the CPU 25 in the picture order indicated by the “display command”. In accordance with this display start command, pictures are read out from the frame memory 24 in the picture order shown in “output” in synchronization with the frame synchronization signal and output. In the example of FIG. 3, the output is delayed by one frame synchronization signal with respect to the display start command. “Video output” indicates a stream output from the decoder board 2 to the outside.

  Note that the meanings of “ES input”, “decode”, “display command”, “output”, “video output”, and the like in FIG.

  FIG. 4 shows an example of the usage status of the frame memory 24 based on the sequence shown in FIG. 3, assuming that decoding starts from the beginning of GOP # 1. In FIG. 4, the vertical axis corresponds to “decode” in FIG. 3, and pictures written to the frame memory 24 are shown in time series in units of frame synchronization signals. The horizontal axis indicates the picture to be output. The output picture is output as indicated by “● (black circle)” in FIG. 4 in time series. In FIG. 4, “◎ (double circle)” indicates a picture written in the frame memory 24 at the horizontal axis timing, and “◯ (circle)” is already written at the horizontal axis timing. Indicates a picture. That is, the horizontal axis in FIG. 4 indicates a picture written in the frame memory 24 at that timing.

First, the I ₂ picture is decoded and written in the frame memory 24, and subsequently, the P ₅ picture, the P ₈ picture, the P ₁₁ picture, and the P ₁₄ picture are respectively preceded by one as indicated by arrows in the figure. Are decoded using the I or P picture that has been decoded and written into the frame memory 24, respectively. Next, the B ₀ picture and the B ₁ picture are decoded using the P ₁₄ picture of the previous GOP and the I ₂ picture of this GOP # 1. In the example of FIG. 4, since decoding is started from GOP # 1, it is not necessary to decode the B ₀ picture and the B ₁ picture.

Subsequently, the B ₃ picture and the B ₄ picture, the B ₆ picture and the B ₇ picture, the B ₉ picture and the B ₁₀ picture, and the B ₁₂ picture and the B ₁₃ picture are sequentially shown by arrows in the figure, respectively. These pictures are decoded using the preceding and succeeding I or P pictures in the display order of the pictures, and are held in the frame memory 24 until they are displayed by the display start command.

  As described above, in this embodiment, the I picture and the P picture are decoded before all the B pictures in the GOP and are held in the frame memory 24 until their output is performed. Such a picture held in the frame memory 24 for reference from other pictures is referred to as an anchor picture. For example, an I picture and four P pictures are anchor pictures.

In FIG. 4, the processing from the I ₂ picture of GOP # 1 to the B ₁₃ picture is repeated after the I ₂ picture of GOP # 2 in the time series direction, and thus detailed description thereof is omitted.

  The number of frames occupied by the frame memory 24 at each timing is shown at the right end of FIG. Note that the number of occupied frames after GOP # 2 on the time series is shown as the processing of the corresponding part of GOP # 1 being repeated. Thus, in forward reproduction, the number of occupied frames does not exceed 7 frames. At the time of forward reproduction, each picture written in the frame memory 24 can be released when output according to the display start command. A new picture can be overwritten in the released area.

  Reproduction control of reverse reproduction at the time of 1 × speed reproduction will be described with reference to FIGS. FIG. 5 is a diagram corresponding to FIG. 3 described above, and shows a schematic sequence of input / output and internal processing at the time of reverse reproduction in the decoder 23. The sequence shown in FIG. 5 is also scheduled in advance by the CPU 25 at the start of decoding of the elementary stream, as described above.

  In FIG. 5, the elementary stream is input to the decoder 23 in the picture order according to the above-described arrangement (2), as indicated by “ES input”. In the decoder circuit 30, the input picture is decoded in accordance with a decoding start instruction from the CPU 25 and written in the frame memory 24 in the picture order as shown in “decode”. In the example of FIG. 5, the picture is decoded and written in the frame memory 24 with a delay of one frame synchronization signal with respect to the ES input. Pictures written in the frame memory 24 can be output.

A display start command is transmitted from the CPU 25 in the picture order indicated by the “display command”. In the case of reverse reproduction, a display start command is transmitted so that the images are displayed in the display order from the P ₁₄ picture to the B ₀ picture, contrary to the above-described forward reproduction. In accordance with this display start command, pictures are read from the frame memory 24 in the picture order as shown in “output”, and output after being delayed by one frame synchronization signal with respect to the display start command.

  FIG. 6 shows the usage status of the frame memory 24 based on the sequence of FIG. 5 as that decoding is started from the head of GOP # 1. The meaning of each part in FIG. 6 is the same as that in FIG. 4 described above.

As in the case of forward playback, the processing of the I picture and the P picture is performed in the order of the I ₂ picture, the P ₅ picture, the P ₈ picture, the P ₁₁ picture, and the P ₁₄ picture. Each picture is decoded using a P picture and written in the frame memory 24.

In the case of reverse playback, as described above, the B ₁ picture and B ₀ picture that are decoded next to the P ₁₄ picture are pictures included in GOP # 0 that is one before in reverse playback input order. In the example of FIG. 6, decoding is started from GOP # 1, and decoding of B ₁ picture and B ₀ picture is omitted.

Subsequently, the B ₁₃ picture and the B ₁₂ picture, the B ₁₀ picture and the B ₉ picture, the B ₇ picture and the B ₆ picture, and the B ₄ picture and the B ₃ picture are sequentially shown as indicated by arrows in the figure, respectively. These pictures are decoded using the preceding and succeeding I or P pictures in the display order of the pictures, and are held in the frame memory 24 until they are displayed by the display start command. Even in the case of the reverse reproduction, as in the case of the forward reproduction described above, the I picture and the P picture are decoded before all the B pictures in the GOP and are stored in the frame memory 24 until their output is performed. Retained.

In FIG. 6, the processing from the I ₂ picture of GOP # 1 to the B ₃ picture is repeated after the I ₂ picture of GOP # 2 in the time series direction, and thus detailed description thereof is omitted.

The number of frames occupied by the frame memory 24 at each timing is shown at the right end of FIG. Note that the number of occupied frames after GOP # 2 on the time series is shown as the processing of the corresponding part of GOP # 1 being repeated. In the case of reverse playback, I ₂ picture is required when decoding the B ₀ picture, so that the number of occupied frames is 8 frames at the decoding timing of the B ₀ picture, unlike the case of the forward playback described above. It becomes. At other timings, the number of occupied frames does not exceed 7 frames. Therefore, in addition to the processing at the time of forward reproduction described above, by setting the capacity of the frame memory 24 to at least 8 frames, it is possible to cope with either forward reproduction or reverse reproduction.

At the time of reverse reproduction, the I ₂ picture on the frame memory 24 is not released until the decoding of the B ₀ picture is completed even after its output is completed. Pictures other than I ₂ pictures can be released when their own output is made.

  In either case of forward reproduction or reverse reproduction, control such as which picture is written in which area on the frame memory 24 is appropriately performed by the CPU 25 when scheduling a decoding sequence, for example. For example, if the format of the elementary stream supplied to the decoder board 2 is known in advance, the mapping of each picture to the frame memory 24 can be controlled using a predetermined table or algorithm.

  Thus, according to the playback control method applied to this embodiment, the picture order of the elementary stream is rearranged in a predetermined order on the memory 21 and supplied to the decoder 23. The reverse reproduction can be performed by substantially the same processing, and the necessary frame memory is sufficient for 8 frames.

  Next, slow reproduction control applicable to one embodiment of the present invention will be described. This slow reproduction control is performed by stopping both the input of video data (picture) to the decoder 23 and the display start command supplied from the CPU 25 to the decoder 23. Thereby, slow reproduction in the forward and reverse directions can be easily performed with good responsiveness.

  In addition, in the present invention, when performing slow playback from the start of playback, a picture to be decoded prior to output of the picture at the start of playback is input and decoded in advance at the same timing as in the case of 1 × playback. To do. This can improve the responsiveness when starting playback from slow playback, and the delay time from the start of slow playback until the actual output by slow playback is obtained does not depend on the playback speed of slow playback. Can be.

  Note that the slow reproduction can be realized by updating the output frame once every two or more frame synchronization signals. In other words, it can be said that the slow reproduction is an operation in which pause reproduction in which the same frame image is output in a fixed manner and step reproduction in which the frame is output one frame at a time according to a step command. For example, by repeating a combination of pause playback for one frame period and one step playback, 1 / 2-speed playback is achieved. Further, for example, when a combination of pause playback in a two-frame period and one step playback is repeated, 1/3 speed playback is performed. Hereinafter, the case of 1 / 2-speed playback will be described.

FIG. 7 shows an example sequence in the case of performing pause playback, step playback, and 1 / 2-speed slow playback during forward playback. The arrangement of the I, P, and B pictures in the ES input is the same arrangement (1) as in the example of FIG. First, pause reproduction will be described. For example, the user operates the playback device in expectation that pause playback is performed at a desired playback video position while watching the playback video based on the video data output at the video output. In the example of FIG. 7, the user issues a pause playback instruction at the timing of the I ₂ picture in the output data. Based on this instruction, a pause reproduction command 200 is transmitted from the CPU 11.

In FIG. 7, for the sake of explanation, it is assumed that an instruction for pause reproduction has been given in the vicinity of the middle of one frame synchronization signal period. Since the pause command 200 based on the pause playback instruction is issued in synchronization with the frame synchronization signal, the pause command 200 becomes effective from the timing of the frame synchronization signal immediately after the timing at which the command is transmitted. For example, if the pause command 200 at the timing of the I-picture as described above is transmitted, in fact, pose reproduction from the next frame period is started, B ₃ picture is fixedly movies out.

  The pause reproduction instruction by the user is received by the CPU 11. In response to this pause playback instruction, the CPU 11 transmits speed information indicating the playback speed to the CPU 25 as “0” indicating that the output image is not updated at all. The CPU 25 stops the decoding start instruction and the display start instruction for the decoder 23 based on the speed information. At the same time, the CPU 25 stops the picture input to the decoder 23. For example, the CPU 25 stops reading the picture from the memory 21 and stops inputting the picture to the decoder 23. A picture may be read from the memory 21 as usual, and the read picture may not be supplied to the decoder 23.

With reference to FIG. 7, the operation of each part of the decoder 23 in response to the pause reproduction instruction will be described. The timing of the I ₂ picture in the output data corresponds to the B ₆ picture of the ES input. Therefore, in accordance with the pause command 200, the input of the picture next to the B ₆ picture (B ₇ picture) is stopped at the ES input.

The CPU 25 issues a decoding start command for the B ₆ picture input by the ES input, and stops the decoding start command from the next picture. The decoded B ₆ picture is written into the frame memory 24 in the same manner as in the case of 1 × forward playback.

On the other hand, the timing of the I ₂ picture in the output data corresponds to the B ₃ picture of the display start instruction. Therefore, after the display start command for the B ₃ picture is transmitted, the display start command from the next picture (B ₄ picture) is stopped according to the pause command 200. In a period in which the display start command is stopped and there is no display start command, the picture immediately before the display start command is stopped is repeatedly read from the frame memory 24 in synchronization with the frame synchronization signal. In the example of FIG. 7, the B ₃ picture is repeatedly read from the frame memory 24, and the pause reproduction according to the pause reproduction instruction is realized.

  During pause playback, each picture in the frame memory 24 is retained. Therefore, even when a picture whose pause playback is canceled and input is stopped by a pause playback command is input to the decoder 23 as an ES input, decoding using the picture in the frame memory 24 can be executed.

For example, in the example of FIG. 7, a pause command 200 is transmitted at the timing of the I ₂ picture of the output data, and an instruction to cancel pause playback at a timing two frames after the pause command 200 (position of the step command 201 in FIG. 7). Consider the case where is sent.

In this case, pause playback is released at the timing of the frame synchronization signal immediately after the pause playback release instruction, and a normal decoding operation is started. Thus, the ES inputs, entered during pause reproduction instruction input picture is started from the B ₇ picture is stopped, the decoding start command input B7 picture is transmitted. In response to this decoding start command, the B ₇ picture is decoded using the P ₅ picture and the P ₈ picture held in the frame memory 24.

Similarly, with respect to the display start command, a display start command is output from the B ₄ picture that is the next picture after the B ₃ picture stopped by the pause playback instruction, and is delayed by one frame synchronization signal from the display start command, and the frame memory The B ₄ picture held in 24 is output.

  Next, the operation of each part of the decoder 23 in response to the step reproduction instruction will be described with reference to FIG. For example, step playback is instructed when it is desired to view the next frame after the currently displayed frame during pause playback. In response to the step reproduction instruction, the CPU 11 transmits a step command 201 for performing step reproduction to the CPU 25. In response to the step command 201, the CPU 25 controls each unit of the decoder 23 to perform step reproduction. This control is substantially the same as the control at the time of pause playback release in the pause playback operation described above.

  For example, in the example of FIG. 7, when the step command 201 is transmitted during pause reproduction, the decoding operation for one frame is performed at the timing of the frame synchronization signal immediately after the step command 201.

That is, in the ES input, the B ₇ picture next to the B ₆ picture whose input has been stopped by the previous pause reproduction is input, and a decoding start command for the input B ₇ picture is transmitted. In accordance with this decoding start instruction, the B ₇ picture is decoded using the P ₅ picture and the P ₈ picture held in the frame memory 24 and written in the frame memory 24 in a predetermined manner. Similarly, for the display start command, a display start command for the B ₄ picture, which is the next picture after the B ₃ picture whose update has been stopped by the previous pause playback, is transmitted, and is delayed by one frame synchronization signal from the display start command. Thus, the B ₄ picture held in the frame memory 24 is output.

  In the step reproduction operation, the CPU 25 inputs the next picture to the decoder 23 for each frame update command transmitted from the CPU 11, and outputs the input decoding start command for the next picture and the output frame. A display start command for updating the frame is transmitted in accordance with the frame synchronization signal. That is, in the step reproduction operation, no picture is input to the decoder 23 and the output frame is not updated until a frame update command is transmitted from the CPU 11 to the CPU 25.

  Next, the operation during slow playback will be described. Slow playback with a playback speed of less than 1 × speed is realized by repeatedly outputting the same frame in accordance with the frame synchronization signal and updating the output frame at an update timing corresponding to the speed information. If the value of the speed information transmitted from the CPU 11 is less than “1” and greater than or equal to “0”, the CPU 25 determines that the slow reproduction has been instructed, and obtains the frame update timing according to the speed information. The frame update timing is obtained, for example, by calculation based on given speed information or by referring to a table obtained in advance, for example, stored in the memory 26. For example, in the case of 1/2 times speed slow playback, it is realized by updating the output frame once for two frame synchronization signals based on the speed information “0.5”.

With reference to FIG. 7, the operation of each part of the decoder 23 during slow playback will be described. A value “0.5” is transmitted as speed information from the CPU 11 to the CPU 25, and a ½ × speed command 202 for instructing the CPU 25 to perform ½ × speed slow playback is issued. This 1 / 2-times speed command 202 is made valid at the timing of the next frame synchronization signal. The CPU 25 inputs a B ₁₀ picture as an ES input of the decoder 23 based on the ½ speed instruction 202 and transmits a decoding start instruction for the input B ₁₀ picture to the decoder 23. At the same time, the CPU 25 transmits a display start command to the decoder 23 so as to update the output frame to the next B ₆ picture. In response to this display start command, the output frame is updated with a delay of one frame synchronization signal from the display start command.

At the timing of the next frame synchronization signal at which the display start command for updating the B picture is transmitted, the input is stopped at the ES input, and at the same time, the decoding start command is not transmitted. Since the input is stopped, display start instruction from CPU25 is not transmitted, therefore, the output frame is not updated, B ₆ picture is output again.

  Thereafter, this operation is repeatedly performed at the time of 1 / 2-speed slow playback. Therefore, it can be said that the slow reproduction is equivalent to an operation combining one step reproduction and pause reproduction for a predetermined frame period with respect to a frame updated by the step reproduction.

  That is, when it is not the update timing of the output frame, the CPU 25 stops the transmission of the decoding start command and the display start command to the decoder 23 and causes the decoder 23 to perform the pause reproduction operation described above. Thus, as described above, the decoder 23 holds the picture on the output side because there is no picture to be input, and repeatedly outputs the same picture until the next update timing.

  At the output frame update timing, a decoding start instruction and a display start instruction are transmitted to the decoder 23, and the decoder 23 is caused to perform the above-described step reproduction operation. Thereby, as described above, the decoder 23 decodes the input picture and updates the output picture.

Here, consider the case of performing slow playback (1 / 2-speed slow playback) from the start of playback. When slow playback is instructed at the start of playback, as shown in an example in FIG. 8, prior to outputting the decoded picture, I ₂ picture, P ₅ picture, P ₈ picture, P ₁₁ picture and P ₁₄ are output. Pictures are sequentially input to the decoder 23. The decoder 23 decodes the previously input I picture and four P pictures and writes them into the frame memory 24. When the I picture and the four P pictures are decoded, the B ₀ picture to be output first is input to the decoder 23.

Conventionally, input and decoding of the I picture, the four P pictures, and the B ₀ picture scheduled to be output first to the decoder 23 are performed at the timing of the playback speed by slow playback. For example, the half speed slow command 300 transmitted from the CPU 25 to the decoder 23 becomes effective from the immediately subsequent frame synchronization signal 302. From this frame synchronization signal 302, a slow playback operation is started in accordance with the above-described 1 / 2-speed slow playback sequence. First, an I ₂ picture is input and decoded, and thereafter, every 4th frame synchronization signal period, 4 frames are input. A number of P pictures are sequentially input and decoded. In such a slow playback control method, as already described as a problem, the delay time until the output by the slow playback is actually obtained from the 1 / 2-times slow command is increased according to the slow playback speed. The response is poor.

  Therefore, in the embodiment of the present invention, input to the decoder 23 and decoding at the decoder 23 are performed immediately after the start of reproduction, and pictures that are not output are decoded in advance and written to the frame memory 24. . At this time, the input of the picture to the decoder 23 and the decoding in the decoder 23 are performed in advance for each frame synchronization signal in accordance with a normal single-speed playback sequence.

  In this way, input to the decoder 23 and decoding at the decoder 23 immediately after the start of playback are performed, and a picture that is not output is decoded in advance according to a normal single-speed playback sequence, for example, playback. Even when the slow playback is instructed from the start of the slow playback, the slow playback can be started with good responsiveness.

This will be described more specifically with reference to FIG. FIG. 9 and FIG. 8 described above are simplified diagrams by extracting “decode”, “output”, and “video output” in FIG. 3, for example. The I picture and the four P pictures are input to the decoder 23 prior to all the B pictures, decoded, and written into the frame memory 24. These I picture and P picture are not output at least until the output timing of the B ₁ picture elapses. Of course, the B ₀ picture scheduled to be output first is output at least one frame synchronization signal period after being input to the decoder 23. Therefore, the I picture and the four P pictures and the B ₀ picture that is scheduled to be output first are input to the decoder 23 in advance and decoded, and for example, slow playback is instructed from the start of playback. In this case, input to the decoder 23 and decoding are performed in accordance with the 1 × speed reproduction sequence, and the result is written in the frame memory 24.

Then, input to the decoder 23 and decoding of each picture (pictures after the B ₁ picture) input to the decoder 23 after the B ₀ picture are performed in accordance with the 1 / 2-speed slow playback sequence of the decoder 23. The 1 / 2-speed slow playback sequence in the decoder 23 is the same as the operation already described with reference to FIG. 7, and therefore detailed description thereof is omitted to avoid complexity.

As described above, when the elementary stream is written in the memory 21, the CPU 25 obtains the head of the GOP, the boundary of each frame (picture), and the picture type (I, P, and B) of each picture. is doing. Therefore, input and decoding of the I picture and four P pictures immediately after the 1 / 2-speed slow instruction 300 and the B ₀ picture to be output first are performed at the timing of 1-speed playback, and subsequent pictures It is easy to control so that the input and the decoding are performed in accordance with the 1 / 2-speed reproduction operation.

  The playback control method according to the present invention can be applied to reverse playback as in the case of forward playback described above. FIG. 10 shows an example sequence in the case of performing pause playback, step playback, and 1 / 2-times slow playback during reverse playback. The arrangement of I, P, and B pictures at the ES input is the same as that in the example of FIG. Further, the basic concept of the operation during reverse playback is the same as that during forward playback described with reference to FIG.

  That is, when repeatedly outputting the same frame, such as pause playback, the picture input to the decoder 23 and the decoding start instruction are stopped, and the display start instruction for the output frame is stopped and the output frame is not updated. . Also, when updating an output frame that has been once stopped, such as when pause playback or step playback is performed, the next picture that has been stopped is input, and the input picture is decoded. A display start command is issued, a display start command for the next output frame for which the display start command is stopped is transmitted, and the output frame is updated.

With reference to FIG. 10, the operation of each part of the decoder 23 in response to a pause playback instruction during reverse playback will be described. When the user gives an instruction to pause playback at the timing of the P ₁₄ picture in the output data and the pause command 203 is transmitted, the picture next to the B ₁₀ picture of the ES input corresponding to the timing of the P ₁₄ picture in the output data (B ₍₉ pictures) input is stopped. Also, the decoding start command for the B ₁₀ picture input by the ES input is transmitted, and the decoding start command for the next picture is stopped. The decoded B ₁₀ picture is written in the frame memory 24 in the same manner as in the case of reverse playback at 1 × speed.

On the output data side, after the display start command for the B ₁₃ picture corresponding to the timing of the P ₁₄ picture of the output data is transmitted, the display start command from the next picture (B ₁₂ picture) is stopped and the display start command is issued. In the absence period, the picture immediately before the display start command is stopped (B ₁₃ picture in the example of FIG. 10) is repeatedly read out from the frame memory 24 in synchronization with the frame synchronization signal.

  Even during reverse playback, each picture in the frame memory 24 is retained during pause playback. Therefore, even when a picture whose pause reproduction is canceled and input is stopped by the pause command 203 is input to the decoder 23 as an ES input, decoding using the picture in the frame memory 24 can be executed.

When cancellation of pause playback is instructed, pause playback is canceled at the timing of the frame synchronization signal immediately after the instruction, and a normal decoding operation is started. For example, in the example of FIG. 10, sent pause command 203 at the timing of P ₁₄ picture of the output data, an instruction to release the pause playback timing of pause command 203 from the second frame after (position of the step instructions 204 of FIG. 10) In the ES input, the input of the picture is started from the B ₉ picture that was stopped at the time of the pause command 203, and from the B ₉ picture at the timing of the frame synchronization signal immediately after the pause playback release instruction. The decryption start command is transmitted. In accordance with this decoding start instruction, the B ₉ picture is decoded using the P ₈ picture and the P ₁₁ picture held in the frame memory 24.

Similarly, with respect to the display start command, a display start command is transmitted from the B ₁₂ picture that is the next picture of the B ₁₃ picture stopped by the pause playback instruction, and is delayed by one frame synchronization signal from the display start command, and the frame memory The B ₁₂ picture held in 24 is output.

  Next, with reference to FIG. 10, the operation of each part of the decoder 23 in response to a step reproduction instruction during reverse reproduction will be described. For example, when it is desired to see the next frame of the frame currently displayed during pause playback (in the case of reverse playback, the previous frame in forward playback), step playback is instructed, and the CPU 11 instructs the CPU 25 to A step command 204 for performing step reproduction is transmitted.

For example, in the example of FIG. 10, when the step command 204 is transmitted during pause playback, the ES input is input with the B ₉ picture next to the B ₁₀ picture whose input has been stopped by the previous pause command 203. A start command is sent. In accordance with this decoding start instruction, the B ₉ picture is decoded using the P ₈ picture and the P ₁₁ picture held in the frame memory 24 and written in the frame memory 24 in a predetermined manner.

Similarly, for the display start command, a display start command for the B ₁₂ picture that is the next picture of the B ₁₃ picture that has been updated by the previous pause command 203 is transmitted, and is delayed by one frame synchronization signal from the display start command. Then, the B ₁₂ picture held in the frame memory 24 is output. Also in this case, as in the case of forward reproduction, no picture is input to the decoder 23 and the output frame is not updated until a frame update command is transmitted from the CPU 11 to the CPU 25.

  Next, the operation during slow playback will be described. Even during reverse playback, as with forward playback described above, slow playback with a playback speed of less than 1 × speed repeatedly outputs the same frame according to the frame sync signal, and outputs an output frame at an update timing according to the speed information. It is realized by updating.

With reference to FIG. 10, the operation of each part of the decoder 23 in the slow playback during the reverse playback will be described. A value “0.5” is transmitted as speed information from the CPU 11 to the CPU 25, and a ½ × speed command 205 for instructing the CPU 25 to perform ½ × speed slow playback is issued. It is assumed that the instruction for instructing reverse playback has been transmitted from the CPU 11 to the CPU 25 in advance. A reverse playback command can be included in the speed information. The 1/2 speed instruction 205 is made valid at the timing of the next frame synchronization signal. The CPU 25 inputs a B ₆ picture as an ES input of the decoder 23 based on the 1/2 × speed instruction 205, transmits a decoding start instruction for the input B ₆ picture to the decoder 23, and sends it to the decoder 23. The display start command is transmitted so as to update the output frame to the next B ₁₀ picture. In response to this display start command, the output frame is updated with a delay of one frame synchronization signal.

At the timing of the next frame synchronization signal at which the display start command for updating the B picture is transmitted, the input is stopped at the ES input, and at the same time, the decoding start command is not transmitted. Since the input is stopped, display start instruction from CPU25 is not transmitted, therefore, the output frame is not updated, B ₁₀ picture is output again.

  Thereafter, this operation is repeatedly performed at the time of 1 / 2-speed slow playback. Therefore, even in reverse playback, slow playback is equivalent to an operation that combines one step playback and pause playback for a predetermined frame period with respect to a frame updated by the step playback.

Consider a case where slow playback (1 / 2-speed slow playback) is performed from the start of reverse playback. When slow playback is instructed at the start of reverse playback, as shown in an example in FIG. 11, prior to outputting the decoded picture, I ₂ picture, P ₅ picture, P ₈ picture, P ₁₁ picture, and P ₁₄ pictures are sequentially input to the decoder 23. The decoder 23 decodes the previously input I and four P pictures and writes them into the frame memory 24. When I and four P pictures are decoded, the (B ₁ ) picture of the previous GOP that is scheduled to be output first and in reverse playback order is input to the decoder 23.

When the input and decoding to the decoder 23 of the I picture, the four P pictures, and the (B ₁ ) picture that is scheduled to be output first are performed according to the sequence by the slow reproduction in the reverse direction as in the prior art In the same manner as the conventional forward reproduction example described with reference to FIG. 8, the delay time until the output by the slow reproduction is actually obtained from the 1 / 2-times slow instruction is increased according to the slow reproduction speed. And responsiveness is poor.

  Also in the case of reverse reproduction, the reproduction control method according to the embodiment of the present invention described with reference to FIG. 9 is applied, and input to the decoder 23 and decoding by the decoder 23 are performed immediately after the reproduction is started and output is performed. For a picture that does not exist, it is decoded in advance and written in the frame memory 24. At this time, the input of the picture to the decoder 23 and the decoding in the decoder 23 are performed in advance in a normal single-speed playback sequence. Also in reverse playback, in this way, by performing decoding in advance on a picture that is input to the decoder 23 and decoded by the decoder 23 and not output immediately after the start of playback, for example, from the start of playback. Even when reverse playback slow playback is instructed, slow playback can be started with good responsiveness.

This will be described more specifically with reference to FIG. Note that FIG. 12 and FIG. 11 described above are diagrams in which, for example, “decode”, “output”, and “video output” in FIG. 3 are extracted and simplified. The I picture and the four P pictures are input to the decoder 23 prior to all the B pictures, decoded, and written into the frame memory 24. These I and P pictures are not output at least until the output timing of the (B ₀ ) picture of the previous GOP in the reverse playback order. The (B ₁ ) picture scheduled to be output first is, of course, output at least one frame synchronization signal period after being input to the decoder 23. Therefore, the I picture, the four P pictures, and the (B ₁ ) picture that is scheduled to be output first are input to the decoder 23 in advance and are decoded. For example, slow playback is performed from the start of playback. When instructed, input to the decoder 23 and decoding are performed according to the 1 × speed reproduction sequence, and the result is written in the frame memory 24.

Then, the input to the decoder 23 and the decoding of each picture (pictures after the (B ₀ ) picture) input to the decoder 23 from the (B ₁ ) picture are thrown at 1/2 times speed in the reverse direction of the decoder 23. Follow the playback sequence. Since the half-speed slow playback sequence at the time of reverse playback in the decoder 23 is the same as the operation already described with reference to FIG. 10, detailed description thereof is omitted to avoid complexity.

Next, a first modification of the embodiment of the present invention will be described. In the above description, the arrangement of pictures input to the decoder 23 is rearranged in a predetermined manner using the memory 21 in order to support reverse reproduction, but this is not limited to this example. That is, the playback control method according to the present invention can be applied to elementary streams of other arrangements. The first modification of the embodiment of the present invention is based on the standard picture arrangement (I ₂ B ₀ B ₁ P ₅ B _{3) in accordance} with the playback control method by the 1 / 2-speed slow instruction according to the embodiment described above. B ₄ P ₈ B ₆ B ₇ P ₁₁ B ₉ B ₁₀ P ₁₄ B ₁₂ B ₁₃ )

First, the operation of each part of the decoder 23 at the time of forward reproduction at 1 × speed with a standard arrangement will be schematically described with reference to FIG. In FIG. 13, diagonal lines attached to squares indicating pictures are for distinguishing GOPs in ES input. In addition, at the timing of the display start instruction for the first B picture in FIG. 13, GOP # 0 (not shown) immediately before GOP # 1 has already been input to the decoder 23, and predetermined processing such as decoding and output has already been completed. In GOP # 1, it is assumed that the I ₂ picture and the B ₀ picture have already been input to the decoder 23 and that the decoding of the I ₂ picture has been completed.

At the timing of the B ₀ picture display start command, the already input B picture is decoded using the P ₁₄ picture of GOP # 0 and the I ₂ picture of GOP # 1 and written into the frame memory 24. At the same time, the B ₁ picture is input to the decoder 23 as an ES input, and the decoding start command for the input B ₁ picture is transmitted from the CPU 25 to the decoder 23. The B ₀ picture is output after being delayed by one frame synchronization signal with respect to the display start command.

Next, the P ₅ picture is input to the decoder 23 as the ES input at the timing of the B ₁ picture display start instruction, decoded using the I ₂ picture, and stored in the frame memory 24 at the timing of the next frame synchronization signal. Written. The B picture is output after being delayed by one frame synchronization signal with respect to the display start command. Thereafter, this process is repeated in accordance with the input order of the elementary stream pictures.

FIG. 14 shows an example of a sequence in the case of performing pause playback, step playback, and 1 / 2-speed slow playback during forward playback according to a standard arrangement. First, the operation of pause playback will be schematically described. For example the user, while watching the reproduced video by the video data output by the video output, an indication of the pause reproduction is performed at the timing of the B ₄ picture in the output data. The CPU 11 transmits the value of the speed information to the CPU 25 as “0” by the pause command 210 corresponding to the pause reproduction instruction. The CPU 25 stops the decoding start instruction and the display start instruction for the decoder 23 based on the speed information.

The timing of the I ₂ picture in the output data corresponds to the B ₄ picture of the ES input. Therefore, the input of the picture next to the B ₄ picture (P ₈ picture) is stopped at the ES input. The CPU 25 issues a decoding start command for the B ₄ picture input by the ES input, and stops the decoding start command from the next picture. The decoded B ₄ picture is written into the frame memory 24.

On the other hand, the timing of the I ₂ picture in the output data corresponds to the B ₃ picture of the display start instruction. Therefore, after the display start command for the B ₃ picture is transmitted, the display start command from the next picture (B ₄ picture) is stopped. In a period in which the display start command is stopped and there is no display start command, the picture immediately before the display start command is stopped is repeatedly read from the frame memory 24 in synchronization with the frame synchronization signal. In the example of FIG. 14, the B ₃ picture is repeatedly read from the frame memory 24, and pause playback according to the pause playback instruction is realized.

  During pause playback, each picture in the frame memory 24 is retained. Therefore, even when a picture whose pause playback is canceled and input is stopped by a pause playback command is input to the decoder 23 as an ES input, decoding using the picture in the frame memory 24 can be executed.

For example, in the example of FIG. 14, a pause command 210 is transmitted at the timing of the I ₂ picture of the output data, and an instruction to cancel pause playback at a timing two frames after the pause command 210 (position of the step command 211 in FIG. 14). Consider the case where is sent.

In this case, the pause command 210 is canceled at the timing of the frame synchronization signal immediately after the instruction to cancel pause playback, and the normal decoding operation is started. Thus, the ES input, input by the pause command 210 is input picture is started from P ₈ picture is stopped, the decoding start instruction is transmitted. In accordance with this decoding start command, the P ₈ picture is decoded using the P ₅ picture held in the frame memory 24. Similarly, for the display start command, the display start command is started from the B ₄ picture that is the next picture of the B ₃ picture stopped by the pause command 210, and is delayed by one frame synchronization signal from the display start command. The B ₄ picture held in 24 is output.

  Next, the operation of each part of the decoder 23 in response to the step reproduction instruction will be described with reference to FIG. For example, in the example of FIG. 14, when a step command I211 instructing step playback is transmitted during pause playback, a decoding operation for one frame is performed at the timing of the frame synchronization signal immediately after the step command 211.

That is, in the ES input, the P ₈ picture next to the B ₄ picture whose input has been stopped by the immediately preceding pause instruction 210 is input, and a decoding start instruction for the P ₈ picture is transmitted. In accordance with this decoding start instruction, the P ₈ picture is decoded and written in the frame memory 24 in a predetermined manner. Similarly, for the display start command, a display start command for the B ₄ picture, which is the next picture after the B ₃ picture whose update has been stopped by the previous pause command 210, is transmitted, and is delayed by one frame synchronization signal from the display start command. Then, the B ₄ picture held in the frame memory 24 is output.

With reference to FIG. 14, the operation of each part of the decoder 23 during slow playback will be described. A value “0.5” is transmitted as speed information from the CPU 11 to the CPU 25, and a ½ × speed command 212 for instructing ½ × speed slow reproduction is issued. This 1 / 2-times speed command 212 is made valid at the timing of the next frame synchronization signal. The CPU 25 inputs a B ₇ picture as an ES input of the decoder 23 based on the 1 / 2-speed instruction 212 and transmits a decoding start instruction for the input B ₇ picture to the decoder 23. At the same time, the CPU 25 transmits a display start command to the decoder 23 so as to update the output frame to the next B ₆ picture. In response to this display start command, the output frame is updated with a delay of one frame synchronization signal.

At the timing of the next frame synchronization signal at which the display start command for updating the B picture is transmitted, the input is stopped at the ES input, and at the same time, the decoding start command is not transmitted. Since the input is stopped, display start instruction from CPU25 is not transmitted, therefore, the output frame is not updated, B ₆ picture is output again.

  Thereafter, this operation is repeatedly performed in accordance with the ES input, display start command, and the like during 1 / 2-speed slow playback.

  Here, in the standard arrangement, the problem in the case where the slow reproduction (1 / 2-speed slow reproduction) is performed from the start of the reproduction is as already described as the subject of the invention. Is omitted.

  Also in the case of a standard picture arrangement, the playback control method according to the embodiment of the present invention described with reference to FIG. 9 is applied, and input to the decoder 23 and decoding by the decoder 23 are performed immediately after the start of playback. Pictures that are not output are decoded in advance and written to the frame memory 24. At this time, the input of the picture to the decoder 23 and the decoding in the decoder 23 are performed in advance according to a normal single-speed playback sequence. In this way, by performing decoding in advance on a picture that is input to the decoder 23 and decoded by the decoder 23 and not output immediately after the start of playback, for example, slow playback is instructed from the start of playback. Even in such a case, the slow playback can be started with good responsiveness.

This will be described more specifically with reference to FIG. Note that FIG. 15 is a diagram in which, for example, “decode”, “output”, and “video output” in FIG. 3 are extracted and simplified. In the standard picture arrangement, the I ₂ picture is output at the timing when the P ₅ picture is input to the decoder 23 and decoded. For this reason, up to P ₅ pictures, that is, I ₂ picture, B ₀ picture, and B ₁ picture, are input to the decoder 23 in advance and are decoded. For example, when slow playback is instructed from the start of playback. Input to the decoder 23 and decoding are performed in accordance with the 1 × speed reproduction sequence, and the result is written in the frame memory 24.

Incidentally, B ₀ picture and B ₁ picture is to be decoded using the previous GOP and (P ₁₄₎ picture, when the (P ₁₄₎ picture is not present on the frame memory 24, decodes Not output and output.

Then, the control of the timing of the input timing and decoding for each picture (P ₅ picture after picture) inputted from the following B ₁ picture decoder 23, carried out according to the sequence of the half speed slow reproduction of the decoder 23. The 1 / 2-speed slow playback sequence in the decoder 23 is the same as the operation already described with reference to FIG. 14, and thus detailed description thereof is omitted to avoid complexity.

  Next, a second modification of this embodiment will be described. In the above description, the case where one decoder 23 is mounted on the decoder board 2 has been described, but this is not limited to this example. That is, the present invention can also be applied to the case where a video stream is decoded using a plurality of decoders 23, 23,.

  FIG. 16 shows an example in which the decoder board 2 includes three decoders 23A, 23B, and 23C, and the decoding unit 40 'includes these three decoders. In FIG. 16, the same reference numerals are given to the same parts as those in FIG. 1 described above, and detailed description thereof is omitted. The decoder 23A has a frame memory 24A. Similarly, the decoder 23B has a frame memory 24B, and the decoder 23C has a frame memory 24C. The configurations of the decoders 23A, 23B, and 23C are the same as those described with reference to FIG.

  The elementary stream supplied to the PCI bridge 20 and stored in the memory 21 is supplied to the decoding unit 40 '. At this time, the CPU 25 sequentially distributes the elementary streams to the decoders 23A, 23B, and 23C for each GOP. Each of the pictures decoded by the decoders 23A, 23B and 23C is supplied to the selector 27. The selector 27 selects and outputs the supplied pictures on a picture-by-picture basis in accordance with the control of the CPU 25.

  In this way, by decoding one elementary stream using a plurality of decoders 23A, 23B, and 23C, the processing capacity of the decoder board 2 as a whole is improved, and, for example, higher definition video is displayed. Thus, an elementary stream with a high data rate can be processed. Further, there is a margin in the use of the frame memory 24.

  FIG. 17 shows a schematic sequence of input / output and internal processing during forward reproduction when three decoders 23A, 23B and 23C are used. In the second modified example of this embodiment, the picture arrangement of the elementary stream supplied to the decoding unit 40 ′ is first set to the I and P pictures in the GOP as described in the above embodiment. Are arranged first, and then B pictures are arranged in order.

Here, when the elementary streams are distributed and supplied to each of the plurality of decoders 23A, 23B, and 23C for each GOP, the GOP supplied to each decoder is a closed GOP in which decoding is completed by the GOP itself. It must be in the form of In the example of the above-described embodiment, the GOP is configured as an open GOP, and the B ₀ picture and the B ₁ picture cannot be decoded unless the P ₁₄ picture of the previous GOP is used.

Therefore, for example, with respect to GOP # 0 of the original elementary stream, the I ₂ picture, the B ₀ picture, and the B ₁ picture of GOP # _1, which is the GOP immediately after GOP # 0, are changed to GOP # 0. It is included and supplied to one decoder as a picture array like the array (3). In the array (3), the picture type enclosed in parentheses () mainly indicates a picture included in the GOP next to the GOP in the elementary stream to be processed.
I ₂ P ₅ P ₈ P ₁₁ P ₁₄ (I ₂ ) B ₃ B ₄ B ₆ B ₇ B ₉ B ₁₀ B ₁₂ B ₁₃ (B ₀ ) (B ₁ ) (3)

With such a picture arrangement, the (I ₂ ) picture is decoded by itself, the (B ₀ ) picture and the (B ₁ ) picture are the P ₁₄ picture and the decoded (I ₂ ) picture. And are decrypted using Therefore, the picture array according to the array (3) can be completed and decoded by itself to form a closed GOP.

  Returning to the description of FIG. 17, the upper stage shows the processing of the decoder 23A, the middle stage shows the processing of the decoder 23B, and the lower stage shows the processing of the decoder 23C. The bottom row shows the output video data output from the selector 27. In FIG. 17, the display start command for the decoders 23B and 23C is the same as that for shifting “output” by one frame synchronization signal, and is omitted. In FIG. 17, the diagonal lines attached to the squares indicating the pictures are for distinguishing GOPs in the ES input.

  According to the above arrangement (3), in each of the decoders 23A, 23B, and 23C, the input timing of the I picture and the four P pictures, and the input timing of the decoder that performs the processing of the GOP that is input immediately before, By duplicating, the decoding operation can be performed at a timing corresponding to the output.

For example, taking the processing of the decoder 23A as an example, although not shown, an I ₂ picture, a P ₅ picture, a P ₈ picture, a P ₁₁ picture, a P ₁₄ picture, and an (I ₂ ) picture are sequentially input at the ES input. The data is decoded by a decoding start command and written in the frame memory 24.

Subsequently, a B ₃ picture and a B ₄ picture are input, decoded by a decoding start command and written into the frame memory 24, and at the same time, a display start command for these B ₃ picture and B ₄ picture is transmitted. Output is performed with a delay of one frame synchronization signal from the display start command. Note that the display start command for the I ₂ picture is issued at the input timing of the B ₃ picture. Thereafter, B ₆ picture, B ₇ picture, B ₉ picture, B ₁₀ picture, B ₁₂ picture, and B ₁₃ picture are sequentially input. At this time, the period corresponding to the order of P pictures that have already been decoded is skipped, and each B picture is input. The B pictures are decoded in the order of input, and a display start command is transmitted simultaneously with the decoding. A display start command is also transmitted in correspondence with the output order even for a P picture that has already been decoded.

When the B ₁₃ picture is input, the (B ₀ ) picture and the (B ₁ ) picture are input after a period corresponding to the P ₁₄ picture, that is, one frame synchronization signal period. Decoding is performed using the decoded (I ₂ ) picture and P ₁₄ picture, and a display start command is transmitted simultaneously with the decoding. (B ₁ ) After the picture is input, the picture is input with a period of two cycles of the array (3).

  By sequentially repeating the above sequence in the decoders 23A, 23B and 23C, forward reproduction is performed with a configuration using the three decoders 23A, 23B and 23C.

  FIG. 18 shows an example sequence in the case of performing pause playback, step playback, and half-speed slow playback during forward playback when three decoders 23A, 23B, and 23C are used. Even when a plurality of decoders are used, the basic concept of each operation is the same as that when only one decoder is used. Commands such as pause playback, step playback, and slow playback are supplied from the CPU 25 to the decoders 23A, 23B, and 23C. In FIG. 18, “* (star mark)” attached to the picture type is for distinguishing the GOP in the ES input.

First, the operation according to the pause reproduction instruction will be described. Assume that a pause command 220 for instructing pause playback is transmitted at the timing of the I ₂ picture of the output video data shown at the bottom. The pause command 220 is made valid at the timing of the frame synchronization signal immediately after the pause command 220 is transmitted. The timing of the I ₂ picture of the output video data corresponds to the B ₄ picture of the ES input. In response to the pause command 220, ES input from the next picture B ₄ picture is stopped. As the input is stopped, the decoding start instruction from the picture next to the input B picture is stopped.

The timing of the I ₂ picture in the output data corresponds to the B ₃ picture of the display start command. Therefore, after a B ₃ picture display start command is transmitted, a display start command from the next picture (B ₄ picture) is stopped, and the B ₃ picture is repeatedly output in synchronization with the frame synchronization signal. Thereby, pause reproduction according to the pause command 220 is realized.

Incidentally, for example, as the timing of P ₁₄ pictures in the output data of FIG. 17, parallel picture to a plurality of decoders 23A and 23B are input (in this case (B ₁₎ picture and (P ₁₄₎ picture In such a case, a decoding start command is transmitted to each of the decoders 23A and 23B to which a picture is input, and each decoding is performed. Further, when a pause command is transmitted at a timing when pictures are input in parallel to a plurality of decoders, ES input to each of the plurality of decoders is stopped.

  During pause playback, each picture in the frame memories 24A, 24B and 24C is held in each of the decoders 23A, 23B and 23C. Therefore, even if a picture whose pause playback is canceled and input is stopped by the pause command is input to the decoders 23A, 23B, and 23C, the pictures in the frame memories 24A, 24B, and 24C are respectively stored in the decoders to which the pictures are input. The decryption used can be performed.

Note that the same processing is performed even when pause playback is transmitted at a timing at which output is switched between decoders, such as when (B ₀ ) picture or (B ₁ ) picture is output in FIG.

For example, when the pause command is transmitted at the timing of the (B ₀ ) picture in the output data, the ES input of the decoder 23A is stopped and the ES input of the decoder 23B is stopped at the corresponding next (B ₃ ) picture. The Also, ES input to the decoder 23C is stopped. The display start command is also stopped at the (B ₁ ) picture, and thereafter the (B ₁ ) picture is repeatedly output until the pause command is canceled.

Also, for example, when a Po instruction is transmitted at the timing of (B ₁ ) picture in the output data, the ES input of the decoder 23A is stopped and the ES input of the decoder 23B is stopped at the corresponding (B ₄ ) picture. Is done. Also, ES input to the decoder 23C is stopped. The display start command is stopped at the (B ₃ ) picture for the decoder 23B, and thereafter the (B ₃ ) picture is repeatedly output until the pause command is canceled.

Next, with reference to FIG. 18, the operation according to the step reproduction instruction will be described. For example, when the step command 221 is transmitted during pause playback as in the step command 221 of FIG. 18, the decoding operation for one frame is performed at the timing of the frame synchronization signal immediately after the step command 221. In this example, the ES input is the P ₅ picture that has been input and decoded since the picture next to the B ₄ picture whose input has been stopped by the pause instruction 220 is input. I will not. As for the display start command, a display start command for the B ₄ picture, which is the next picture after the B ₃ picture that has been updated by the previous pause playback, is transmitted, delayed by one frame synchronization signal from the display start command, The B ₄ picture held in the frame memory 24A is output.

Even when the output is switched between decoders, such as when the (B ₁ ) picture in FIG. 17 is output, display is started for the switching destination decoder in the same manner as in the pause playback operation described above. As commands are transmitted, ES input to each decoder is initiated.

Next, with reference to FIG. 18, the operation according to the slow playback will be described. For example, a 1/2 × speed command 222 for instructing a 1/2 × speed slow playback is made valid in the next frame synchronization signal cycle. Based on this 1/2 × speed command 222, the CPU 25 uses B as an ES input of the decoder 23A. ₇ pictures are input, and a decoding start instruction for this picture is transmitted to the decoder 23A. At the same time, the CPU 25 transmits a display start command to the decoder 23A so as to update the output frame to the next B ₆ picture. In response to the display start command, the output frame of the decoder 23A is updated with a delay of one frame synchronization signal from the display start command.

At the next frame synchronization signal timing when the display start command to update to the B ₆ picture is transmitted, the input is stopped at the ES input, and the decoding start command is not transmitted at the same time. In the example of FIG. 18, the next picture of ES input entered in response to the 1/2-speed instruction 222, a P ₈ picture, already input and decoding is complete. Since the input is stopped, the display start instruction is not sent from the CPU 25, therefore, the output frame is P ₅ picture is not updated is output again. This operation is repeated, and 1 / 2-speed slow playback is realized.

When the elementary stream is input to the next decoder (decoder 23B) in parallel with the input of the elementary stream to the decoder 23A during the half-speed slow playback (for example, in FIG. 17). decoder 23B (I ₂₎ input from the picture), the input of the elementary stream in the decoder 23B also, similar to the input of the decoder 23A, the input and stop every picture is repeated.

Even when three decoders 23A, 23B, and 23C are used, when slow playback is performed in the forward direction from the start of playback (1 / 2-speed slow playback), as shown in FIG. As in the case of performing slow reproduction in the forward direction using one decoder 23, the I ₂ picture, P ₅ picture, P ₈ picture, P ₁₁ picture, P ₁₄ picture, and (I ₂ picture are output prior to picture output. ) Pictures are sequentially input to, for example, the decoder 23A. The decoder 23A decodes the previously input I ₂ picture, four P pictures and (I ₂ ) picture and writes them into the frame memory 24A.

Conventionally, the input and decoding of the I ₂ picture, the four P pictures, and the (I ₂ ) picture to the decoder 23 are performed according to a sequence by slow reproduction. Therefore, as already described as a problem, the delay time until the output by the slow playback is actually obtained from the 1 / 2-speed slow command becomes long according to the slow playback speed, and the responsiveness is poor.

  Even when a plurality of decoders are used, the playback control method according to the embodiment of the present invention described with reference to FIG. 9 is applied, and for example, the input to the decoder 23A and the decoding at the decoder 23A are performed immediately after the start of playback and the output is output. Pictures not to be performed are previously decoded and written in the frame memory 24A. At this time, the input of the picture to the decoder 23A and the decoding in the decoder 23A are performed in advance according to a normal single-speed playback sequence. In this manner, for example, a picture that is input to the decoder 23A and decoded by the decoder 23A and not output immediately after the start of playback is decoded in advance, so that, for example, a slow-down of forward playback from the start of playback is performed. Even when playback is instructed, slow playback can be started with good responsiveness.

This will be described more specifically with reference to FIG. FIG. 20 and FIG. 19 described above are diagrams in which, for example, “decode”, “output”, and “video output” in FIG. 3 are extracted and simplified. The I ₂ picture, the four P pictures, and the (I ₂ ) picture are input to, for example, the decoder 23A prior to all the B pictures, decoded, and written to the frame memory 24A. Among these, the (I ₂ ) picture is a picture scheduled to be output first. Therefore, the I ₂ picture, the four P pictures, and the (I ₂ ) picture are input to the decoder 23A in advance and decoded, and for example, when slow playback is instructed from the start of playback, the 1 × speed In accordance with the reproduction sequence, input to the decoder 23A and decoding are performed, and the result is written into the frame memory 24A.

Then, the input and decoding for (I ₂₎ each picture that is input from the next picture to the decoder 23A (B ₃ and later pictures Picture), carried out according to the sequence of the half speed slow reproduction of the decoder 23. Since the 1 / 2-speed slow playback sequence in the decoder 23 is the same as the operation already described with reference to FIG. 18, a detailed description thereof is omitted to avoid complexity.

  FIG. 21 shows a schematic sequence of input / output and internal processing during reverse reproduction when three decoders 23A, 23B and 23C are used. In FIG. 21, the diagonal lines attached to the squares indicating pictures are for distinguishing GOPs in ES input. As described in the above-described embodiment, first, the I and P pictures in the GOP are arranged first, and then the B pictures are arranged in order. An array. Also in this case, as in the case of the forward reproduction described above, the elementary stream input to each of the plurality of decoders 23A, 23B, and 23C needs to be in the form of a closed GOP.

In the case of reverse reproduction, a picture arrangement like the arrangement (4) is used. In the array (4), the picture type enclosed in parentheses () indicates a picture included in the previous GOP in the playback order of the GOP in the reverse playback in the original elementary stream.
I ₂ P ₅ P ₈ P ₁₁ P ₁₄ (I ₂ ) (B ₀ ) (B ₁ ) B ₁₃ B ₁₂ B ₁₀ B ₉ B ₇ B ₆ B ₄ B ₃ (4)

With such a picture arrangement, the (I ₂ ) picture is decoded by itself, the (B ₀ ) picture and the (B ₁ ) picture are the P ₁₄ picture and the decoded (I ₂ ) picture. And are decrypted using Therefore, the picture array according to the array (4) can be completed and decoded by itself to form a closed GOP.

  According to the array (4) described above, in each of the decoders 23A, 23B, and 23C, the timing of the I picture and the four P pictures is set to the input timing of the decoder that performs the process of the GOP input immediately before. By overlapping, the decoding operation can be performed at a timing corresponding to the output.

For example, taking the processing of the decoder 23A as an example, although not shown, an I ₂ picture, a P ₅ picture, a P ₈ picture, a P ₁₁ picture, a P ₁₄ picture, and an (I ₂ ) picture are sequentially input at the ES input. The data is decoded by a decoding start command and written in the frame memory 24.

Subsequently, a (B ₁ ) picture and a (B ₀ ) picture are input, decoded using the P ₁₄ picture and the (I ₂ ) picture by a decoding start instruction, written to the frame memory 24, and one frame from the display start instruction. Output is made with a delay of the synchronizing signal.

Next, a display start command is transmitted corresponding to the output order for the P ₁₄ picture that has already been decoded, and further, a B ₁₃ picture, a B ₁₂ picture, a B ₁₀ picture, a B ₉ picture, and a B ₇ picture. , B ₆ picture, B ₄ picture, and B ₃ picture are sequentially input. At this time, a period corresponding to the order of P pictures that have already been decoded is skipped, and each B picture is input. The B pictures are decoded in the order of input, and a display start command is transmitted simultaneously with the decoding. Further, a display start command is transmitted to the I ₂ picture that has already been decoded.

After input of the B ₃ picture, at a time of two cycles of the sequence (4), the picture is input.

  By sequentially repeating the above sequence in the decoders 23A, 23B and 23C, reverse reproduction is performed with a configuration using the three decoders 23A, 23B and 23C.

  FIG. 22 shows an example sequence in the case of performing pause playback, step playback, and half-speed slow playback during reverse playback when three decoders 23A, 23B, and 23C are used. In FIG. 22, “* (star mark)” and “**” attached to the picture type are for distinguishing GOPs in the ES input. Also in the case of reverse reproduction, the basic concept of each operation is the same as when only one decoder is used.

First, the operation according to the pause reproduction instruction will be described. It shall pause command 230 to instruct the pause playback timing of P ₁₄ picture of the output video data shown at the bottom has been sent. The pause command 230 is made valid at the timing of the frame synchronization signal immediately after the pause command 230 is transmitted. The timing of the P ₁₄ picture of the output video data corresponds to the B ₁₂ picture of the ES input. In response to the pause command 230, ES input from the next picture B ₁₂ picture is stopped. With the stop of input, decoding start command from the next picture of the input B ₁₂ picture is stopped.

Further, the timing of the P ₁₄ picture in the output data corresponds to the B ₁₃ picture of the display start instruction. Therefore, after the B ₁₃ picture display start command is transmitted, the display start command from the next picture (B ₁₂ picture) is stopped, and the B ₁₃ picture is repeatedly output in synchronization with the frame synchronization signal. Thereby, pause reproduction according to the pause command 230 is realized.

Note that pictures are input in parallel to the plurality of decoders 23A and 23B, as in the timing of the P ₅ picture in the output data of FIG. 21 (in this case, (B ₃ ) picture and (P ₁₄ ) picture) In such a case, a decoding start command is transmitted to each of the decoders 23A and 23B to which a picture is input, and each decoding is performed. In addition, when a pause command is transmitted at a timing when pictures are input in parallel to a plurality of decoders, picture input to each of the plurality of decoders is stopped.

  During pause playback, each picture in the frame memories 24A, 24B and 24C is held in each of the decoders 23A, 23B and 23C. Therefore, even if a picture for which the pause command has been canceled and input has been stopped by the pause command is input to the decoders 23A, 23B, and 23C, the pictures in the frame memories 24A, 24B, and 24C are changed in each of the decoders to which the pictures are input. The decryption used can be performed.

Note that the same processing is performed even when a pause command is transmitted at a timing at which output is switched between decoders, such as when an (I ₂ ) picture is output in FIG. For example, when the pause reproduction command is transmitted at the timing of the (I ₂ ) picture in the output data, the ES input of the decoder 23A is stopped and the ES input of the decoder 23B is stopped at the corresponding next picture. In the example of FIG. 21, the input of the decoder 23B is vacated in correspondence with the P ₁₄ picture that has already been decoded, so that the input of the next B ₁₃ picture is stopped. Also, ES input to the decoder 23C is stopped. The display start command is also stopped at the (I ₂ ) picture, and thereafter the (I ₂ ) picture is repeatedly output until the pause command is canceled.

Next, with reference to FIG. 22, the operation according to the step reproduction instruction will be described. For example, when a step command 231 for instructing step playback is transmitted during pause playback by the pause command 230 as in the step command 231 of FIG. 22, one frame is sent at the timing of the frame synchronization signal immediately after the step playback command. The decoding operation is performed. In this example, the ES input is a P ₁₁ picture that has already been input and decoded since the picture next to the B ₁₂ picture whose input has been stopped by the pause instruction 230, so that the actual picture is not input. I will not. As for the display start command, a display start command for the B ₁₂ picture, which is the next picture after the B ₁₃ picture that has been stopped by the previous pause playback, is transmitted, delayed by one frame synchronization signal from the display start command, The B ₁₂ picture held in the frame memory 24A is output.

Even when the output is switched between decoders, such as when the (I ₂ ) picture is output in FIG. 21, display is started for the switching destination decoder in the same manner as in the pause playback process described above. As commands are transmitted, ES input to each decoder is initiated.

Next, with reference to FIG. 22, the operation according to the slow playback will be described. For example, a 1/2 × speed command 232 for instructing a 1/2 × speed slow playback is made valid in the next frame synchronization signal cycle. _Nine pictures are input, and a decoding start instruction for this picture is transmitted to the decoder 23A. At the same time, the CPU 25 transmits a display start command to the decoder 23A so as to update the output frame to the next B ₁₀ picture. In response to the display start command, the output frame of the decoder 23A is updated with a delay of one frame synchronization signal from the display start command.

In the next frame synchronizing signal timing display start command is sent to update the B ₁₀ picture input in ES input is stopped, the decoding start command therewith also not transmitted. Since the input is stopped, display start instruction from CPU25 is not transmitted, therefore, the output frame B ₁₀ picture is not updated is output again. This operation is repeated, and 1 / 2-speed slow playback is realized.

When the elementary stream is input to the next decoder (decoder 23B) in parallel with the input of the elementary stream to the decoder 23A during 1 / 2-speed slow playback (for example, in FIG. 21). input from I ₂ picture decoder 23B), the input of the elementary stream in the decoder 23B also, similar to the input of the decoder 23A, the input and stop every picture is repeated.

Even when three decoders 23A, 23B, and 23C are used, when performing slow playback in the reverse direction from the start of playback (1 / 2-speed slow playback), as shown in FIG. As in the case of performing slow reproduction in the forward direction using one decoder 23, the I ₂ picture, P ₅ picture, P ₈ picture, P ₁₁ picture, P ₁₄ picture, and (I ₂ picture are output prior to picture output. ) Pictures are sequentially input to, for example, the decoder 23A. In addition, the (B ₁ ) picture scheduled to be output first is input to the decoder 23A. The decoder 23A decodes the previously input I ₂ picture, four P pictures, (I ₂ ) picture and (B ₁ ) picture, and writes them in the frame memory 24A.

Conventionally, input and decoding of the I ₂ picture, the four P pictures, the (I ₂ ) picture, and the (B ₁ ) picture to the decoder 23A are performed according to the slow reproduction sequence in the reverse direction. Therefore, as already described as a problem, the delay time until the output by the slow playback is actually obtained from the 1 / 2-speed slow command becomes long according to the slow playback speed, and the responsiveness is poor.

  Even when a plurality of decoders are used, the playback control method according to the embodiment of the present invention described with reference to FIG. 9 is applied, and for example, the input to the decoder 23A and the decoding at the decoder 23A are performed immediately after the start of playback and the output is output. Pictures not to be performed are previously decoded and written in the frame memory 24A. At this time, the input of the picture to the decoder 23A and the decoding in the decoder 23A are performed in advance according to a normal single-speed playback sequence. In this manner, for example, a picture that is input to the decoder 23A and decoded by the decoder 23A and is not output immediately after the start of playback is decoded in advance, so that, for example, reverse playback is slowed from the start of playback. Even when playback is instructed, slow playback can be started with good responsiveness.

This will be described more specifically with reference to FIG. Note that FIG. 24 and FIG. 23 described above are diagrams in which, for example, “decode”, “output”, and “video output” in FIG. 3 are extracted and simplified. The I ₂ picture, the four P pictures, and the (I ₂ ) picture are input to, for example, the decoder 23A prior to all the B pictures, decoded, and written to the frame memory 24A. The (B ₁ ) picture scheduled to be output first is, of course, input to the decoder 23A and decoded before all the pictures are output.

Therefore, the I ₂ picture, the four P pictures, the (I ₂ ) picture, and the (B ₁ ) picture are input to the decoder 23A in advance and decoded, and for example, slow playback is instructed from the start of playback. In this case, input to the decoder 23A and decoding are performed in accordance with the reverse playback single-speed playback sequence, and the result is written into the frame memory 24A.

Then, input and decoding for each picture (pictures after the B ₀ picture) input to the decoder 23A after the (B ₁ ) picture is performed in accordance with a 1 / 2-speed slow playback sequence in the reverse direction in the decoder 23A. . Since the sequence of 1 / 2-speed slow reproduction in the decoder 23A is the same as the operation already described with reference to FIG. 22, detailed description thereof is omitted to avoid complexity.

  In the above description, an example in which three decoders 23A, 23B, and 23C are mounted on the decoder board 2 has been described. However, this is not limited to this example, and two decoders are mounted on the decoder board 2. Alternatively, when four or more decoders are mounted on the decoder board 2, the same processing can be performed.

  FIG. 25 and FIG. 26 are flowcharts showing display processing of an example of a video stream in a playback apparatus applicable to the present invention. The processing according to this flowchart can be commonly applied to the above-described embodiment of the present invention, the first modification of the embodiment, and the second modification of the embodiment. Here, in order to avoid complexity, it is assumed that only one decoder 23 is mounted on the decoder board 2 as in the embodiment or a modification of the embodiment. In FIG. 25 and FIG. 26, the symbols “A” and “B” indicate that the processing shifts to the corresponding symbols between FIG. 25 and FIG.

  For example, in a standby state of the playback device, the CPU 11 reads one to a plurality of GOP elementary streams from the hard disk drive 14 (step S10). This elementary stream is supplied to the decoder board 2 via the south bridge 13 and the PCI bus 15, and is transferred to the memory 21 via the PCI bridge 20 and stored in the decoder board 2 (step S11). When a predetermined amount of elementary stream is read from the hard disk drive 14 and the transfer of the read stream to the memory 21 is completed, the CPU 11 notifies the CPU 25 of the transfer completion (step S12). .

  When the CPU 25 receives the transfer completion notification from the CPU 11, it prepares to decode the elementary stream, for example, initialization of the decoder 23. Then, the CPU 25 notifies the CPU 11 that the preparation for decoding has been completed (step S13). In step S14, for example, in response to an operation of the computer device 1 by the user, an instruction to start decoding is transmitted from the CPU 11 to the CPU 25.

  This decoding start command includes playback direction information indicating whether to perform forward playback or reverse playback, and speed information indicating the playback speed. The speed information indicates normal 1 × speed playback with a value of “1”, slow playback when the value is less than “1” and “0” or more, and in particular when the speed information value is “0”, it indicates pause playback. A negative value may be allowed as the speed information, and if the speed information is a negative value, reverse playback may be indicated. Information on whether or not to perform step reproduction is also transmitted in the decoding start command. In the following, it is assumed that the step reproduction is a reproduction speed of 1 × or less.

  When the CPU 25 receives the decoding start command from the CPU 11, the picture and the display picture to be input to the decoder 23 according to the reproduction direction with respect to the data for 1 GOP in the elementary stream stored in the memory 21. Is scheduled (step S15). For example, in the case of forward reproduction, scheduling is performed as shown in FIG. 3, and the order in which pictures are read from the memory 21 and a display start command for the decoder 23 are determined.

  In the next step S16 (FIG. 26), the CPU 25 determines whether or not playback at a playback speed less than 1 × is instructed based on the speed information. If it is determined that playback at a playback speed less than 1 × is instructed, the process proceeds to step S17, and whether the picture currently input to the decoder 23 is a picture to be decoded in advance. It is determined whether or not.

For example, if the arrangement of pictures input to the decoder 23 is arrangement (1), it is assumed that the I ₂ picture, the four P pictures, and the B ₀ picture are pictures that are decoded in advance. If the picture array is array (2), it is assumed that the I ₂ picture, the four P pictures, and the B ₁ picture in the previous GOP in the output order are the pictures that are decoded in advance. If the picture array input to the decoder 23 is a standard picture array, the I ₂ picture, the B ₀ picture, and the B ₁ picture are pictures that are decoded in advance. If it is determined in step S17 that the input picture is a picture to be decoded in advance, the process proceeds to step S20.

  On the other hand, if it is determined in step S17 that the input picture is not a picture to be decoded in advance, the process proceeds to step S18. In step S18, the CPU 25 calculates the frame update timing based on the speed information, and in the next step S19, it is determined whether or not the present is the frame update timing. For example, as already described with reference to FIGS. 7 and 8, when 1 / 2-speed slow playback is instructed, frame update is performed every frame synchronization signal period from the timing of the next frame synchronization signal. Made. If pause playback is instructed, the frame is not updated from the timing of the next frame synchronization signal. Furthermore, when step reproduction is instructed, the frame is updated at the timing of the next frame synchronization signal.

  If it is determined in step S19 that the current time is not the update timing, the process proceeds to step S25 described later. If it is determined that the current timing is the update timing, the process proceeds to step S20. Note that the first frame is considered to be the update timing.

  In step S20, the CPU 25 transfers a decoding start command to the decoder 23 based on the schedule obtained in step S15. At the same time, the CPU 25 reads the elementary stream stored in the memory 21 in units of pictures based on the schedule obtained in step S15 and supplies the read stream to the decoder 23. Based on the transferred decoding start instruction, the decoder 23 decodes the supplied picture using the decoded picture written in the frame memory 24 as necessary. The decoded picture is written into a writable or overwritable area of the frame memory 24 (step S21).

  In step S22, a display start command is transferred from the CPU 25 to the decoder 23 based on the schedule obtained in step S15. In step S23, one frame is displayed (output) in response to the display start command.

  When it is determined in step S17 described above that the input picture is a picture to be decoded in advance, the process proceeds to step S20, and the process related to the frame update timing in steps S18 and S19 is performed. Since it is canceled, the speed information is automatically set to a value indicating 1 × speed. However, the frame update timing may be calculated by setting the value of the speed information to “1” in step S18 when it is determined that the input picture is a picture to be decoded in advance.

  In step S24, it is determined whether or not display (output) for one GOP has been performed. If it is determined that one GOP worth of display (output) has not been performed, the process proceeds to step S25, where it is determined whether the data has been output to the end. If it is determined that the data has been output to the end, a series of reproduction operations are terminated. If it is determined in step S25 that the data has not been output to the end, the process returns to step S16.

  On the other hand, if it is determined in step S24 that display (output) for 1 GOP has been performed, the process proceeds to step S26, and it is determined whether or not the data has been output to the end. If it is determined that the data has been output to the end, a series of reproduction operations are terminated. If it is determined in step S26 that data has not been output to the end, the process proceeds to step S27, and the CPU 25 notifies the CPU 11 that display (output) for one GOP has been completed. .

  In the next step S28, the CPU 11 reads from the hard disk drive 14 an elementary stream corresponding to 1 GOP required next to the elementary stream read from the hard disk drive 14 in step S10 described above. At this time, if sufficient data is already stored in the memory 21, the process of step S28 can be omitted. The read elementary stream of 1 GOP is transferred to the memory 21 and stored (step S29). When the transfer of the read stream to the memory 21 is completed, the transfer completion is notified from the CPU 11 to the CPU 25 (step S30).

  When the CPU 25 receives the transfer completion notification from the CPU 11, it prepares to decode the elementary stream, for example, initialization of the decoder 23. Then, the CPU 25 notifies the CPU 11 that the preparation for decoding has been completed (step S31). In step S32, the CPU 25 determines whether the GOP process is necessary. For example, when the user performs an operation for switching the playback direction on the computer apparatus 1, it is necessary to perform scheduling again in units of GOPs. If it is determined that it is necessary, the process proceeds to step S15 and scheduling is performed. If it is determined that the GOP process is not necessary, the process proceeds to step S16.

  In the above description, the embodiment of the present invention, and the first and second modifications of the embodiment have been described so as to be applied to an elementary stream based on the MPEG2 long GOP. This is not limited to this example. For example, the present invention can also be applied to an example of a single GOP in which all pictures are composed of I pictures and 1 GOP = 1 picture. Further, the present invention can be applied not only to the MPEG2 system but also to video streams of other systems.

  In the above description, the playback apparatus applicable to the present invention has been described as being configured by predeterminedly loading the decoder board 2 on which the decoder 23 is mounted on the computer apparatus, but this is not limited to this example. For example, if the CPU 11 is sufficiently fast and the memory 12 has a sufficient capacity, the decoder board 2 is not loaded into the computer apparatus 1 and the reproduction control according to the present invention is performed by software processing on the CPU 11. Is also possible.

  Further, in the above description, the GOP has been described as being composed of I, P, and B pictures. However, this is not limited to this example, and the present invention is applicable to cases where the GOP is composed of only I pictures and B pictures. Can be applied. In this case, for example, it is conceivable that the I picture and the B picture scheduled to be output first are pictures that are input in advance to the decoder 23 and decoded.

  It should be noted that, for a video stream stored in the hard disk drive 14, a flag group for reading indicating whether the data is valid as data read from the hard disk drive 14, and whether it is valid in decoding scheduling. A decoding flag group, a display flag group indicating whether or not the scheduling of displaying the decoded data is effective as metadata corresponding to the video stream, and a series of flag groups It is also possible to manage the scheduling in the decoder 23 by automatically updating in accordance with the reproduction speed and the reproduction direction.

  At this time, it is also possible to manage a series of scheduling and flag group update information used for variable-speed playback processing such as past slow playback as separate scheduling metadata (history information). It may be described as syntax in the video stream, or may be recorded separately on the hard disk drive 14 as a recording medium.

  It is also possible to manage the number of decoders mounted on the decoder board 2, the number of banks of the frame memory 24, the decoder ID, and the like as metadata (configuration history information). Furthermore, it is also possible to manage the playback speed, playback direction, etc. as metadata (playback history information). At this time, these metadata may be described as syntax in the video stream as needed, or may be separately recorded on the hard disk drive 14 as a recording medium.

  By referring to such metadata (history information), it is possible to reuse scheduling processing executed in the past, and to execute it more accurately and at high speed. Such metadata may be managed by an external device as a database, for example.

  In the above-described embodiment, the first modification of the embodiment, and the second modification of the embodiment, the decoder 23 (in the second modification of the embodiment, the decoder 23A, 23B and 23C, in the following, an example in which only one decoder 23 is mounted on the decoder board 2 of the embodiment in order to avoid complexity will be described) The present invention can also be applied to the case where the recorded video stream is not completely decoded (decoded until halfway).

  Specifically, for example, when the decoder 23 performs only decoding and inverse quantization on a variable length code and does not execute inverse DCT (Discrete Cosine Transform), or performs inverse quantization but performs decoding on a variable length code. The present invention can be applied even when not performing the above. In such a case, for example, the decoder 23 generates, as necessary, history information that indicates to what stage (for example, the inverse quantization stage) the encoding process and the decoding process have been performed, and is incomplete. The data may be output in association with the decrypted data.

  Furthermore, in the above-described embodiment, incompletely encoded data (for example, data that has been subjected to DCT and quantization but not subjected to variable-length encoding processing) is stored in the hard disk drive 14. The history information of the encoding process and the decoding process is stored as necessary, and the decoder 23 decodes the supplied incompletely encoded data based on the control of the CPU 25, and the base The present invention can also be applied to a case where it can be converted into a band signal.

  Specifically, the decoder 23 performs, for example, DCT and quantization, but only inverse DCT transform and inverse quantization are performed on incompletely encoded data that is not subjected to variable-length encoding processing. The present invention can be applied even when the decoding is performed for the variable length code and the variable length code is not executed.

  In such a case, for example, the CPU 25 acquires the history information of the encoding process and the decoding process stored in the hard disk drive 14 in association with the incompletely encoded data via the CPU 11. Based on these pieces of information, the decoder 23 may perform decoding scheduling.

  Furthermore, in the above-described embodiment, the first modification of the embodiment, and the second modification of the embodiment, the hard disk drive 14 includes incompletely encoded data and necessary. Accordingly, history information of the encoding process and the decoding process is stored, and the decoder 23 does not completely decode the supplied incompletely encoded data based on the control of the CPU 25 (intermediate stage). The present invention can also be applied to the case of decoding up to.

  Also in such a case, for example, the CPU 25 acquires the history information of the encoding process and the decoding process stored in the hard disk drive 14 in association with the incompletely encoded data, and these Based on the information, the decoder 23 may be able to schedule decoding. Further, in this case, the decoder 23 may generate the history information of the encoding process and the decoding process as necessary, and output the history information in association with the incompletely decoded data. Good.

  In other words, the present invention is applicable even when the decoder 23 performs partial decoding based on the control of the CPU 25 (executes a part of the decoding processing steps). Obtains the history information of the encoding process and the decoding process stored in the hard disk drive 14 in association with the incompletely encoded data, and based on these information, the decoding scheduling by the decoder 23 The decoder 23 may generate encoding and decoding history information as necessary, and output the information in association with incompletely decoded data.

  Further, the history information of the encoding and decoding processes may be further recorded in the hard disk drive 14 in association with the video stream, and the CPU 25 decodes the compression-encoded video stream. Scheduling may be performed based on history information of encoding processing and decoding processing. Further, even when the decoder 23 can decode the compression-encoded video stream and convert it into a baseband signal based on the control of the CPU 25, the history information of encoding and decoding is necessary. May be generated in response to the baseband signal and output in association with the baseband signal.

  In the second modification of the embodiment described above, one or more decoders 23 are mounted on the decoder board 2 and the decoder board 2 is loaded into the computer apparatus 1 for use. The present invention is also applicable when the decoder is configured as an independent device.

  At this time, the decoder configured as an independent device receives the compressed and encoded video stream, decodes it, and displays or outputs it. Received supply, partially decoded until halfway stage, output to the outside along with encoding and decoding history information, received supply of partially encoded video stream, performs decoding process, base It is converted into a band signal and output to the outside, or it is supplied with a partially encoded video stream, partially decoded to an intermediate stage, and output to the outside together with encoding and decoding history information It may be.

  Furthermore, in the above-described embodiment, the first modification of the embodiment, and the second modification of the embodiment, the CPU 11 and the CPU 25 are configured independently of each other. For example, the CPU 11 and the CPU 25 may be configured as one CPU that controls the entire playback device. Even when the CPU 11 and the CPU 25 are configured independently of each other, the CPU 11 and the CPU 25 can be configured in one chip.

  Furthermore, when the CPU 11 and the CPU 25 are configured independently of each other, the CPU 11 executes in the above-described embodiment, the first modification of the embodiment, and the second modification of the embodiment. At least a part of the processing may be executed by the CPU 25, for example, in a time division manner, or at least a part of the processing executed by the CPU 25 may be executed by the CPU 11, for example, in a time division manner. . That is, the CPU 11 and the CPU 25 can use processors capable of distributed processing.

  Further, for example, the playback apparatus is configured to be connectable to a network such as a LAN (Local Area Network), and the above-described embodiment, the first modification of the embodiment, and the second modification of the embodiment. In the example, at least a part of the processing executed by the CPU 11 and / or the CPU 25 may be executed on the CPU of another device connected via the network.

  Similarly, in the above-described embodiment, the first modification of the embodiment, and the second modification of the embodiment, the memory 21 and the frame memory 24 are configured independently of each other. However, this is not limited to this example, and each of the memory 21 and the frame memory 24 can be configured by different areas of one memory.

  Furthermore, in the above-described embodiment, the first modification of the embodiment, and the second modification of the embodiment, the hard disk drive 14 and the decoder 23 (the second modification of the embodiment) In the above description, the hard disk drive 14, the decoders 23A, 23B and 23C, and the selector 27) are connected via the PCI bridge 20 and the PCI bus 15, respectively, and are integrally configured as a playback device. The invention is not limited to this example. For example, the present invention can be applied to a case where some of these components are connected from the outside by wired or wireless, or when these components are connected to each other in various connection forms. it can.

  Furthermore, in the above-described embodiment, the first modification example of the embodiment, and the second modification example of the embodiment, the video stream has been described as being stored in the hard disk drive 14. This is not limited to this example. That is, the present invention can also be applied to a case where reproduction processing is performed on video streams recorded on various recording media such as an optical disk, a magneto-optical disk, a semiconductor memory, and a magnetic disk.

  Furthermore, in the above-described embodiment, the first modification of the embodiment, and the second modification of the embodiment, the CPU 25, the memory 21, the decoder 23, and the frame memory 24 (one embodiment) In the second modification, the CPU 25, the memory 21, the decoders 23A, 23B and 23C, the frame memories 24A, 24B and 24C, and the selector 27) are connected to the same expansion board (for example, PCI). An example of mounting on a board or a PCI-Express board) has been described, but this is not limited to this example. For example, when the data transfer speed between expansion boards is sufficiently high by a technique such as PCI-Express, these components may be mounted on different expansion boards.

  In this specification, the system refers to a logical collection of a plurality of devices, and it does not matter whether the devices of each configuration are in the same housing.

It is a block diagram which shows roughly the structure of an example reproducing | regenerating apparatus applicable to the 1st form of this invention. It is a block diagram which shows the structure of an example of a decoder. It is an approximate line figure showing a rough sequence of input / output and internal processing in a decoder. It is a basic diagram which shows the usage condition of an example of the frame memory at the time of forward reproduction | regeneration. It is a basic diagram which shows the schematic sequence of the input / output at the time of reverse reproduction | regeneration in a decoder, and an internal process. It is a basic diagram which shows the usage condition of an example of the frame memory at the time of reverse reproduction | regeneration. It is a basic diagram which shows a sequence of an example in the case of performing pause reproduction | regeneration, step reproduction | regeneration, and 1/2 times speed slow reproduction | regeneration at the time of forward reproduction | regeneration. It is a basic diagram which shows the example in the case of performing slow reproduction from the time of a reproduction | regeneration start by the conventional method. It is a basic diagram which shows the example in the case of performing slow reproduction | regeneration from the time of a reproduction | regeneration start by the method by one Embodiment of this invention. It is a basic diagram which shows a sequence of an example in the case of performing pause reproduction | regeneration, step reproduction | regeneration, and 1/2 times speed slow reproduction | regeneration at the time of reverse reproduction | regeneration. It is a basic diagram which shows the example in the case of performing slow reproduction from the time of reverse reproduction start by the conventional method. It is a basic diagram which shows the example in the case of performing slow reproduction | regeneration from the time of reverse reproduction | regeneration start by the method by one Embodiment of this invention. It is a figure for demonstrating operation | movement of each part of a decoder at the time of 1x forward reproduction by a standard arrangement | sequence. It is a basic diagram which shows a sequence of an example in the case of performing pause reproduction | regeneration at the time of forward reproduction | regeneration, step reproduction | regeneration, and 1/2 time speed slow reproduction | regeneration by a standard arrangement | sequence. It is a basic diagram which shows the example in the case of performing slow reproduction from the time of a reproduction | regeneration start by the method by the 1st modification of one Embodiment of this invention. It is a block diagram which shows the structure of an example reproducing | regenerating apparatus in case three decoders are mounted in a decoder board. It is a basic diagram which shows the rough sequence of the input / output at the time of forward reproduction | regeneration, and an internal process at the time of using three decoders. It is a basic diagram which shows an example sequence in the case of performing pause reproduction | regeneration, step reproduction | regeneration, and 1/2 times speed slow reproduction | regeneration at the time of forward reproduction | regeneration at the time of using three decoders. It is a basic diagram which shows the example in the case of performing slow reproduction | regeneration from the time of a reproduction | regeneration start by a conventional method using three decoders. It is a basic diagram which shows the example in the case of performing slow reproduction | regeneration from the time of a reproduction | regeneration by the method by the 2nd modification of one Embodiment of this invention using three decoders. It is a basic diagram which shows the schematic sequence of the input / output at the time of reverse reproduction | regeneration, and an internal process at the time of using three decoders. It is a basic diagram which shows a sequence of an example in the case of performing a pause reproduction | regeneration, step reproduction | regeneration, and 1/2 times speed slow reproduction | regeneration at the time of reverse reproduction | regeneration at the time of using three decoders. It is a basic diagram which shows the example in the case of performing slow reproduction | regeneration from the time of a reverse reproduction | regeneration start by the conventional method using three decoders. It is a basic diagram which shows the example in the case of using 3 decoders and performing slow reproduction | regeneration from the time of reverse reproduction | regeneration start by the method by the 2nd modification of one Embodiment of this invention. It is a flowchart which shows the display process of an example of the video stream in the reproducing | regenerating apparatus applicable to this invention. It is a flowchart which shows the display process of an example of the video stream in the reproducing | regenerating apparatus applicable to this invention. FIG. 10 is a diagram for schematically explaining decoding of an MPEG2 elementary stream according to a conventional technique. FIG. 2 is a block diagram schematically showing a configuration of an example computer apparatus for decoding a video stream that has been compression-encoded using the MPEG2 system or the like. It is a basic diagram for demonstrating slow reproduction by a prior art.

Explanation of symbols

1 Computer Device 2 Decoder Board 11 CPU
14 Hard disk drive 20 PCI bridge 21 Memory 23 Decoder 24 Frame memory 25 CPU

Claims (39)

In a decoding device for decoding and outputting compressed and encoded video data,
Decoding means for decoding and outputting input video data;
The input of the video data to the decoding means, and control means for controlling the decoding of the input video data based on a predetermined sequence,
The control means inputs an input to the decoding means of a preceding frame that is input before the timing of the first output frame from the decoding means when a playback speed less than 1 × speed is instructed; A decoding apparatus, characterized in that said decoding by said decoding means for a preceding frame is controlled to be performed based on a 1 × speed playback sequence. The decoding device according to claim 1, wherein
The video data is compression encoded using inter-frame compression,
The preceding frame includes at least one complete frame that can be decoded by itself, and a forward reference frame that is decoded using a frame that is temporally positioned in the display order. Device. The decoding device according to claim 1, wherein
The decoding apparatus according to claim 1, wherein the preceding frame includes a frame output first. The decoding device according to claim 1, wherein
The video data is compression encoded using inter-frame compression,
The decoding apparatus according to claim 1, wherein the preceding frame includes at least one complete frame that can be decoded by itself. The decoding device according to claim 1, wherein
The video data includes at least one complete frame that can be decoded by itself using inter-frame compression, and a forward reference frame that is decoded using a frame that is positioned temporally earlier in display order; Compression encoding is performed in units of groups of bi-directional reference frames that are decoded with reference to frames that are temporally forward and backward in display order, and the decoding is performed in units of the groups. A decoding device characterized by the above. The decoding device according to claim 5, wherein
The decoding apparatus according to claim 1, wherein the bidirectional reference frame in the group is input to the decoding means after the completion frame and the forward reference frame in the group. The decoding device according to claim 6, wherein
A storage means for temporarily storing the input video data;
Decoding, wherein when reading the video data from the storage means, the complete frame and the forward reference frame in the group are read, and then the bidirectional reference frame in the group is read. apparatus. The decoding device according to claim 1, wherein
A plurality of decoding means,
The decoding device according to claim 1, wherein the control means sequentially inputs the video data to the plurality of decoding means for each group unit consisting of predetermined one or a plurality of frames. The decoding device according to claim 8,
The video data is compression encoded using inter-frame compression,
The group includes at least one complete frame that can be decoded by itself, a forward reference frame that is decoded using a frame that is temporally earlier in display order, A decoding apparatus comprising: a bi-directional reference frame that is decoded with reference to a frame located behind. The decoding device according to claim 9, wherein
The decoding apparatus according to claim 1, wherein the group is configured such that decoding is completed within the group. In a decoding method for decoding and outputting compression-encoded video data,
A decoding step of decoding and outputting the input video data;
When a playback speed less than 1 × speed is instructed, an input to the decoding step of the preceding frame input before the timing of the first output frame from the decoding step; A decoding method characterized in that the decoding in the decoding step is controlled to be performed based on a sequence of 1 × speed reproduction. In a decoding program for causing a computer device to execute a decoding method for decoding and outputting compression-encoded video data,
The decoding method is
A decoding step of decoding and outputting the input video data;
When a playback speed less than 1 × speed is instructed, an input to the decoding step of the preceding frame input before the timing of the first output frame from the decoding step; A decoding program characterized in that the decoding in the decoding step is controlled to be performed based on a sequence of 1 × speed reproduction. In a computer-readable recording medium on which a decoding program for causing a computer apparatus to execute a decoding method for decoding and outputting compressed and encoded video data is recorded,
The decoding method is
A decoding step of decoding and outputting the input video data;
When a playback speed less than 1 × speed is instructed, an input to the decoding step of the preceding frame input before the timing of the first output frame from the decoding step; A computer-readable recording medium, wherein the decoding in the decoding step is controlled to be performed based on a sequence of 1 × speed reproduction. In a playback device that decodes and outputs video data that has been compression-encoded and recorded on a recording medium,
A recording medium on which compressed and encoded video data is recorded;
Speed information output means for outputting speed information indicating the playback speed of the video data;
Decoding means for decoding and outputting video data read from the recording medium,
When the playback speed less than 1 × is instructed by the speed information output from the speed information output means, the preceding frame input before the timing of the first output frame from the decoding means A reproduction apparatus characterized in that input to the decoding means and the decoding of the preceding frame by the decoding means are controlled based on a sequence of 1 × speed reproduction. The playback device according to claim 14, wherein
The video data is compression encoded using interframe compression,
The preceding frame includes at least one complete frame that can be decoded by itself, and a forward reference frame that is decoded by using a frame that is temporally preceding in display order. apparatus. The playback device according to claim 14, wherein
The playback apparatus, wherein the preceding frame includes a frame that is output first. The playback device according to claim 14, wherein
The video data is compression encoded using inter-frame compression,
The playback apparatus according to claim 1, wherein the preceding frame includes at least one complete frame that can be decoded by itself. The playback device according to claim 14, wherein
The video data includes at least one complete frame that can be decoded by itself using inter-frame compression, and a forward reference frame that is decoded using a frame that is positioned temporally earlier in display order; Compression encoding is performed in units of groups of bi-directional reference frames that are decoded with reference to frames that are temporally forward and backward in display order, and the decoding is performed in units of the groups. A reproducing apparatus characterized by the above. The playback device according to claim 18, wherein
The reproducing apparatus, wherein the bidirectional reference frame in the group is input to the decoding means after the completion frame and the forward reference frame in the group. The playback device according to claim 19,
A storage means for temporarily storing video data read from the recording medium;
A reproduction apparatus characterized in that, when the video data is read from the storage means, the complete frame and the forward reference frame in the group are read, and then the bidirectional reference frame in the group is read. . The playback device according to claim 14, wherein
A plurality of decoding means,
2. A playback apparatus according to claim 1, wherein the video data is sequentially input to the plurality of decoding means for each group unit consisting of predetermined one or a plurality of frames. The playback device according to claim 21, wherein
The video data is compression encoded using inter-frame compression,
The group includes at least one complete frame that can be decoded by itself, a forward reference frame that is decoded using a frame that is temporally earlier in display order, A playback apparatus comprising: a bi-directional reference frame which is decoded with reference to a frame located behind. The playback device according to claim 22,
The playback apparatus according to claim 1, wherein the group is configured to complete decoding within the group. In a reproduction method for decoding and outputting video data that has been compression-encoded and recorded on a recording medium,
A speed information output step for outputting speed information indicating the playback speed of the video data;
A decoding step of decoding and outputting video data read from a recording medium on which the compressed and encoded video data is recorded,
The preceding frame that is input before the timing of the first frame output from the decoding step when a playback speed less than 1 × speed is instructed by the speed information output from the speed information output step A playback method characterized in that the input to the decoding step and the decoding of the preceding frame in the decoding step are controlled based on a 1 × speed playback sequence. In a playback program for causing a computer device to execute a playback method for decoding and outputting video data compressed and encoded and recorded on a recording medium,
The above playback method is
A speed information output step for outputting speed information indicating the playback speed of the video data;
A decoding step of decoding and outputting video data read from a recording medium on which the compressed and encoded video data is recorded,
The preceding frame that is input before the timing of the first frame output from the decoding step when a playback speed less than 1 × speed is instructed by the speed information output from the speed information output step A reproduction program characterized in that the input to the decoding step and the decoding of the preceding frame in the decoding step are controlled based on a 1 × speed reproduction sequence. In a recording medium readable by a computer apparatus on which a reproduction program for causing a computer apparatus to execute a reproduction method for decoding and outputting video data compressed and encoded and recorded on the recording medium is provided.
The above playback method is
A speed information output step for outputting speed information indicating the playback speed of the video data;
A decoding step of decoding and outputting video data read from a recording medium on which the compressed and encoded video data is recorded,
The preceding frame that is input before the timing of the first frame output from the decoding step when a playback speed less than 1 × speed is instructed by the speed information output from the speed information output step A computer apparatus characterized in that control is performed so that the input to the decoding step and the decoding by the decoding step of the preceding frame are performed based on a sequence of 1 × speed reproduction. A readable recording medium.
In a playback system that decodes and outputs video data that has been compression-encoded and recorded on a recording medium,
A recording medium on which compressed and encoded video data is recorded;
A control device having speed information output means for outputting speed information indicating the playback speed of the video data;
Decoding means for decoding and outputting video data read from the recording medium;
When the playback speed less than 1 × is instructed by the speed information output from the speed information output means, the preceding frame input before the timing of the first output frame from the decoding means And a decoding device having control means for controlling the input to the decoding means and the decoding of the preceding frame by the decoding means based on a sequence of 1 × speed reproduction. Playback system. 28. A playback system according to claim 27.
The video data is compression encoded using inter-frame compression,
The preceding frame includes at least one complete frame that can be decoded by itself, and a forward reference frame that is decoded by using a frame that is temporally preceding in display order. system. 28. A playback system according to claim 27.
The reproduction system according to claim 1, wherein the preceding frame includes a frame output first. 28. A playback system according to claim 27.
The video data is compression encoded using inter-frame compression,
The reproduction system according to claim 1, wherein the preceding frame includes at least one complete frame that can be decoded by itself. 28. A playback system according to claim 27.
The video data includes at least one complete frame that can be decoded by itself using inter-frame compression, and a forward reference frame that is decoded using a frame that is positioned temporally earlier in display order; Compression encoding is performed in units of groups of bi-directional reference frames that are decoded with reference to frames that are temporally forward and backward in display order, and the decoding is performed in units of the groups. A reproduction system characterized by this. 32. A playback system according to claim 31, wherein
The reproduction system according to claim 1, wherein the bi-directional reference frame in the group is input to the decoding means after the completion frame and the forward reference frame in the group. The playback system according to claim 32, wherein
The decoding device further includes storage means for temporarily storing video data read from the recording medium,
A reproduction system characterized in that, when the video data is read from the storage means, the complete frame and the forward reference frame in the group are read, and then the bidirectional reference frame in the group is read. . 28. A playback system according to claim 27.
The decoding device has a plurality of the decoding means,
A reproduction system characterized in that the video data is sequentially input to the plurality of decoding means for each group consisting of predetermined one or a plurality of frames. The playback system of claim 34,
The video data is compression encoded using inter-frame compression,
The group includes at least one complete frame that can be decoded by itself, a forward reference frame that is decoded using a frame that is temporally earlier in display order, A reproduction system comprising a bidirectional reference frame decoded with reference to a frame located behind. 36. A playback system according to claim 35.
The reproduction system according to claim 1, wherein the group is configured such that decoding is completed within the group. In a reproduction method for decoding and outputting video data that has been compression-encoded and recorded on a recording medium,
When the compression-encoded video data is input, the video data has decoding means for decoding and outputting the input video data, and when the playback speed less than 1 × is instructed by the input speed information, The input of the preceding frame input before the timing of the first frame output from the decoding unit to the decoding unit and the decoding of the preceding frame by the decoding unit are performed at 1 × speed reproduction. The video data is read from the recording medium on which the compression-encoded video data is recorded and supplied to the decoding apparatus controlled to be performed based on the sequence, and the playback speed of the video data is indicated. A reproduction method characterized in that the speed information is supplied. In a playback program for causing a computer device to execute a playback method for decoding and outputting video data compressed and encoded and recorded on a recording medium,
The above playback method is
When the compression-encoded video data is input, the video data has decoding means for decoding and outputting the input video data, and when the playback speed less than 1 × is instructed by the input speed information, The input of the preceding frame input before the timing of the first frame output from the decoding unit to the decoding unit and the decoding of the preceding frame by the decoding unit are performed at 1 × speed reproduction. The video data is read from the recording medium on which the compression-encoded video data is recorded and supplied to the decoding apparatus controlled to be performed based on the sequence, and the playback speed of the video data is indicated. A reproduction program characterized in that the speed information is supplied. In a recording medium readable by a computer apparatus on which a reproduction program for causing a computer apparatus to execute a reproduction method for decoding and outputting video data compressed and encoded and recorded on the recording medium is provided.
The above playback method is
When the compression-encoded video data is input, the video data has decoding means for decoding and outputting the input video data, and when the playback speed less than 1 × is instructed by the input speed information, The input of the preceding frame input before the timing of the first frame output from the decoding unit to the decoding unit and the decoding of the preceding frame by the decoding unit are performed at 1 × speed reproduction. The video data is read from the recording medium on which the compression-encoded video data is recorded and supplied to the decoding apparatus controlled to be performed based on the sequence, and the playback speed of the video data is indicated. A computer-readable recording medium characterized by supplying the speed information.

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