JP4216295B2 - バンプ構造およびその形成方法、ならびにそれを用いた半導体装置 - Google Patents
バンプ構造およびその形成方法、ならびにそれを用いた半導体装置 Download PDFInfo
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- JP4216295B2 JP4216295B2 JP2006127813A JP2006127813A JP4216295B2 JP 4216295 B2 JP4216295 B2 JP 4216295B2 JP 2006127813 A JP2006127813 A JP 2006127813A JP 2006127813 A JP2006127813 A JP 2006127813A JP 4216295 B2 JP4216295 B2 JP 4216295B2
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Description
図1(a)は、本発明の第1の実施の形態のバンプ構造の断面図であり、図1(b)はその平面図である。図1(a)(b)に示すように、本実施の形態のバンプ構造では、半導体チップ1上に電極パッド2が備え付けられている。電極パッド2上には圧着ボール3aが備え付けられ、更に圧着ボール3aからループ状のワイヤからなるワイヤループ3bが伸びている。このとき上記ワイヤループ3bは、圧着ボール3aの端部からはみ出るように形成されている。なお、本明細書中にて「圧着ボールの端部からはみ出す」とは、圧着ボールから伸びているワイヤループが、圧着ボール上のみならず、圧着ボールの端部よりも外側にも存在する状態を意図する。
次いで、第6工程では、ワイヤ55をバンプ構造57から切断する。ワイヤ55の切断方法は、特に限定されず、適宜公知の方法を用いることができる。例えば、クランパ(図示せず)とキャピラリ54とを共に上昇させ、この上昇途中にてクランパを閉じることによって、ワイヤ55をバンプ構造57の根元から切断してもよい。
図2(a)は、本発明の第2の実施の形態のバンプ構造の断面図であり、図2(b)はその平面図である。図2(a)(b)に示すように、本実施の形態のバンプ構造では、半導体チップ11上に電極パッド12が備え付けられている。電極パッド12上には圧着ボール13aが備え付けられ、更に圧着ボール13aからループ状のワイヤからなるワイヤループ13bが伸びている。このとき上記ワイヤループ13bは、圧着ボール13a上からはみ出るように形成されている。
図3は、本発明の第3の実施の形態のバンプ構造の平面図である。図3に示すように、本実施の形態のバンプ構造では、半導体チップ(図示せず)上に電極パッド22が備え付けられている。電極パッド22上には圧着ボール23aが備え付けられ、更に圧着ボール23aからループ状のワイヤからなる複数のワイヤループ23bが伸びている。つまり、1つの圧着ボール23a上に複数のワイヤループ23bが形成されている。なお、本実施の形態のバンプ構造は、実施の形態1にて説明したワイヤループ3bを複数有するものでもよいし、実施の形態2にて説明したワイヤループ13bを複数有するものであってもよい。あるいは、実施の形態1にて説明したワイヤループ3bと実施の形態2にて説明したワイヤループ13bとの両方を有するものであってもよい。また、本実施の形態のバンプ構造は、1つの圧着ボール23a上に複数のワイヤループ23bが形成されているものであればよく、圧着ボール23a上に形成されるワイヤループ23bの数は特に限定されない。また、実施の形態1にて説明したワイヤループ3bと実施の形態2にて説明したワイヤループ13bとの両方を有する場合、それぞれのワイヤループの数も、特に限定されない。また、上記ワイヤループ23bのそれぞれは、圧着ボール23aの端部からはみ出るように形成されている。
上記長さ25は、ワイヤループ23bが圧着ボール23aの端部からはみ出す長さであればよく、特に限定されない。また、それぞれのワイヤループ23bの長さ25は、それぞれのワイヤループ23bに応じて設定すればよい。つまり、それぞれのワイヤループ23bの長さ25は、異なる長さであってもよいし、同じ長さであってもよく、特に限定されない。また、それぞれのワイヤループ23bの角度26も、それぞれのワイヤループ23bに応じて設定すればよく、特に限定されない。なお、上記角度26は、それぞれのワイヤループ23bが異なる方向に向かって伸びるように設定されていることが好ましい。それぞれのワイヤループ23bの長さ25は、電極パッド22と、当該電極パッド22を接続させるべき各接続パッド(図示せず)とを接続させ得る長さであればよく、特に限定されない。また、それぞれのワイヤループ23bの角度26も、電極パッド22と、当該電極パッド22を接続させるべき各接続パッド(図示せず)とを接続させ得る角度であればよく特に限定されない。
本発明の半導体装置は、実施の形態1〜実施の形態3において説明したバンプ構造を用いてフリップチップ接続した半導体装置である。図6(a)〜図6(d)に、本発明の半導体装置を示す。図6(a)は、本発明の半導体装置の平面図であり、図6(b)は、図6(a)に示すX1−Y1部分の断面図である。また、図6(c)は、図6(a)のX2−Y2部分の断面図である。また、図6(d)は、図6(a)に示すX3−Y3部分の断面図である。
82・102・202 電極パッド
87・207 接続パッド
3a・13a・23a・53a 圧着ボール
63a・83a・117a 圧着ボール
3b・13b・23b・53b ワイヤループ
63b・83b・117b ワイヤループ
4・14・57・67・84 バンプ構造
118・218 バンプ構造
91・211 ベース基板
56・66 ボール
14・54・64・114 キャピラリ
Claims (6)
- 電極パッド上に設けられる圧着ボールと該圧着ボール上に設けられる複数のワイヤとから構成されるバンプ構造において、
該複数のワイヤは、いずれも該電極パッドの端部から側方に、はみ出すように形成されたループ状の形状を有するワイヤループからなっていると共に、
該ワイヤループは、ループ状のワイヤによって囲まれて形成される平面が、前記電極パッドの表面に対して直交するように形成されているか、または前記電極パッドの表面面に対して略平行に形成されているかのうち少なくともいずれか一方であることを特徴とするバンプ構造。 - 請求項1に記載のバンプ構造を備える半導体装置であって、
半導体チップに形成された電極パッドとベース基板に形成された接続パッドとが、該バンプ構造を介してフリップチップ接続されていることを特徴とする半導体装置。 - 前記バンプ構造が、前記半導体チップのコーナー部に位置する電極パッド上に形成されていることを特徴とする請求項2に記載の半導体装置。
- キャピラリに通したワイヤの先端にボールを形成し、該キャピラリを下降させて該ボールを電極パッドに押圧して形成した圧着ボールを該電極パッドに固着する第1工程と、
該キャピラリを上昇および横方向へ移動させて、該キャピラリの先端部が、該電極パッドの端部から側方に、はみ出すように位置させる第2工程と、
該キャピラリの先端部が、該圧着ボールを押圧しないように該キャピラリを下降させる第3工程と、
該キャピラリを上昇、および第2工程における横方向への移動とは反対の横方向に移動させる第4工程と、
該キャピラリを下降させて該ワイヤを該圧着ボールに押圧して固着させ、ループ状のワイヤからなるワイヤループを該圧着ボール上に形成する第5工程と、
該ワイヤを該ワイヤループから切断する第6工程を含むことを特徴とするバンプ構造の形成方法。 - 前記電極パッドの表面を規定する方向をX軸方向およびY軸方向とし、該表面に垂直な方向をZ軸方向とした場合、
前記キャピラリの横方向への移動が、X軸方向またはY軸方向への移動のみからなることを特徴とする請求項4に記載のバンプ構造の形成方法。 - 前記電極パッドの表面を規定する方向をX軸方向およびY軸方向とし、該表面に垂直な方向をZ軸方向とした場合、
前記キャピラリの横方向への移動が、X軸方向およびY軸方向への移動からなることを特徴とする請求項4に記載のバンプ構造の形成方法。
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JP2006127813A JP4216295B2 (ja) | 2006-05-01 | 2006-05-01 | バンプ構造およびその形成方法、ならびにそれを用いた半導体装置 |
US11/790,143 US7683484B2 (en) | 2006-05-01 | 2007-04-24 | Bump structure, method of forming bump structure, and semiconductor apparatus using the same |
TW096115056A TWI341566B (en) | 2006-05-01 | 2007-04-27 | Bump structure, method of forming bump structure, and semiconductor apparatus using the same |
KR1020070042092A KR100884520B1 (ko) | 2006-05-01 | 2007-04-30 | 범프 구조, 그 형성 방법, 및 그것을 이용한 반도체 장치 |
CNA200710102380XA CN101068012A (zh) | 2006-05-01 | 2007-04-30 | 凸点结构及其形成方法和使用该凸点结构的半导体器件 |
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JP2006127813A JP4216295B2 (ja) | 2006-05-01 | 2006-05-01 | バンプ構造およびその形成方法、ならびにそれを用いた半導体装置 |
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JP (1) | JP4216295B2 (ja) |
KR (1) | KR100884520B1 (ja) |
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TWI384603B (zh) | 2009-02-17 | 2013-02-01 | Advanced Semiconductor Eng | 基板結構及應用其之封裝結構 |
US8008785B2 (en) | 2009-12-22 | 2011-08-30 | Tessera Research Llc | Microelectronic assembly with joined bond elements having lowered inductance |
US9082763B2 (en) * | 2012-03-15 | 2015-07-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Joint structure for substrates and methods of forming |
KR101977391B1 (ko) | 2018-05-31 | 2019-08-28 | 주식회사 동부아이씨티 | 열영상 기반의 교통 신호 제어 방법 및 장치 |
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JPH0429389A (ja) | 1990-05-24 | 1992-01-31 | Hitachi Chem Co Ltd | フレキシブルプリント配線板 |
JPH0529389A (ja) | 1991-07-22 | 1993-02-05 | Sharp Corp | 半導体素子の接続構造 |
JP3259377B2 (ja) | 1992-11-06 | 2002-02-25 | ソニー株式会社 | 半導体装置 |
JP2735022B2 (ja) | 1995-03-22 | 1998-04-02 | 日本電気株式会社 | バンプ製造方法 |
US5842628A (en) * | 1995-04-10 | 1998-12-01 | Fujitsu Limited | Wire bonding method, semiconductor device, capillary for wire bonding and ball bump forming method |
US6225143B1 (en) * | 1998-06-03 | 2001-05-01 | Lsi Logic Corporation | Flip-chip integrated circuit routing to I/O devices |
JP2000311915A (ja) | 1998-10-14 | 2000-11-07 | Texas Instr Inc <Ti> | 半導体デバイス及びボンディング方法 |
JP2001176908A (ja) | 1999-12-17 | 2001-06-29 | Matsushita Electronics Industry Corp | 半導体装置の製造方法 |
JP2001189338A (ja) | 1999-12-28 | 2001-07-10 | Fujitsu Ltd | 半導体装置、半導体装置の製造方法及び試験方法 |
JP2002076048A (ja) | 2000-09-05 | 2002-03-15 | Sony Corp | フリップチップ接続によるバンプの配置方法 |
JP3913134B2 (ja) * | 2002-08-08 | 2007-05-09 | 株式会社カイジョー | バンプの形成方法及びバンプ |
JP2002329742A (ja) | 2001-05-07 | 2002-11-15 | Mitsubishi Electric Corp | 半導体装置 |
US7229906B2 (en) * | 2002-09-19 | 2007-06-12 | Kulicke And Soffa Industries, Inc. | Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine |
TWI221664B (en) * | 2002-11-07 | 2004-10-01 | Via Tech Inc | Structure of chip package and process thereof |
JP2004172477A (ja) * | 2002-11-21 | 2004-06-17 | Kaijo Corp | ワイヤループ形状、そのワイヤループ形状を備えた半導体装置、ワイヤボンディング方法及び半導体製造装置 |
JP3854232B2 (ja) * | 2003-02-17 | 2006-12-06 | 株式会社新川 | バンプ形成方法及びワイヤボンディング方法 |
US6815836B2 (en) * | 2003-03-24 | 2004-11-09 | Texas Instruments Incorporated | Wire bonding for thin semiconductor package |
US20050133928A1 (en) * | 2003-12-19 | 2005-06-23 | Howard Gregory E. | Wire loop grid array package |
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- 2007-04-30 CN CNA200710102380XA patent/CN101068012A/zh active Pending
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KR20070106935A (ko) | 2007-11-06 |
US20070252272A1 (en) | 2007-11-01 |
JP2007300000A (ja) | 2007-11-15 |
TWI341566B (en) | 2011-05-01 |
TW200809993A (en) | 2008-02-16 |
US7683484B2 (en) | 2010-03-23 |
CN101068012A (zh) | 2007-11-07 |
KR100884520B1 (ko) | 2009-02-18 |
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