JP4215424B2 - Manufacturing method of membrane sensor array and membrane sensor array - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a membrane sensor array according to the superordinate concept of claim 1 or 5 and a membrane sensor array according to the superordinate concept of claim 6.
[0002]
[Prior art]
A method of manufacturing a membrane sensor having a semiconductor material support and having at least one flat membrane region as a support for a sensor layer on the support is already known. If the membrane sensor array has a plurality of flat membrane regions, the membrane regions are more regular with a web of material having a clearly improved thermal conductivity compared to the membrane and the lateral perimeter of the web. Are insulated from each other.
[0003]
Membrane sensors currently on the market are often realized as thin films. For this purpose, a layer system having a thickness of several tens of nm to several μm is deposited on the support substrate, and then the support substrate is removed in a predetermined region in order to obtain a self-supporting membrane region. The sensor element is then placed in the center of the membrane, for example by a self-supporting arrangement of the membrane, which is insulated from the surrounding support substrate, which is preferred for temperature and flow sensors.
[0004]
There are two ways to expose the membrane.
[0005]
1. Surface micromechanics (OMM) using a sacrificial layer that is generally coated on the surface of a support substrate before depositing the membrane. The sacrificial layer is later removed from the surface of the sensor by a melt opening in the membrane, resulting in a self-supporting structure. This surface micromechanical process is relatively expensive due to the need for a separate sacrificial layer.
[0006]
2. Bulk micromechanics by exposing the membrane from the backside of the support substrate by an etching process, i.e. by etching the opening through a full thickness wafer, for example.
[0007]
A sensor array is required for many uses. For this purpose, a plurality of the same sensors are arranged linearly in parallel or two-dimensionally. If a temperature sensor is used, it must be separated from one another by a heat sink to allow spatial resolution of the measurement signal.
[0008]
There are various possibilities for producing a heat sink. A layer of good heat conductive material is deposited on the surface of the membrane and structured, and the remaining structure of good heat conductive material is used as a heat sink.
[0009]
However, the membrane can also be exposed using a bulk micromechanic process so that a web of bulk material remains between the individual membrane regions. In the case of a bulk micromechanical membrane sensor, the back membrane is generally exposed by anisotropic etching, for example, using KOH (potassium hydroxide). In this case, etching requires significantly more space on the backside of the substrate than is necessary for the original membrane structure, despite its anisotropy. This limits the integration density in this method.
[0010]
[Problems to be solved by the invention]
The object of the present invention is to reduce the manufacturing cost of the membrane sensor array, in particular to provide a membrane sensor array with an improved integration density, which likewise enables a reduction of the manufacturing cost.
[0011]
[Means for Solving the Problems]
The object is solved by the method according to claim 1 or 5 and the membrane sensor according to claim 6.
[0012]
According to the present invention, a plurality of flat membrane regions are first arranged on a semiconductor material support as a support layer of a sensor element, and the flat membrane regions are clearly compared with the membrane region and the lateral peripheral portion of the web. We start with a method of manufacturing a membrane sensor array with a semiconductor material support that is insulated from one another by a web of material with improved thermal conductivity. The term membrane region is understood within the scope of the present invention not only to be a self-supporting layer, but in the simplest case to be a single layer placed in a volume that is less thermally conductive than the web. The core of the present invention is to maintain the masking for the next step of forming the porous semiconductor material at the position where the web is formed for heat insulation on the semiconductor material support, and to protect the semiconductor material not protected by the masking. A membrane region is produced by making the substrate porous and coating a continuous membrane layer on the semiconductor material support or the porous region, for example. In this way, it is possible to achieve a high integration density of the membrane sensor array in which the individual sensors are insulated to a sufficient extent. In this case, the knowledge that a porous semiconductor material can be produced with a relatively fine structure by appropriate masking is utilized. This makes it possible to produce correspondingly fine webs that can be arranged closely in parallel accordingly, which in general allows for a high density of array sensors. Insulation occurs when the remaining semiconductor web is removed by the porous and semiconductive material as compared to the porous semiconducting material or, as will be described in detail below, possibly by gas filling. It is obtained by having a clearly higher thermal conductivity than a hollow having.
[0013]
In a particularly advantageous embodiment of the invention, it is advantageous to use a stable layer, for example silicon oxide, silicon nitride or silicon carbide or a combination thereof, for masking, in producing a porous semiconductor material. It is. This is a relatively simple possibility of masking, in which a web-shaped radiator can be realized without protruding areas after further removal of the masking layer, based on an under-etching process. However, this method cannot form a self-supporting web. That is, the web always remains bonded to the bulk material of the semiconductor material support.
[0014]
In order to manufacture a heat sink in the form of a free-standing web having a defined width and height, the semiconductor material support has a predetermined depth as a mask at the position where the web is formed for thermal insulation. It is proposed to maintain a suitable doping part and to make the semiconductor material not assigned by the doping part porous in the peripheral part of the web.
[0015]
The porous semiconductor region is preferably removed by etching after covering the membrane region. In this way, a particularly self-supporting web structure is formed when the semiconductor region surrounding the web in a continuous bath is made porous. A self-supporting web is sufficient to provide a heat sink that is sufficient for favorable thermal insulation. In this case, this method has the advantage that no additional sacrificial layer or other metal layer, for example forming a heat sink, is required. Rather, the base of the membrane sensor array below the membrane region can be formed entirely from the semiconductor material of the support, for example in the form of a continuous membrane layer.
[0016]
In the case of a method known per se for producing porous silicon, an electrochemical reaction between hydrofluoric acid and silicon is generally used, and in this case, a sponge-like structure is formed in the silicon. For this purpose, the silicon semiconductor support (generally a silicon wafer) must be connected to the anode with respect to the hydrofluoric acid electrolyte. Porous silicon is produced by partial etching to said depth, for example by electrochemical etching (anodization) of silicon in a mixture of hydrofluoric acid / ethanol. In order to etch silicon, defective electrons (holes) are required at the interface between the silicon and the electrolyte, which is supplied by a flowing current. If the current density is less than the critical current density j _{KRIT, the} holes are diffused by the electric field applied in the depressions present on the surface, where advantageous etching takes place. In the case of p-doped silicon, for example, holes can no longer penetrate into this region due to quantum effects, and the region between the recesses is etched laterally to a minimum thickness until the etching process stops. In this way, a sponge-like skeleton structure consisting of silicon and free-etched holes is produced. Since the etching process is performed only on the hole tip region when forming the skeleton structure, the already etched silicon sponge structure is maintained. As a result, the hole diameter in the already etched region remains substantially unchanged. The pore size depends on the concentration of HF in hydrofluoric acid, doping and current density, and may be several nanometers to several tens of nanometers. Similarly, the porosity can be adjusted to a range of about 10% to 90% or more.
[0017]
Various doping substrates can be used to produce porous silicon. In general, p-doped wafers of various doping degrees are used. The size of the structure can be determined inside the porous silicon by doping.
[0018]
By forming a porous structure, silicon acquires other internal chemical and physical properties (eg, other etch rates, thermal conductivity, heat capacity, etc.) such as large internal surfaces and the bulk silicon that it surrounds. Accordingly, the reactivity is clearly improved, which allows selective etching of porous silicon relative to bulk silicon.
[0019]
In this case, the production of the web in silicon is carried out as follows.
[0020]
In the case of silicon, the knowledge that p-doped silicon and n-doped silicon in particular have significantly different etching properties can be used. Under conditions where porous silicon can be produced in p-doped silicon, this is not possible or only possible to a very small extent in n-doped silicon. Thus, as a masking layer, for example, a thin layer on the surface of a p-doped substrate can be n-doped again (by ion implantation or diffusion). In the case of electrochemical etching, porous silicon is produced only in the p-doping region. The thickness of the masking layer can vary depending on processing parameters (doping amount, implantation energy, implantation after doping material). Since the formation of porous silicon is an isotropic process, the mask is under-etched accordingly. If the web region characterized by doping is completely under-etched, a free-standing web structure results after removal of the porous silicon.
[0021]
Due to the etching of the porous semiconductor material, in the case of silicon, there are essentially two possibilities, in particular after depositing the sensor layer. One uses strongly diluted potassium hydroxide solution (KOH) and one uses hydrofluoric acid (HF). In this case, the porous silicon is still treated in an oxidation step before coating the membrane region.
[0022]
In another advantageous embodiment of the invention, a plurality of flat membrane regions are arranged on the semiconductor material support as a support layer of the sensor element, wherein the plurality of flat membrane regions are transverse to the membrane region and the web. In a method of manufacturing a membrane sensor array with a semiconductor material support, which is thermally insulated by a web of material having a clearly improved thermal conductivity compared to the surrounding part of the Forms a web from the back side of the semiconductor material support by a subsequent anisotropic plasma etching process that allows the membrane layer to be coated directly on the semiconductor material support to achieve at least a nearly vertical etched side in the semiconductor. It is advantageous to do so. By this method, an improvement in integration density can be achieved to a considerable extent, especially with respect to membrane sensor arrays, despite the use of bulk micromechanical methods.
[0023]
Furthermore, the present invention has a support made of a semiconductor material, and a flat membrane region that exists in parallel on the support is arranged as a support layer of the sensor element, and this membrane region is located next to the membrane region and the web. Starting from a membrane sensor array in which the webs are insulated from one another by a web of material having a significantly improved thermal conductivity compared to the peripheral part of the direction, the web being formed from a semiconducting material of the support. The central idea of this configuration of the invention is that the width of the web in direct contact with the membrane region is less than 50 μm. The recognition that forms the basis of this idea is that, for example, when the web is placed under a continuous membrane and the membrane is divided into membrane regions, this type of formed web has a sufficient function as a heat sink. To meet.
[0024]
In order to obtain a simple structure of the membrane sensor array, it is further proposed that the web is formed only from the semiconductor material of the support.
[0025]
For example, in the case of silicon wafers, if masking is used by doping a p-doped wafer to produce a web, the web width and web thickness can be easily adjusted by the doping process, thereby The heat conduction value can be controlled in a sensitive manner. Exactly this masking process makes it possible to produce thin webs when viewed in the vertical direction, which meets the requirements of the heat sink. It has been found that a web thickness of less than 30 μm is already sufficient.
[0026]
The structure of the heat dissipation body advantageously consists of a web, for example a web arranged in a cruciform shape and a frame area joined to the web. In order to produce this heat sink structure for the surrounding semiconductor material in the process of forming the porous semiconductor material, it is advantageous if the web and the frame region are correspondingly doped.
[0027]
【Example】
The invention will be explained in greater detail by means of an embodiment shown in the drawing.
[0028]
FIG. 1 shows a p-doped silicon wafer 1 in which the regions 2 and 3 of the wafer are n-doped, for example by an ion implantation process. The n-doping region is not impaired when the porous silicon 9 is manufactured. In the production of porous silicon, lateral under-etching is observed below regions 2 and 3 in FIG. 1 based on isotropic etching. In this way, the silicon wafer is completely porous under the region 3. After removing the porous silicon 9 according to FIG. 2 in a selective etching process, a free-standing web correspondingly made of n-doped silicon is produced.
[0029]
A silicon wafer 4 is shown in FIG. 3a, and masks 5 and 6 made of silicon oxide and silicon nitride are formed to mask the porous region on the silicon wafer. Before removing the porous silicon 7, it is possible first to remove the mask made of silicon oxide, silicon nitride or silicon carbide or a combination thereof, so that the indentation 8 remains according to FIG. It does not have a protruding mask portion as in the second embodiment.
[0030]
FIG. 5 a shows a plan view of one example of membrane sensor array 20. A self-supporting membrane region 22 is formed on the bulk silicon 21 (see FIG. 5b), and the membrane region is insulated from one another by a lattice 23 together with a frame region 25 made of n-doped silicon that acts as a heat sink. The grid 23 and part of the frame area 25 are self-supporting, which further improves the thermal insulation.
[0031]
The arrangement of FIGS. 5a and 5b is realized, for example, by a surface micromechanical method in which porous silicon is produced as an intermediate step. A lattice-shaped n-doping region 23 having a frame region 25 is used as masking. For example, the doping of the n-doping lattice 23 and the frame 25 in the p-doped bulk silicon 21 is performed by ion implantation or by a diffusion process. In the case of ion implantation, the depth of the implantation region can be adjusted by implantation energy. The thickness of the radiator and the resulting thermal conductivity with it, in particular to the surrounding area, can thus be measured over a wide range. In the case of the diffusion process, the doping depth can be adjusted by the amount of the doping substance, the diffusion time and the diffusion temperature.
[0032]
In general, a doping depth greater than 10 μm is achieved by diffusion, but in the case of ion implantation, the depth is in the range of up to 5 μm. The process of preparing the production of porous silicon as an intermediate process can be roughly classified as follows.
[0033]
a) Production of porous silicon b) Partial oxidation in the case of porous silicon c) Deposition of membrane 24 (see FIG. 5b)
d) Deposition and structuring of the sensor layer (not shown in FIGS. 5a and 5b)
e) Deactivation of the membrane f) Production of openings in the membrane (not shown)
g) Removal of porous silicon or oxidized porous silicon.
[0034]
Instead of using n-doping masking, a masking layer having a sufficient thickness, such as the silicon oxide / silicon nitride layer 30 (see FIG. 6), can be used. When manufacturing porous silicon, masking is under-etched in the lateral direction based on an isotropic etching process in the same manner as n-doping masking. In FIG. 6a, the porous region 31 formed in the silicon wafer 32 is shown under the masking 30 with a clear underetch. After the porous silicon is locally produced, the masking 30 is removed and the sensor membrane 33 (see FIG. 6b) is deposited after the porous silicon is optionally oxidized. After the production of the sensor element (not shown), the optionally oxidized porous silicon is removed from the surface by a corresponding opening in the membrane 33. For simpler use, the porous or optionally oxidized porous silicon 31 can be left undisturbed, so that no depression 34 (see FIG. 6b) occurs. Thermal conductivity reduced to about one hundredth ensures thermal insulation even when leaving porous or optionally oxidized porous silicon. However, the Q value for the thermal conductivity of the depression 34 impinged by air, vacuum or fill gas is not achieved.
[0035]
By the method of the present invention, a membrane sensor can be realized in which the distance between the individual membrane regions 35 can be reduced to a minimum value of about 20 to 50 μm.
[0036]
The configuration of the membrane sensor array is not limited to the lattice structure. Other freely selectable shapes of the radiator are conceivable. FIG. 7 shows an embodiment having a web 40 as a linear heat sink for separating, for example, free-standing membrane regions 41 within the silicon bulk material 42.
[0037]
In the embodiment according to FIG. 4, the web 10 is formed as a heat radiator by an anisotropic plasma etching process on the back surface of the silicon wafer 11. The web 10 is self-supporting. Sensor elements can be arranged on the membrane 12 between the webs 10, which are insulated from one another by the web 10 acting as a radiator.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a silicon wafer having a doping region as a mask for producing porous silicon.
FIG. 2 is a cross-sectional view of the porous silicon according to FIG. 1 removed by etching.
FIG. 3 is a cross-sectional view of a silicon wafer in an arrangement comparable to FIGS. 1 and 2, but using a masking layer deposited later to produce porous silicon.
FIG. 4 is a cross-sectional view of a silicon wafer after etching the wafer back surface.
FIG. 5 is a plan view and a cross-sectional view of a membrane sensor array.
FIG. 6 is a cross-sectional view of another membrane sensor array at a different manufacturing stage.
FIG. 7 is a plan view of another membrane sensor array.

Claims (11)

Having a semiconductor material support (1, 4, 11, 21, 32, 42) on which a plurality of flat membrane regions (22, 35, 41) are arranged as a support layer for the sensor element is a flat membrane region (22,35,41) has a transverse thermal conductivity that is improvements in comparison with the peripheral portion of the membrane area (22,35,41) and the web (23,40) In the manufacturing method of a membrane sensor array which is insulated from each other by a web (23, 40) made of a material, first, a semiconductor material support (1, 4, 11, 21, 32, 42) is provided with a web (23 40), the masking for the next step of forming the porous semiconductor material is maintained, the semiconductor material not protected by the masking is made porous, and the membrane is formed thereon. Characterized in that to form a region, method of manufacturing the membrane sensor array.   2. The method according to claim 1, wherein a stable layer (5, 6, 30) is used for masking in the production of a porous semiconductor material. 3. The method of claim 2 , wherein silicon oxide, silicon nitride or silicon carbide or a combination thereof is used for masking . A semiconductor material support (1,4,11,21,32,42), at the location where the web (23,40) is formed for insulation, the Doping portion that have a predetermined depth as masking maintain, a semiconductor material that has not been allocated by the doping unit the method of any one of claims 1 to porous in the peripheral portion of the web up to 3. After coating the membrane region (22,35,41), to remove the semiconductor region made porous by etching, any one process of claim 1 to 4. A flat membrane region (22) having a support (21) made of a semiconductor material and arranged in parallel on the support is arranged as a support layer of the sensor element, and this membrane region is a membrane region (22). ) and the lateral insulation from each other by a web (23) made of a material having a compared to ambient partial improvements thermal conductivity of the web (23), whereby the web (23) is a semiconductor material of the support In the membrane sensor array (20) formed, the width of the web that directly contacts the membrane region is less than 50 μm.   7. A membrane sensor array according to claim 6, wherein the web (23) is formed only from the semiconductor material of the support.   The membrane sensor array according to claim 6 or 7, wherein the web (23) is arranged to stand on the lower side of the membrane region (22).   The membrane sensor array according to any one of claims 6 to 8, wherein the thickness of the web (23) is less than 30 m.   10. A membrane sensor array according to any one of claims 6 to 9, wherein the membrane region (22) forms a continuous membrane (24). Web (23) and around the web frame area (25), remaining as compared to the semiconductor material is Doping, membrane sensor array according to any one of claims 6 to 10.

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