JP4209797B2 - Transversal filter - Google Patents

Description

  The present invention relates to a transversal filter, and more particularly to an ultrahigh frequency operation transversal filter that compensates for chromatic dispersion and polarization mode dispersion in optical fiber communication with an electric circuit.

  Examples of conventional transversal filters are described in Patent Document 1 and Patent Document 2 below, for example.

  FIG. 11 shows an example of a conventional transversal filter. Data input from the input terminal 1 is level-adjusted by the input buffer 11 and input to the first to fourth delay circuits 21 to 24 connected in cascade. The output of the input buffer 11 and the outputs of the first to fourth delay circuits 21 to 24 are input to the first to fifth multiplier circuits 31 to 35, respectively. The outputs of the first to fifth multiplier circuits 31 to 35 are added by the first to fourth adder circuits 42 to 45 and output from the output terminal 2 via the output buffer 12.

  Here, the signal path passing through the first multiplication circuit 31 is P1, the signal path passing through the second multiplication circuit 32 is P2, the signal path passing through the third multiplication circuit 33 is P3, and the fourth multiplication circuit. A signal path passing through 34 is P4, and a signal path passing through the fifth multiplication circuit 35 is P5.

  FIG. 12 shows the transmission time of the conventional transversal filter. The horizontal axis indicates the signal path, and the vertical axis indicates the transmission time of the transversal filter. For example, P1 shown on the horizontal axis is a signal path passing through the first multiplier circuit 31, and the plot of the transmission time corresponding to this is a tap coefficient input to the first multiplier circuit 31 and all other multiplications. The transmission time of the transversal filter when the tap coefficient input to the circuit is zero is shown. As shown in the figure, the transmission time of the conventional transversal filter is variable by selecting the signal path (P1 to P5). Therefore, the conventional transversal filter functions as a finite-length impulse response circuit (FIR) by giving an appropriate tap coefficient.

JP 2003-087198 A JP 2003-258606 A

  In general, in a finite impulse response circuit, a combination of tap coefficients for realizing a required filter characteristic is calculated by Z conversion. In order to execute this calculation, it is required that the change in the transmission time when the signal path is changed in order is always constant. However, in the conventional transversal filter of FIG. 11, as shown in FIG. 12, the change in the transmission time when the signal path is changed in order is not constant. That is, the change in the transmission time is the largest when the signal path is changed from P1 to P2, and the change is the smallest when the signal path is changed from P4 to P5.

  In order to examine whether the change in transmission time (transmission time difference) is constant, it becomes clear by drawing a graph with the vertical axis representing the transmission time difference. FIG. 13 shows the transmission time difference of the conventional transversal filter. The horizontal axis shows two adjacent signal paths, and the vertical axis shows the transmission time difference of the transversal filter. For example, P2-P1 shown on the horizontal axis indicates two signal paths P2 and P1, and the vertical axis indicates a transmission time difference between the two signal paths. In a finite impulse response circuit, it is required that the transmission time differences between adjacent signal paths are all equal. However, in the conventional transversal filter, P2-P1 and P5-P4 are larger and smaller than the others, respectively. Such a variation in the transmission time difference is particularly noticeable when a high-frequency signal (approximately 10 GHz or more) is passed.

  The reason why the transmission time difference between the adjacent signal paths is not constant is because of the discontinuity existing at the input end and output end of the conventional transversal filter. That is, at the input end, only the output of the first multiplication circuit 31 is directly input to the first adder 42 corresponding to the subsequent stage, so that the transmission time of the signal path P1 becomes shorter than the other signal paths. . At the output end, the output of the fourth (generally N) delay circuit 24 has no delay circuit of the next stage for sending data, and the load is reduced compared to the first to third delay circuits 21 to 23. Therefore, the transmission time of the signal path P5 is shorter than that of the other signal paths.

  An object of the present invention is to provide a transversal filter that compensates for discontinuities at the input end and output end, or the output end, and makes the transmission time difference between adjacent signal paths equal or all other than the input end. There is to do.

  In order to achieve the above object, according to the present invention, as described in claim 1, the input buffer for adjusting the level of the input data, and the first from which the output of the input buffer is input and a predetermined time delay is applied. N delay circuits up to Nth (N is an integer of 3 or more), a first multiplication circuit that inputs the output of the input buffer, multiplies a tap coefficient given from the outside, and outputs the N multiplication circuit N outputs from the second to (N + 1) -th multiplication circuits that input the outputs of the respective delay circuits and output by multiplying by externally applied tap coefficients, and the K-th (K is an integer from 1 to N) The first to Nth adder circuits for adding the output of the K + 1 multiplier circuit and the output buffer to which the output of the Nth adder circuit is input. Constructed transversal fill An N + 1th delay circuit for inputting the output of the Nth delay circuit is newly provided, and all the wiring lengths connecting the Kth delay circuit and the (K + 1) th delay circuit are made equal. A characteristic transversal filter is constructed.

  Also, in the present invention, as described in claim 2, each of the N delay circuits from the first to the Nth is constituted by a cascade connection of a plurality of delay buffers, and the N + 1th delay circuit 2. The transversal filter according to claim 1, wherein the transversal filter comprises only a first-stage delay buffer among the plurality of delay buffers.

  Also, in the present invention, as described in claim 3, a pre-adder circuit that inputs an output of the first multiplier circuit and sends the output to the first adder circuit, and the pre-adder circuit A transversal filter according to claim 1 or 2, further comprising a signal generation circuit for transmitting a signal corresponding to zero to the other input of the first and second inputs.

  In the present invention, the delay time of the first delay circuit is set so that the delay time of the first adder circuit is shorter than the delay times of the second to Nth delay circuits. 3. The transversal filter according to claim 1, wherein the transversal filter is shortened by an amount corresponding to time.

  Implementation of the present invention compensates for discontinuities at the input and output terminals or output terminals by newly installing a delay circuit, a new combination of a signal generation circuit and an adder circuit, or shortening the delay time of the first stage delay circuit. Thus, it is possible to provide a transversal filter in which the transmission time difference between the signal paths of adjacent soils is all equal, or all except the input end.

(First embodiment)
FIG. 1 shows a transversal filter according to a first embodiment of the present invention. Data input from the input terminal 1 is level-adjusted by the input buffer 11 and input to the first to fourth delay circuits 21 to 24 connected in cascade. The output of the input buffer 11 and the outputs of the first to fourth delay circuits 21 to 24 are input to the first to fifth multiplier circuits 31 to 35, respectively. The outputs of the first to fifth multiplier circuits 31 to 35 are added by the first to fourth adder circuits 42 to 45 and output from the output terminal 2 via the output buffer 12. Here, the signal path passing through the first multiplication circuit 31 is P1, the signal path passing through the second multiplication circuit 32 is P2, the signal path passing through the third multiplication circuit 33 is P3, and the fourth multiplication circuit. A signal path passing through 34 is P4, and a signal path passing through the fifth multiplication circuit 35 is P5. Up to this point, the configuration is the same as that of the conventional transversal filter shown in FIG. In the present embodiment, the fifth delay circuit 25 is newly added to the output of the fourth delay circuit 24, and all the wiring lengths connecting the first to fifth delay circuits 21 to 25 are made equal. And different.

  FIG. 2 shows the transmission time of the transversal filter according to the first embodiment of the present invention. The horizontal axis indicates the signal path, and the vertical axis indicates the transmission time of the transversal filter. For example, P1 shown on the horizontal axis is a signal path passing through the first multiplier circuit 31, and the plot of the transmission time corresponding to this is a tap coefficient input to the first multiplier circuit 31 and all other multiplications. The transmission time of the transversal filter when the tap coefficient input to the circuit is zero is shown. As shown in the figure, the transmission time of the transversal filter of this embodiment is variable depending on the selection of the signal path (P1 to P5). Therefore, the transversal filter of this embodiment functions as a finite-length impulse response circuit (FIR) by giving an appropriate tap coefficient.

  FIG. 3 shows a transmission time difference of the transversal filter according to the first embodiment of the present invention. The horizontal axis shows two signal paths, and the vertical axis shows the transmission time difference of the transversal filter. For example, P2-P1 shown on the horizontal axis indicates two signal paths P2 and P1, and the vertical axis indicates a transmission time difference between the two signal paths.

  For example, the conventional transversal filter shown in FIG. 11 has a problem that the transmission time difference (P5−P4) between the signal path P5 and the signal path P4 is smaller than that due to the discontinuity at the output end. In the present embodiment, the fifth delay circuit 25 is newly added to the output of the fourth delay circuit 24, and the wiring lengths connecting the first to fifth delay circuits 21 to 25 are all designed to be equal. The transmission time difference (P5-P4) between the signal path P5 and the signal path P4 is completely equal to the others (P3-P2, P4-P3).

  The above effect was obtained not only because the lumped circuit constant load of the fourth delay circuit became equal to the lumped circuit constant load of the first to third delay circuits, but also between each delay circuit. This is because all the loads due to the wiring parasitics are equalized by making the wiring lengths connecting the two equal, and the discontinuity existing at the output end can be completely compensated.

  The present embodiment is an example of the embodiment according to claim 1 when N = 4. Even when N is an integer greater than or equal to 3 and different from 4, it is clear that the invention according to claim 1 has the same effect as the present embodiment.

(Second Embodiment)
FIG. 4 shows a transversal filter according to the second embodiment of the present invention. Data input from the input terminal 1 is level-adjusted by the input buffer 11 and input to the first to fourth delay circuits 21 to 24 connected in cascade. The output of the input buffer 11 and the outputs of the first to fourth delay circuits 21 to 24 are input to the first to fifth multiplier circuits 31 to 35, respectively. The outputs of the first to fifth multiplier circuits 31 to 35 are added by the first to fourth adder circuits 42 to 45 and output from the output terminal 2 via the output buffer 12. Further, as in the first embodiment, the fifth delay circuit 25A is newly added to the output of the fourth delay circuit 24, and the wiring length connecting the first to fifth delay circuits 21 to 24, 25A Are all designed equally. The difference from the first embodiment is that the first to fourth delay circuits 21 to 24 are each configured by cascading a plurality of delay buffers, and the fifth delay circuit 25 in the first embodiment is different from the first delay circuit 25 in the first embodiment. The fifth delay circuit 25A is composed of only the first-stage delay buffer among the plurality of delay buffers constituting the first to fourth delay circuits 21-24.

  FIG. 5 shows a circuit diagram of the fifth delay circuit 25A and its periphery. The fourth delay circuit 24 is composed of a plurality of delay buffers (six stages in the figure) in order to obtain a desired delay time, whereas the fifth delay circuit 25A is composed of only the first-stage delay buffer. . For this reason, this embodiment can be operated with low power compared to the first embodiment, and the same effect as the first embodiment can be achieved with low power.

  On the other hand, as in the first embodiment, the lumped circuit constant load of the fourth delay circuit is equal to the lumped circuit constant load of the first to third delay circuits, and between the delay circuits. By making all the connected wiring lengths equal, all the loads due to wiring parasitics are also equal, and discontinuities existing at the output end can be completely compensated. The operation of this embodiment shows the characteristics of the delay time shown in FIG. 2 and the delay time difference shown in FIG. 3, as in the first embodiment.

  The first to fourth delay circuits 21 to 24 are composed of a plurality of delay buffers. Specific examples of the circuit include “emitter follower (collector grounded amplifier) + differential amplifier + emitter follower + differential amplifier. .. ”or“ source follower + differential amplifier + source follower + differential amplifier... ”Or the like. In this case, the emitter follower or the source follower may be a first-stage delay buffer, that is, a fifth delay circuit.

  This embodiment is an embodiment when N = 4 in the invention according to claim 2. Even when N is an integer greater than or equal to 3 and different from 4, it is clear that the invention according to claim 2 has the same effect as the present embodiment.

(Third embodiment)
FIG. 6 shows a transversal filter according to a third embodiment of the present invention. Data input from the input terminal 1 is level-adjusted by the input buffer 11 and input to the first to fourth delay circuits 21 to 24 connected in cascade. The output of the input buffer 11 and the outputs of the first to fourth delay circuits 21 to 24 are input to the first to fifth multiplier circuits 31 to 35, respectively. The outputs of the first to fifth multiplier circuits 31 to 35 are added by the first to fourth adder circuits 42 to 45 and output from the output terminal 2 via the output buffer 12. Further, as in the first embodiment, the fifth delay circuit 25 is newly added to the output of the fourth delay circuit 24, and all the wiring lengths connecting the first to fifth delay circuits 21 to 25 are all. Designed equally. In the present embodiment, a pre-adder circuit 41 is newly added between the first multiplier circuit 31 and the first adder circuit 42, and a signal corresponding to zero is sent to the other input of the pre-adder circuit 41. A signal generation circuit 40 to be transmitted is added.

  FIG. 7 shows the transmission time of the transversal filter of the third embodiment of the present invention, and FIG. 8 shows the transmission time difference of the transversal filter of the third embodiment of the present invention. For example, the conventional transversal filter shown in FIG. 11 has a problem that the transmission time difference (P2−P1) between the signal path P2 and the signal path P1 is larger than that due to discontinuity at the input end. In the present embodiment, a pre-adder circuit 41 is newly added between the first multiplier circuit 31 and the first adder circuit 42, and a signal corresponding to zero is applied to the other input of the pre-adder circuit 41. Since the signal generation circuit 40 to be transmitted is added, the transmission time difference (P2-P1) between the signal path P2 and the signal path P1 becomes completely equal to the other (P3-P2, P4-P3, P5-P4).

  The above effect is obtained because the pre-adder circuit 41 that is symmetrical in terms of the circuit structure is added to the signal path P1 in the same manner as the other signal paths (P2 to P5). This is because the reachability was completely compensated.

  This embodiment is an embodiment when N = 4 in the invention according to claim 3. Even when N is an integer greater than or equal to 3 and different from 4, it is clear that the invention according to claim 3 has the same effect as the present embodiment.

(Fourth embodiment)
FIG. 9 shows a transversal filter according to the fourth embodiment of the present invention. Data input from the input terminal 1 is level-adjusted by the input buffer 11 and input to the first to fourth delay circuits 21A and 22-24 connected in cascade. The output of the input buffer 11 and the outputs of the first to fourth delay circuits 21A and 22 to 24 are input to the first to fifth multiplier circuits 31 to 35, respectively. The outputs of the first to fifth multiplier circuits 31 to 35 are added by the first to fourth adder circuits 42 to 45 and output from the output terminal 2 via the output buffer 12. Further, similarly to the first embodiment, the fifth delay circuit 25 is newly added to the output of the fourth delay circuit 24, and the wiring length connecting the first to fifth delay circuits 21A, 22-25 is connected. Are all designed equally. In the present embodiment, the delay time of the first delay circuit 21A is further made smaller than the delay times of the second to fourth delay circuits 22 to 24 by the amount corresponding to the transmission time of the first adder circuit 42. . Here, the transmission time of the adder circuit is the time from when a signal is input to the adder circuit until it is output. It is assumed that the first to fourth adder circuits 42 to 45 all have the same transmission time.

  FIG. 10 shows a circuit diagram of the first delay circuit 21A and its periphery. The second delay circuit 22 is configured by a plurality of delay buffers (six stages in the figure) to obtain a desired delay time, whereas the first delay circuit 21A is a delay time of the first adder circuit 42. The delay buffer corresponding to is deleted (in the figure, 5 stages).

  For example, the conventional transversal filter shown in FIG. 11 has a problem that the transmission time difference (P2−P1) between the signal path P2 and the signal path P1 is larger than that due to discontinuity at the input end. In the present embodiment, the delay time of the first delay circuit 21A is made smaller than the delay times of the second to fourth delay circuits 22 to 24 by an amount corresponding to the transmission time of the first adder circuit 42. , The discontinuity at the input end can be completely compensated, and the transmission time difference (P2-P1) between the signal path P2 and the signal path P1 is completely different from the others (P3-P2, P4-P3, P5-P4). An effect equal to is obtained. Further, as compared with the third embodiment, the pre-adder circuit 41 is unnecessary, and the number of elements of the delay circuit 21A can be reduced, so that an effect that can be realized with low power is obtained. The operation of the present embodiment shows the characteristics of the delay time shown in FIG. 7 and the delay time difference shown in FIG. 8, as in the third embodiment.

  The present embodiment is an embodiment when N = 4 in the invention according to claim 4. Even when N is an integer greater than or equal to 3 and different from 4, it is clear that the invention according to claim 4 has the same effect as the present embodiment.

It is a figure explaining the transversal filter of the 1st Embodiment of this invention. It is a figure which shows the transmission time of the transversal filter of the 1st Embodiment of this invention. It is a figure which shows the transmission time difference of the transversal filter of the 1st Embodiment of this invention. It is a figure explaining the transversal filter of the 2nd Embodiment of this invention. FIG. 10 is a circuit diagram of a fifth delay circuit 25A and its surroundings. It is a figure explaining the transversal filter of the 3rd Embodiment of this invention. It is a figure which shows the transmission time of the transversal filter of the 3rd Embodiment of this invention. It is a figure which shows the transmission time difference of the transversal filter of the 3rd Embodiment of this invention. It is a figure explaining the transversal filter of the 4th Embodiment of this invention. It is a circuit diagram of the first delay circuit 21A and its periphery. It is a figure explaining the conventional transversal filter. It is a figure which shows the transmission time of the conventional transversal filter. It is a figure which shows the transmission time difference of the conventional transversal filter.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Input terminal, 2 ... Output terminal, 3-7 ... Tap coefficient input terminal, 11 ... Input buffer, 12 ... Output buffer, 21 ... 1st delay circuit, 21A ... 1st delay circuit, 22 ... 2nd Delay circuit, 23 ... third delay circuit, 24 ... fourth delay circuit, 25 ... fifth delay circuit, 25A ... fifth delay circuit, 31 ... first multiplier circuit, 32 ... second multiplier circuit , 33... Third multiplier circuit, 34... Fourth multiplier circuit, 35... Fifth multiplier circuit, 40... Signal generation circuit, 41 ... pre-adder circuit, 42 ... first adder circuit, 43. , 44... Third adder circuit, 45... Fourth adder circuit.

Claims (4)

An input buffer that adjusts the level of input data, and N delay circuits from the first to Nth (N is an integer of 3 or more) that inputs the output of the input buffer and applies a predetermined time delay;
A first multiplication circuit that inputs the output of the input buffer and multiplies a tap coefficient given from the outside;
N multiplier circuits from the second to the (N + 1) th to input the outputs of the N delay circuits, multiply the tap coefficients given from the outside, and output them,
First to Nth addition circuits for adding the output of the Kth (K is an integer from 1 to N) multiplication circuit and the output of the (K + 1) th multiplication circuit;
An output buffer for inputting an output of the Nth adder circuit;
A transversal filter comprising:
An N + 1th delay circuit for inputting the output of the Nth delay circuit is newly provided,
A transversal filter characterized in that all the wiring lengths connecting the Kth delay circuit and the (K + 1) th delay circuit are equal. Each of the N delay circuits from the first to the Nth is configured by a cascade connection of a plurality of delay buffers,
2. The transversal filter according to claim 1, wherein the (N + 1) -th delay circuit includes only a first-stage delay buffer among the plurality of delay buffers. A pre-adder circuit that inputs the output of the first multiplier circuit and sends the output to the first adder circuit;
A signal generating circuit for sending a signal corresponding to zero to the other input of the pre-adder circuit;
The transversal filter according to claim 1, wherein a transversal filter is provided.   2. The delay time of the first delay circuit is shorter than the delay times of the second to Nth delay circuits by an amount corresponding to the transmission time of the first adder circuit. Or the transversal filter of 2.

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