JP4193256B2 - Audio signal processing apparatus and method, and video / audio recording / reproducing apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an audio signal processing apparatus and method, and a video / audio recording / reproducing apparatus in which noise generated when a mute of a digital audio signal is canceled is not generated.
[0002]
[Prior art]
Currently, digital audio devices that process analog audio signals as A / D converted digital audio data have become widespread. Even if the process is repeated, the sound quality is hardly deteriorated and a high sound quality can be obtained relatively easily. Therefore, it is widely used regardless of professional use or amateur use.
[0003]
By the way, when the audio signal is reproduced, there is a case where a mute process for temporarily silence the reproduction output is performed. For example, when the audio circuit is started up, or when an excessive level signal or an illegal signal is input, the output is automatically silenced by the mute processing to protect the circuit and the speaker. The mute process is canceled automatically or manually, and normal reproduction is resumed.
[0004]
If the silent state is simply switched to the normal playback state when canceling the mute process, the signal waveform may rise sharply when the normal playback state is reached. The steep rise of the signal waveform appears as a pulse-like noise “pit” with respect to the reproduced sound.
[0005]
[Problems to be solved by the invention]
In a conventional digital audio device, a pulse noise such as “petit” generated at a change point from the mute state to the normal reproduction state is suppressed by arithmetic processing. For example, in an integrated circuit (IC) dedicated to audio data processing, a multiplier is used to attenuate a signal level by multiplying a predetermined count for each sample in the time series direction. However, this method has a problem that the audio data signal circuit becomes complicated and the scale becomes large because a multiplier is used.
[0006]
In portable devices such as video tape recorders with built-in cameras, for example, low power consumption due to longer battery operation and circuit reduction due to substrate size limitations associated with smaller and lighter devices Therefore, an audio data processing IC provided with a multiplier for mute processing is often omitted. Therefore, such a portable device has a problem in that pulse noise is generated when mute is released.
[0007]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an audio signal processing apparatus and method, and a video / audio recording / reproducing apparatus which are configured so as not to generate noise upon canceling mute with a simple configuration.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problem, the present invention is directed to an audio signal processing apparatus for processing a digital audio signal, wherein at the time of start-up from a silent state to a voiced state, only higher-order bits of input audio data are lower-ordered. The audio signal processing apparatus is characterized in that the level of the audio data is inclined by bit-shifting the signal to the next bit and decreasing the bit-shift amount with time from the start-up.
[0009]
The present invention also provides video signal recording in which video data and audio data are error correction encoded using product codes and recorded on a recording medium, and the video data and audio data recorded on the recording medium are reproduced. In the reproducing apparatus, input video data and audio data are each subjected to error correction encoding using a product code, added with ID information and a synchronization signal and recorded on a recording medium, and the recording medium Reproducing means for reproducing the recorded video data and audio data, and decoding the error correction coding by the product code based on the synchronization signal and the ID information, respectively, for the reproduced video data and audio data; The audio data played back by the playback means is changed from the silent state to the voiced state. And means for shifting the upper bits of the audio data to the lower side at the time of starting up, and reducing the amount of bit shift with time from the time of starting, so as to incline the level of the audio data. Is a video / audio recording / reproducing apparatus.
[0010]
The present invention also relates to an audio signal processing method for processing a digital audio signal, wherein at the time of start-up from a silent state to a voiced state, only the upper bits of the input audio data are bit-shifted to the lower side, and the bit shift is performed. The audio signal processing method is characterized in that the level of the audio data is decreased with time from the time of start-up to give a slope to the level of the audio data.
[0011]
As described above, according to the present invention, at the time of start-up from the silent state to the sound state, only the high-order bits of the input audio data are bit-shifted to the low-order side, and the amount of bit shift is increased with time from the start-up. Since the number is reduced, it is possible to add a slope to the level of the audio data at the time of start-up from the silent state to the voiced state with a simple configuration that only performs bit shift.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment in which the present invention is applied to a digital VTR will be described. This embodiment is suitable for use in a broadcast station environment, and enables recording / playback of video signals in a plurality of different formats. For example, both signals with 480 effective lines (480i signal) in interlaced scanning based on the NTSC system and signals with 576 effective lines (576i signal) in interlaced scanning based on the PAL system are almost hard. It is possible to record and play back without changing the wear. Furthermore, signals with 1080 lines (1080i signal) in interlaced scanning and signals with 480 lines, 720 lines, and 1080 lines in progressive scanning (non-interlaced) (480p signal, 720p signal, 1080p signal), respectively. Recording / playback can be performed.
[0013]
In this embodiment, the video signal is compression-encoded based on the MPEG2 system, and the audio signal is handled without being compressed. As is well known, MPEG2 is a combination of motion compensation predictive coding and compression coding by DCT. The data structure of MPEG2 has a hierarchical structure, and from the lower order is a block layer, a macroblock layer, a slice layer, a picture layer, a GOP layer, and a sequence layer.
[0014]
The block layer is composed of DCT blocks that are units for performing DCT. The macroblock layer is composed of a plurality of DCT blocks. The slice layer is composed of a header part and an arbitrary number of macroblocks that do not extend between rows. The picture layer is composed of a header part and a plurality of slices. A picture corresponds to one screen. The GOP (Group Of Picture) layer is composed of a header part, an I picture that is a picture based on intra-frame coding, and a P and B picture that are pictures based on predictive coding.
[0015]
A GOP includes at least one I picture, and P and B pictures are allowed even if they do not exist. The uppermost sequence layer includes a header part and a plurality of GOPs.
[0016]
In the MPEG format, a slice is one variable length code sequence. A variable-length code sequence is a sequence in which a data boundary cannot be detected unless the variable-length code is decoded.
[0017]
In addition, an identification code (referred to as a start code) having a predetermined bit pattern arranged in units of bytes is arranged at the heads of the sequence layer, GOP layer, picture layer, slice layer, and macroblock layer. . In addition, the header part of each layer mentioned above describes a header, extension data, or user data collectively. In the header of the sequence layer, the size (number of vertical and horizontal pixels) of the image (picture) is described. In the GOP layer header, a time code, the number of pictures constituting the GOP, and the like are described.
[0018]
The macroblock included in the slice layer is a set of a plurality of DCT blocks, and the coded sequence of the DCT block is a sequence of quantized DCT coefficients, the number of consecutive 0 coefficients (run), and the non-zero sequence immediately thereafter. (Level) is variable length encoded as one unit. Identification codes arranged in byte units are not added to the macroblock and the DCT block in the macroblock. That is, these are not one variable length code sequence.
[0019]
The macro block is obtained by dividing a screen (picture) into a grid of 16 pixels × 16 lines. The slice is formed by, for example, connecting the macro blocks in the horizontal direction. The last macroblock of the previous slice and the first macroblock of the next slice are continuous, and it is not allowed to form macroblock overlap between slices. When the screen size is determined, the number of macro blocks per screen is uniquely determined.
[0020]
On the other hand, in order to avoid signal degradation due to decoding and encoding, it is desirable to edit on the encoded data. At this time, the P picture and the B picture require the temporally previous picture or the previous and subsequent pictures for decoding. For this reason, the editing unit cannot be set to one frame unit. In consideration of this point, in this embodiment, one GOP is made up of one I picture.
[0021]
Further, for example, a recording area in which recording data for one frame is recorded is a predetermined one. Since MPEG2 uses variable length coding, the amount of data generated for one frame is controlled so that data generated in one frame period can be recorded in a predetermined recording area. Further, in this embodiment, one slice is composed of one macro block and one macro block is applied to a fixed frame having a predetermined length so as to be suitable for recording on a magnetic tape.
[0022]
FIG. 1 shows an example of the configuration of the recording side of the recording / reproducing apparatus according to this embodiment. At the time of recording, a digital video signal is input from the terminal 101 via a receiving unit of a predetermined interface, for example, SDI (Serial Data Interface). SDI is an interface defined by SMPTE for transmitting (4: 2: 2) component video signals, digital audio signals and additional data. The input video signal is subjected to DCT (Discrete Cosine Transform) processing in the video encoder 102, converted into coefficient data, and the coefficient data is variable-length encoded. The variable length coding (VLC) data from the video encoder 102 is an elementary stream compliant with MPEG2. This output is supplied to one input terminal of the selector 103.
[0023]
On the other hand, SDTI (Serial Data Transport Interface) format data, which is an interface defined by ANSI / SMPTE 305M, is input through the input terminal 104. This signal is synchronously detected by the SDTI receiving unit 105. Then, once stored in the buffer, the elementary stream is extracted. The extracted elementary stream is supplied to the other input terminal of the selector 103.
[0024]
The elementary stream selected and output by the selector 103 is supplied to the stream converter 106. In the stream converter 106, the DCT coefficients arranged for each DCT block based on the MPEG2 regulations are grouped for each frequency component through a plurality of DCT blocks constituting one macro block, and the collected frequency components are rearranged. The rearranged converted elementary streams are supplied to the packing and shuffling unit 107.
[0025]
Since the elementary stream video data is variable-length encoded, the data lengths of the macroblocks are not uniform. In the packing and shuffling unit 107, macroblocks are packed in a fixed frame. At this time, the portion that protrudes from the fixed frame is sequentially packed into the remaining portion with respect to the size of the fixed frame. Further, system data such as a time code is supplied from the input terminal 108 to the packing and shuffling unit 107, and the system data is subjected to a recording process in the same manner as picture data. Further, shuffling is performed in which the macroblocks of one frame generated in the scanning order are rearranged to distribute the recording positions of the macroblocks on the tape. Shuffling can improve the image update rate even when data is reproduced piecewise during variable speed reproduction.
[0026]
Video data and system data from the packing and shuffling unit 107 (hereinafter, unless otherwise required, system data is also simply referred to as video data) is supplied to the outer code encoder 109. A product code is used as an error correction code for video data and audio data. In the product code, the outer code is encoded in the vertical direction of the two-dimensional array of video data or audio data, the inner code is encoded in the horizontal direction, and the data symbols are encoded doubly. As the outer code and the inner code, a Reed-Solomon code can be used.
[0027]
The output of the outer code encoder 109 is supplied to the shuffling unit 110, and shuffling is performed in which the order is changed in units of sync blocks over a plurality of ECC (Error Correctig Code) blocks. Shuffling in sync block units prevents errors from concentrating on a specific ECC block. The shuffling performed by the shuffling unit 110 may be referred to as interleaving. The output of the shuffling unit 110 is supplied to the mixing unit 111 and mixed with the audio data. Note that the mixing unit 111 includes a main memory as will be described later.
[0028]
Audio data is supplied from an input terminal 112. In this embodiment, uncompressed digital audio signals are handled. The digital audio signal is separated by an input side SDI receiving unit (not shown) or SDTI receiving unit 105, or inputted via an audio interface. The input digital audio signal is supplied to the AUX adding unit 114 via the delay unit 113. The delay unit 113 is for time alignment of the audio signal and the video signal. The audio AUX supplied from the input terminal 115 is auxiliary data, and is data having information related to audio data such as a sampling frequency of the audio data. The audio AUX is added to the audio data by the AUX adding unit 114 and is handled in the same way as the audio data.
[0029]
Audio data and AUX from the AUX adding unit 114 (hereinafter referred to simply as audio data including AUX unless otherwise required) are supplied to the outer code encoder 116. The outer code encoder 116 encodes audio data with an outer code. The output of the outer code encoder 116 is supplied to the shuffling unit 117 and subjected to shuffling processing. As audio shuffling, shuffling in sync blocks and shuffling in channels are performed.
[0030]
The output of the shuffling unit 117 is supplied to the mixing unit 111, and the video data and the audio data are converted into one channel data. The output of the mixing unit 111 is supplied to the ID adding unit 118, and the ID adding unit 118 adds an ID having information indicating a sync block number. The output of the ID adding unit 118 is supplied to the inner code encoder 119, and the inner code is encoded. Further, the output of the inner code encoder 119 is supplied to the synchronization adding unit 120, and a synchronization signal for each sync block is added. Recording data with continuous sync blocks is configured by adding a synchronization signal. This recording data is supplied to the rotary head 122 via the recording amplifier 121 and recorded on the magnetic tape 123. The rotary head 122 is actually a magnetic head in which a plurality of magnetic heads having different azimuths forming adjacent tracks are attached to a rotary drum.
[0031]
You may perform a scramble process with respect to recording data as needed. Also, digital modulation may be performed during recording, and partial response class 4 and Viterbi code may be used.
[0032]
Signal recording on the magnetic tape is performed by a helical scan method in which an oblique track is formed by a magnetic head provided on a rotating rotary head. A plurality of magnetic heads are provided on the rotary drum at positions facing each other. That is, when the magnetic tape is wound around the rotary head with a winding angle of about 180 °, a plurality of tracks can be simultaneously formed by rotating the rotary head at 180 °. Further, two magnetic heads having different azimuths are used as one set. The plurality of magnetic heads are arranged so that adjacent tracks have different azimuths.
[0033]
FIG. 2 shows an example of the configuration on the playback side of one embodiment of the present invention. A reproduction signal reproduced by the rotary head 122 from the magnetic tape 123 is supplied to the synchronization detection unit 132 via the reproduction amplifier 131. Equalization and waveform shaping are performed on the reproduced signal. Further, demodulation of digital modulation, Viterbi decoding, and the like are performed as necessary. The synchronization detector 132 detects a synchronization signal added to the head of the sync block. A sync block is cut out by synchronization detection.
[0034]
The output of the synchronization detection block 132 is supplied to the inner code decoder 133 and error correction of the inner code is performed. The output of the inner code decoder 133 is supplied to the ID interpolation unit 134, and the ID of the sync block, for example, the sync block number, which is an error due to the inner code, is interpolated. The output of the ID interpolation unit 134 is supplied to the separation unit 135, and the video data and the audio data are separated. As described above, video data means DCT coefficient data and system data generated by MPEG intra coding, and audio data means PCM (Pulse Code Modulation) data and AUX.
[0035]
The video data from the separation unit 135 is processed in the deshuffling unit 136 in the reverse process of shuffling. The deshuffling unit 136 performs a process of restoring the sync block unit shuffling performed by the recording-side shuffling unit 110. The output of the deshuffling unit 136 is supplied to the outer code decoder 137, and error correction using the outer code is performed. When an error that cannot be corrected occurs, an error flag indicating the presence or absence of an error indicates that there is an error.
[0036]
The output of the outer code decoder 137 is supplied to the deshuffling and depacking unit 138. The deshuffling and depacking unit 138 performs processing for restoring the macroblock unit shuffling performed by the recording side packing and shuffling unit 107. The deshuffling and depacking unit 138 disassembles the packing applied during recording. That is, the original variable length code is restored by returning the data length in units of macroblocks. Further, in the deshuffling and depacking unit 138, the system data is separated and taken out to the output terminal 139.
[0037]
The output of the deshuffling and depacking unit 138 is supplied to the interpolation unit 140, and the data in which the error flag is set (that is, there is an error) is corrected. That is, if there is an error in the middle of the macroblock data before conversion, the DCT coefficient of the frequency component after the error location cannot be restored. Therefore, for example, the data at the error location is replaced with a block end code (EOB), and the DCT coefficients of the frequency components thereafter are set to zero. Similarly, during high-speed reproduction, only DCT coefficients up to the length corresponding to the sync block length are restored, and the subsequent coefficients are replaced with zero data. Further, the interpolation unit 140 performs processing for recovering the header (sequence header, GOP header, picture header, user data, etc.) when the header added to the head of the video data is an error.
[0038]
Since the DCT coefficients are arranged from the DC component and the low-frequency component to the high-frequency component across the DCT block, a macroblock is configured even if the DCT coefficient is ignored from a certain point in this way. For each DCT block, DCT coefficients from DC and low frequency components can be distributed evenly.
[0039]
The output of the interpolation unit 140 is supplied to the stream converter 141. The stream converter 141 performs the reverse process of the stream converter 106 on the recording side. That is, the DCT coefficients arranged for each frequency component across DCT blocks are rearranged for each DCT block. As a result, the reproduction signal is converted into an elementary stream compliant with MPEG2.
[0040]
As for the input / output of the stream converter 141, as in the recording side, a sufficient transfer rate (bandwidth) is secured according to the maximum length of the macroblock. When the length of the macroblock is not limited, it is preferable to secure a bandwidth that is three times the pixel rate.
[0041]
The output of the stream converter 141 is supplied to the video decoder 142. The video decoder 142 decodes the elementary stream and outputs video data. That is, the video decoder 142 performs an inverse quantization process and an inverse DCT process. Decoded video data is extracted to the output terminal 143. For example, SDI is used as an interface with the outside. Further, the elementary stream from the stream converter 141 is supplied to the SDTI transmission unit 144. Although the route is not shown in the SDTI transmission unit 144, system data, reproduction audio data, and AUX are also supplied and converted into a stream having a data structure of the SDTI format. A stream from the SDTI transmission unit 144 is output to the outside through the output terminal 145.
[0042]
The audio data separated by the separation unit 135 is supplied to the deshuffling unit 151. The deshuffling unit 151 performs a process reverse to that performed by the shuffling unit 117 on the recording side. The output of the deshuffling unit 117 is supplied to the outer code decoder 152, and error correction using the outer code is performed. From the outer code decoder 152, error-corrected audio data is output. For data with errors that cannot be corrected, an error flag is set.
[0043]
The output of the outer code decoder 152 is supplied to the AUX separation unit 153, and the audio AUX is separated. The separated audio AUX is taken out to the output terminal 154. Audio data is supplied to the interpolation unit 155. The interpolation unit 155 interpolates samples with errors. As an interpolation method, average value interpolation for interpolating with the average value of correct data before and after time, pre-value hold for holding the value of the previous correct sample, and the like can be used. The output of the interpolation unit 155 is supplied to the output unit 156. The output unit 156 performs a mute process for prohibiting output of an audio signal that is an error and cannot be interpolated, and a delay amount adjustment process for time alignment with the video signal. A reproduced audio signal is extracted from the output unit 156 to the output terminal 157.
[0044]
Although omitted in FIGS. 1 and 2, a timing generator for generating a timing signal synchronized with input data, a system controller (microcomputer) for controlling the overall operation of the recording / reproducing apparatus, and the like are provided. .
[0045]
Next, the footprint for the magnetic tape and the format of the audio data in this embodiment will be described.
[0046]
3 to 5 show the types of audio error correction blocks that can be supported by the recording / reproducing apparatus according to the embodiment. Audio error correction blocks can be broadly classified by the difference in field (frame) frequency. There are five field (frame) frequencies: 29.97 Hz, 59.94 Hz, 25 Hz, 50 Hz, and 23.976 Hz. 29.97 Hz, 25 Hz, and 23.976 Hz are frequencies in the case of progressive (non-interlaced) scanning, and the other frequencies are interlaced scanning. FIG. 3 shows an example of a field (frame) frequency 29.97 Hz / 59.94 Hz, and FIG. 4 shows an example of a field (frame) frequency 25 Hz / 50 Hz. FIG. 5 shows an example of a frame frequency of 23.976 Hz.
[0047]
Since the frame period of progressive scanning is the same as the interlaced field period, in order to avoid complexity, the frame and field of interlaced scanning are simply referred to as frame and field, and the frame of progressive scanning is This is called a P frame.
[0048]
There are two types of audio bits per sample: 16 bits and 24 bits depending on the difference in sound quality required for each format. 3A, 4A and 5A show 16 bits / sample, and FIGS. 3B, 4B and 5B show 24 bits / sample. The sampling frequency is all 48 KHz.
[0049]
In the error correction block, error correction encoding is performed in units of one symbol consisting of, for example, 8 bits (1 byte), and one row in the horizontal direction corresponds to the sync block. SY is a sync pattern on tape recording, and 2 bytes are allocated. The ID stores important information inherent to the sync block, such as sync number and segment number video / audio, and is assigned 2 bytes. The DID contains important information related to audio data such as audio 5FSeq (described later) information, and 1 byte is allocated.
[0050]
For example, an error correction block of 59.94 Hz, 16 bytes / sample is shown in the upper left of FIG. 1, and the number of data of one sync block is 119 bytes, the inner code parity is 12 bytes, and the outer code parity is 10 bytes. I understand that there is.
[0051]
FIG. 6 shows the structure of the sync block. FIG. 7 shows bit assignment of ID and DID in the sync block. In FIG. 6A, SYNC is a sync pattern on tape recording, and 2 bytes (76B4h: h represents hexadecimal notation) are allocated. Following the SYNC, a 2-byte ID is arranged, and a data area having a variable capacity of 112 bytes to 189 bytes is arranged. The subsequent 12 bytes are parity, and the inner code parity is stored.
[0052]
In the data area, as shown in FIG. 6B, 1-byte DID is arranged at the head, and audio data is subsequently stored. This entire data area is called a payload.
[0053]
As shown in the left side of FIG. 7A, ID0 stores a sync ID that is an identification number of the sync block. With ID0, another ID is assigned to each audio sync block on one track. As shown on the right side of FIG. 7A, ID1 stores a segment number, a video / audio identification bit, and the like. The azimuth number is azimuth information, and [0] or [1] is entered. Upper / Lower is additional information of the sync ID, and the sync block on the track can be distinguished and identified by the 8 bytes of ID0, the video / audio identification bit, and the Upper / Lower. Edit IN is edit information, and this bit is recorded as [1] at the IN point at the time of editing.
[0054]
FIG. 7B shows the bit assignment of the DID. NT Seq in the DID is used to identify which sync block is the same field during non-tracking reproduction. Data / audio is set to [1] when data other than uncompressed audio data is stored in an audio sync block. 5FSeq contains information on a five-field sequence generated when the frame (field) frequency is 59.94 Hz and 29.97 Hz.
[0055]
The 5-field sequence is a period of 5 fields when the sampling frequency of audio data is 48 KHz, and is 4004 samples / 5 fields. Therefore, when assigning each field to 800, 801, 801, 801, Assign as 801 samples / field. This is called a 5-field sequence.
[0056]
FIG. 8 shows a layout in an error correction block for audio of one channel and one field when frame (field) frequencies are 29.97 Hz and 59.94 Hz. FIG. 8A shows the arrangement schematically, and FIG. 8B shows it in more detail. This also applies to FIGS. 9 and 10 below. 800 or 801 samples per field are divided into two error correction blocks in which even-numbered samples and odd-numbered samples are stored, respectively. In FIG. 8, AUX0, AUX1, and AUX2 are AUX data, and auxiliary data related to audio is stored.
[0057]
Each frame corresponds to the data length of one sample, and the numbers in the frame correspond to sample numbers representing the sample order of audio data. PVx is an outer code parity, which will be described later. Numbers 0 to 800 are audio sample data, and as described above, there are five field sequences, which are 800 or 801 samples / field. In the case of 800 samples / field, the No. 798 sample stored in No. 798 is copied to No. 800.
[0058]
PV0 to PV9 are 10-byte outer code parity in the vertical series. The outer code number is a number for collectively calling sync blocks that are horizontal data. Since one field (1P frame) is 36 sync blocks, the outer code number is 0-35.
[0059]
FIGS. 9 and 10 are layouts in an audio error correction block when the frame (field) frequencies are 25 Hz / 50 Hz and 23.976 Hz, respectively. These are the same as in the case of 29.97 Hz / 59.94 Hz shown in FIG. 8 except for the difference in the sample numbers accompanying the change in the total number of samples.
[0060]
FIGS. 11 to 14 show examples of channel allocation on the footprint in each format. There are four types of formats, referred to as SD1 to SD4, respectively. 11 shows SD1, FIG. 12 shows SD2, FIG. 13 shows SD3, and FIG. 14 shows SD4. In each figure, a square represents one sector, and Ax therein represents an audio channel number. Also, the numbers “9” and “6” shown on the right side of each figure indicate the number of sync blocks per sector.
[0061]
For example, in the case of the format SD1, as shown in FIG. 11, there are four channels A0 to A3, and 9 [sync block] × 2 [sector / track, channel] × 4 [track / frame] = It can be seen that there are 72 sync blocks / channel and frame. That is, it can be seen that each channel has 72/2 = 36 sync blocks per field. When the formats SD2 to SD4 are calculated in the same manner, 36 sync blocks / channel and field per channel in one field or 1P frame. This corresponds to the 36 outer code numbers per field (1P frame) in FIGS.
[0062]
The reason why the number of tracks per field or 1P frame is different is that the amount of data differs depending on the format due to the difference in the compression rate of video, and the number of necessary tracks varies accordingly. In this embodiment, audio data is handled uncompressed, and the amount of audio data per field (1P frame) is always the same. Therefore, the audio is also divided into SD1 to SD4 formats corresponding to the number of tracks that require video.
[0063]
FIG. 15 shows audio outer code number allocation in each format. FIG. 15A shows an example of format SD1, and FIG. 15B shows an example of SD4. FIG. 15C shows an arrangement common to the formats SD2 and SD3. It shows how the outer code numbers of one channel and one field are arranged with respect to the segment and azimuth. In this figure, the number written in the square is the outer code number. The arrows in the figure indicate the head trace direction. One row in the horizontal direction corresponds to one sector. For example, in SD1, it can be seen that audio data for one channel and one field is arranged over two sectors.
[0064]
As can be seen from FIGS. 15A to 15C, the 36 outer code numbers for one field are shuffled and rearranged in order. Depending on the direction of the head trace, the left side is recorded first. For example, in the case of SD3 (SD2) in FIG. 15C, outer code numbers 19 and 18 are recorded at the head.
[0065]
In this example, one sector of azimuth 0 and segment 0 is composed of 9 sync blocks of outer code numbers 19, 21, 0, 4, 8, 12, 16, 23, and 25. The one sector is azimuth 0 and segment 0. If this is A0, this one sector is written to azimuth 0 and segment 0 A0 of the format SD3 shown in FIG. Further, one sector of the outer code numbers 28, 30, 1, 5, 9, 13, 17, 32, and 34 in the format SD3 of FIG. 15C is azimuth 1 and segment 1, and if this is A0, the sector of SD3 of FIG. This one sector is written for azimuth 1, segment A0.
[0066]
Next, audio decoding processing in this embodiment will be described. FIG. 16 shows an example of the configuration of the decoder 1 used in this storage / playback apparatus. The decoder 1 is configured in, for example, one IC (integrated circuit). Further, this configuration corresponds to the configuration of the audio signal processing system from the separation circuit 135 and the deshuffling circuit 151 to the output unit 156 in FIG. The decoder 1 deshuffles the reproduction signals shuffled during recording and rearranges them in the original order. Then, a total of 16 channels of audio data are output, each of which is called Adv and Conf.
[0067]
The timing generation block 10 generates various timing signals, control signals, and various information necessary in the decoder 1 based on the supplied various signals. The control signal generated by the timing generation block 10 is supplied to the RC block 19. Various information generated by the timing generation block 10 is supplied to the deshuffling unit 11 and the AOT block 16.
[0068]
The reproduction data reproduced from the magnetic tape 123 and subjected to synchronization detection, inner code correction, and ID interpolation is supplied to the deshuffling unit 11 in units of sync blocks. The deshuffling unit 11 generates an address for writing data to the SDRAM (Synchronous DRAM) 13 based on the deshuffling tables stored in the channel deshuffling RAM 14 and the sync deshuffling RAM 15. This address is supplied to the SDRAM controller 12 together with the reproduction data. The reproduction data is rearranged in the original data order and written to the SDRAM 13 under the control of the SDRAM controller 12 based on the supplied address.
[0069]
The data read from the SDRAM 13 is supplied to the AOT block 16, and outer code correction is performed using the outer code RAMs 17A and 17B. In the AOT block 16, an error flag and AUX data are extracted. The reproduction data whose outer code has been corrected is classified into Adv and Conf based on the information of ID1 and AUX data, and is divided for each channel and output from the AOT block 16. At this time, two channels are used as one signal path, and a total of eight signals are output. The four outputs of the Adv system are supplied to the rate conversion RAMs 18A to 18D, respectively. Similarly, the four outputs of the Conf system are respectively supplied to the rate conversion RAMs 18E to 18H. In each figure, the rate conversion RAM is abbreviated as RC RAM.
[0070]
The rate conversion RAMs 18 </ b> A to 18 </ b> H are read and controlled by the RC block 19. The RC block 19 is supplied with a control signal from the AOT block 16 and supplied with a field start signal from the RC block 19 to the AOT block 16. Based on the control of the RC block 19, the reproduced audio data is read from the rate conversion RAMs 18 </ b> A to 18 </ b> H in 8-bit parallel and supplied to the AIF block 20.
[0071]
The AIF block 20 performs parallel / serial conversion on the supplied reproduced audio data and outputs the data as output data of 8 channels and 2 systems. Further, the AIF block 20 performs audio data modification, mute processing, and the like as necessary.
[0072]
Next, each part of the decoder 1 will be described in more detail. The timing generation block 10 receives a TG-frame that is a frame signal, a TG-AVSTO that is a field signal, a TG-5F-ID that is a reference 5 field sequence ID, and an FS that is a sample delimiter signal, and is necessary inside the decoder 1. Timing signals, control signals, and various information are generated. The timing generation block 10 sends the Adv path number, Adv light field bank number, Conf path number, and Conf light field bank number (described later) to the deshuffling unit 11 as control signals.
[0073]
The deshuffling unit 11 is supplied with the reproduction data with the inner code corrected. Outer code correction has not yet been performed on this reproduced data. Then, using the channel deshuffling RAM 14 and the sync deshuffling RAM 15, deshuffling is performed, and an address for writing the reproduction data to the SDRAM 13 is generated. By writing the reproduction data into the SDRAM 12 according to this address, the reproduction data is deshuffled. Address information and reproduction data are supplied to the SDRAM controller 12, and reproduction data is written to the SDRAM 13 by address control of the SDRAM controller 12.
[0074]
The processing in the channel deshuffling RAM 14 and the sync and shuffling RAM 15 will be described in more detail. The processing in the RAMs 14 and 15 is a part related to the gist of the present invention.
[0075]
The address assignment of the SDRAM 13 will be described with reference to FIGS. In the SDRAM 13, the audio data is written by being divided by fields. An area of the SDRAM 13 in which one field is stored is called a field bank. In this embodiment, the SDRAM 13 has eight field banks and can store audio data for eight fields.
[0076]
FIG. 17A shows data blocks stored in one field bank. One row in the horizontal direction is a sync block, and an in-sync byte number is assigned to each byte of data constituting the sync block. The sync blocks are arranged in the column direction, and an outer code number is assigned to each. As shown in FIG. 17B, the address assignment of the SDRAM 13 follows a 2-bit ID, a 1-bit Conf / Adv value, a 6-bit outer code number, a 3-bit field bank value, a 3-bit channel number, and a 6-bit channel number. It consists of a total of 21 bits of byte numbers in the sync of bits.
[0077]
FIG. 18 shows an example of the configuration of the sync block on the SDRAM 13. As shown in FIG. 18A, the sync block is composed of PS number 0, PS number 1, AIX 0, AIX 1, DID, and data on the SDRAM 13.
[0078]
PS number is an abbreviation for path number. PS numbers 0 and 1 are used to determine that data is old when new data is not written on the SDRAM 13 by a head clog or the like. PS numbers 0 and 1 are simply incremented every 8 fields (every period of the field bank of the SDRAM 13). That is, the 16-bit numerical values from 0 to 65535 sent from the timing generation block 10 are stored in the PS numbers 0 and 1. Rsv is an abbreviation for Reserved and stores dummy data.
[0079]
FIG. 18B shows the bit assignment of AIX0. Bits 7 and 6 and bits 4 to 0 are reserved. FabSYNC of bit 5 is a bit that is set when there is a high possibility that this sync block is not a normal sync block because the distance between the sync blocks is disturbed at the time of inner code correction.
[0080]
FIG. 18C shows the bit assignment of AIX1. Jump is used at the time of variable speed reproduction for reproducing at a speed different from that at the time of recording. During variable speed reproduction, the value is set to 1 when a DT (Dynamic Tracking) head flies by one field. TapeDir is the tape running direction, and is 1 for forward and 0 for reverse. The value of the inner code error is set to 1 in the case of a sync block that is regarded as an error at the time of inner code correction.
[0081]
Note that the DID itself already stored in FIG. 7 is stored as the DID.
[0082]
The sync block stored in the SDRAM 13 is the above-described PS numbers 0 and 1, AIX 0 and 1, and DID with respect to the data in one row in the horizontal direction in FIG. 3 to FIG. 5 or FIG. 8 to FIG. It is set as the structure which added each additional information which consists of.
[0083]
As described above, an in-sync byte number is assigned to each byte in the sync block. In this embodiment, the SDRAM 13 is 32 bits wide. Therefore, the sync block data is provided with an address every 4 bytes as shown in FIG. Therefore, on the SDRAM 13, the address is assigned by the upper 6 bits ([7: 2]) of the in-sync byte number.
[0084]
As shown in FIG. 18B, the address of the SDRAM 13 is created and written using Adv / Conf, the outer code number, the field bank and channel number, and the in-sync byte number. Adv / Conf makes a determination based on information attached by the system when the inner code corrected data arrives at the deshuffling unit 11. The field bank is the Adv / Conf Wr field bank number itself supplied from the timing generation block 10.
[0085]
In the byte number in the sync, numbers 0 to 7 are assigned as the numbers for the additional information. On the other hand, the data number is determined by offsetting and incrementing the value when the data with the inner code corrected is supplied. The additional information for the inner code corrected data is only ID0 and ID1 shown in FIG. 7, and there is no information on the outer code number and the channel number. Therefore, the channel deshuffling RAM 14 and the sync deshuffling RAM 15 are used to generate the outer code number and the channel number from the information of ID0 and ID1.
[0086]
Processing in the channel deshuffling RAM 14 will be described with reference to FIG. First, the in-track sector number is generated from the ID0 sync number and ID1 upper / lower information. The in-track sector number is obtained by numbering the audio sectors in one track in the head trace order.
[0087]
As shown in FIG. 21, ID0 is assigned in ascending order in the head trace direction in each upper / lower audio sector. Accordingly, the sector number in the track can be obtained from the upper / lower of ID1 and ID0. In the example of FIG. 21, if ID0 is [24h], ID1 and upper / lower is [1], the in-track sector number is [6].
[0088]
The channel deshuffling RAM 14 stores a deshuffling table in which the channel number is returned as a return value when the in-track sector number and the SEG number of ID1 are given as addresses. These values are supplied as addresses from the deshuffling unit 11 to the channel deshuffling RAM 14, and the corresponding channel numbers are output from the RAM 14. The deshuffling table stored in the channel deshuffling RAM 14 can be rewritten by a system controller (not shown). By changing the deshuffling table according to the data format, any format change can be handled.
[0089]
FIG. 22 shows an example of bit allocation of the track sector number and SEG number supplied to the channel deshuffling RAM 14. As shown in FIG. 22A, the number of bits required for each value differs in each of the formats SD1 to SD4. In this embodiment, bit allocation is performed for each format, as shown in FIG. 22B.
[0090]
The processing in the sync deshuffling RAM 15 will be described with reference to FIG. When the sync deshuffling RAM 15 gives the sector number in the channel field and the sync number in the sector as addresses, it returns the outer code number as a return value. The sector number in the channel field is a number indicating the sector number in the same channel and the same field with the sector of azimuth 0 and 1 as a pair. For example, in the example of FIG. 21 described above, each sector of Seg1 becomes the second sector when the sectors of azimuth 0 and 1 are counted as a pair in the same channel and the same field. Accordingly, the sector number 1 in the channel field is obtained by counting 0, 1, and 2.
[0091]
Similarly, since Seg2 is the first sector of the new field, the sector number in the channel field is 0.
[0092]
FIG. 24 shows the bit assignment of the sector number in the channel field, the azimuth number, the sync number in the sector, and the outer code number in each of the formats SD1 to SD4. In the case of SD2 and SD3, the sector number in the channel field and the Seg number are the same value of 1 bit. In the case of SD4, the sector number in the channel field and the Seg number are the same value of 2 bits. On the other hand, in the case of SD1, as can be seen from FIG. 11 described above, the same channel enters the upper and lower even within the same track. Therefore, the sector number in the channel field is the same 1-bit value as upper / lower of ID1.
[0093]
In FIG. 24, the in-sector sync number is a number indicating the number of sync blocks counted in the head trace order in the same sector. In the example of SD2 in FIG. 21, there are 9 sync blocks in each sector, and the sync number in the sector is obtained from the lower 4 bits of ID0. As described above, when the sector number in the channel field, the azimuth number and the sync number in the sector thus obtained are given as addresses from the deshuffling unit 11 to the sync deshuffling RAM 15, the sync deshuffling is performed. An outer code number is returned from the RAM 15 to the deshuffling unit 11 as a return value.
[0094]
25 and 26 show more specific examples of obtaining the outer code number as described above. FIG. 25A is an example of the format SD1, and FIG. 25B is an example of the format SD4. FIG. 26 shows an example of the format SD2.
[0095]
The deshuffling table stored in the sync deshuffling RAM 15 can be rewritten by a system controller (not shown). By changing the deshuffling table according to the data format, any format change can be handled.
[0096]
As shown in FIG. 24B, the number of bits required for the sector number in the channel field and the sync number in the sector differ between the formats SD1 to SD3 and SD4. However, since the total necessary number of bits added to these bits is the same, when the address is generated, the necessary number of bits can be finally saved by changing the bit allocation according to the format. Bit allocation according to the format is instructed by a system controller (not shown).
[0097]
In this way, the channel deshuffling RAM 14 and the sync deshuffling RAM 15 are used to obtain values necessary for address calculation of the SDRAM 13 in the deshuffling unit 11. The determined address is sent to the SDRAM controller 12 together with the data. Data is written into the SDRAM 12 according to the address sent under the control of the SDRAM 12 controller 12. The address assignment of the SDRAM 13 is written in the SDRAM 13 after being arranged and arranged by Conf / Adv, by field bank, by channel, and by the outer code number, so that later processing such as outer code correction becomes easy.
[0098]
The AOT block 16 controls reading of the SDRAM 13, extraction of an error flag from the read data, control of the outer code RAMs 17A and 17B, outer code correction, write control of the rate conversion RAMs 18A to 18H, and AUX data It has a function of sampling.
[0099]
FIG. 27 shows a timing chart of audio processing performed by the AOT block 16. A control signal (Fld-Start) having a field period is supplied from the timing generation block 10 (FIG. 27A). The signal Fld-Start is, for example, a pulse signal that is output at the change of field. In the AOT block 16, various processes are performed based on this signal. In the following description, a field that starts immediately after the signal Fld-Start is set as a new field, and a field before the signal Fld-Start is set as an old field.
[0100]
As a schematic processing flow, as described above, data is read from the SDRAM 13 by the AOT block 16 and written to the outer code RAM 17A or 17B (FIG. 27B). Then, the outer code correction is performed on the data written in the outer code RAM 17A or 17B. The data subjected to the outer code correction is read from the outer code RAM 17A or 17B (FIG. 27C) and written to the corresponding one of the rate conversion RAMs 18A to 18H (FIG. 27D). Data written in the rate conversion RAMs 18A to 18H is read out in a time-sharing manner for each channel based on a predetermined clock.
[0101]
The AOT block 16 calculates the bank corresponding to the new field among the field banks of the SDRAM 13. This is calculated based on information supplied from the timing generation block 10 as an Adv / Conf RdFld bank number. Then, an error flag is read from the data stored in the bank. Data is read from the bank and written to the corresponding side of the outer code RAM 17A or 17B. The AOT block 16 uses the error flag read from the SDRAM 13 to correct the outer code for the data written in the outer code RAM 17A or 17B (the process of “A” in FIG. 27B).
[0102]
These processes will be described in more detail. The address of the SDRAM 13 having the corresponding field bank number is designated by the AOT block 16. This address is sent from the AOT block 16 to the SDRAM controller 12. The SDRAM controller 12 reads data from the SDRAM 13 according to this address.
[0103]
As shown in FIGS. 27F to 27I, the outer code correction processing is divided into slots and is performed in a time division manner. In FIG. 27, only Adv out of the two signal systems Adv and Conf is shown. In FIG. 27F to FIG. 27I, “Conf” indicates a slot for processing the Conf system, and it can be seen that Adv and Conf are alternately processed in a time division manner.
[0104]
The slot is further divided into smaller slots. First, Ps numbers 0 and 1, AIX0 and 1, DID, D0 to D11 are read for data with an even outer code number of channel 0. At this time, the error flag of bit 0 of AIX1 is stored in the register. When the error flag is determined, the Adv / Conf path number supplied from the timing generation block 10 is compared with the path number read from the SDRAM 13, and if they are different, it is determined that old data remains, and those old Data sync blocks are treated as errors.
[0105]
FIG. 28 shows how the pass number (PS number) is written and read. 28A and 28B are charts at the time of writing. 28C and 28D are charts at the time of reading. When writing to the SDRAM 13, the Adv / Conf light field number supplied from the timing generation block 10 to the deshuffling unit 11 is compared with the pass number. Based on the comparison result, each time the data with the inner code corrected is supplied, the data is written with the pass number attached to the address of the SDRAM 13 of the corresponding field bank number.
[0106]
Here, if all sync block data for one field has been received, all the pass numbers are updated to new ones. On the other hand, if there is sync block data that has not arrived, that portion of the SDRAM 13 is not updated. At that time, the pass number is not updated and the old value is entered.
[0107]
The pass number information to be read from the SDRAM 13 is supplied from the timing generation block 10 to the AOT block 16. If the supplied pass number is different from the pass number of the corresponding part of the SDRAM 13, it is determined that the data on the SDRAM 13 is old data that has not been updated. In the example of FIG. 28, Ps number 297 and Ps number 298 are mixed in bank 2, and it can be seen that there is a sync block that has not been updated.
[0108]
As described above, even in the case of data that has not been updated, the outer code is corrected as usual, mainly using old data. In order to prevent this, when there are more than a certain number of unupdated sync blocks, normal outer code correction is prohibited and outer code correction mainly using old data is prevented. However, erasure correction is possible. In this embodiment, it is determined whether the sync block has been updated using the Ps number, and unupdated data is treated as an error. The data added with the outer code parity after the data D0 in the sync block is temporarily stored in the outer code RAM 17A or 17B.
[0109]
FIG. 29 shows an example of address assignment of the outer code RAMs 17A and 17B. In the figure, a dummy is a meaningless area that is not actually used but has occurred in address assignment. In FIG. 29, the byte numbers given in the row direction are given for convenience of explanation, and are numbers in byte units. In the column direction, outer code numbers are assigned. First, the processing of the portions denoted by Ch0 and Evn in FIGS. 27F to 27H is performed. Here, processing is performed on data of channel 0 having an even outer code number.
[0110]
The data read from the SDRAM 13 is written in the outer code RAM 17A, for example. Then, byte numbers 0 to 11 are filled in FIG. Next, data is read from the outer code RAM 17A one by one (ie, one byte number) in the vertical direction (column direction) of FIG. An error flag stored in the above-described register is added to the read data. Then, the outer code correction is performed by the AOT block 16 on the data read from the outer code RAM 17A and added with the error flag. The outer code correction is performed on the 12-byte number in FIG. 29, that is, 12 pieces of data in the column direction.
[0111]
In this embodiment, the decoder 1 is provided with outer code RAMs 17A and 17B. Out of these, the outer code RAM 17A corresponds to the Adv system, and the outer code RAM 17B corresponds to the Con system.
[0112]
The data subjected to outer code correction is written in the rate conversion RAMs 18A to 18H. Referring to FIGS. 27F to 27I, in the Adv series, processing of data with an even outer code number of channel 0 continues from processing of data with an odd outer code number of channel 0. In the same manner, the processing of channels 1, 2,... In this manner, the outer code corrected data is stored in the corresponding one of the rate conversion RAMs 18A to 18H. In this example, Adv series channels 0 and 1, channels 2 and 3, channels 4 and 5, and channels 6 and 7 are stored in rate converter RAMs 18A, 18B, 18C, and 18D, respectively.
[0113]
FIG. 30 shows an example of address assignment of the rate conversion RAMs 18A to 18H. A byte number is assigned in the row direction, and the column direction corresponds to the outer code number. As described above, in this embodiment, two types of audio data, one sample being 16 bits and one sample being 24 bits, are handled. With these two types of data, the storage methods for the rate conversion RAMs 18A to 18H are different from each other. For one sample of 16 bits (2 bytes) of data, such as byte numbers 0 and 1, for example, two byte numbers are set as one set, and the data is packed in the row direction. On the other hand, for one sample of 24 bits (3 bytes) of data, for example, byte numbers 0, 1, and 2, one set of three byte numbers is packed in the row direction.
[0114]
Further, the rate conversion RAMs 18A to 18H are composed of three banks of banks 0, 1, and 2. Each of these banks 0, 1 and 2 can store the data portion excluding the outer code parity for 12 rows in the outer code RAMs 17A and 17B shown in FIG. In FIG. 27E described above, the numbers written in the squares indicate the bank numbers. The rate conversion RAMs 18A to 18H are cyclically read. Therefore, as shown in FIG. 27E, the bank numbers are also cyclically switched to 0, 1, 2, 0, 1, 2,.
[0115]
On the other hand, in FIG. 27B, the numbers (for example, 2, 0) written on the lines indicating the write timing for each outer code RAM 17 are written to the outer code RAM 17A or 17B, and from the outer code RAM 17A or 17B. The bank numbers for reading and writing to the rate conversion RAMs 18A to 18H are shown. In each of the rate conversion RAMs 18A to 18H, control is performed so that writing and reading do not overlap in time.
[0116]
After the process of “A” in FIG. 27B, the process proceeds to a process marked “B”. In “B”, the processing subsequent to D0 to D11 described above is performed. That is, the 24-byte number composed of D12 to D25 is read from the SDRAM 13 in the same manner as described above. The read data is written to all 24 byte numbers in the outer code RAM 17A or 17B. Then, the data is subjected to outer code correction and written in the corresponding ones of the rate conversion RAMs 18A to 18H. In the example of FIG. 27, for example, data is written in banks 0 and 1 of the rate conversion RAM 18A. In this way, the process is subsequently performed in the order of D26 to D49, D50 to D73, and so on, and data for one field is processed.
[0117]
Returning to FIG. 16, the reading of the rate conversion RAMs 18 </ b> A to 18 </ b> H is controlled by the RC block 19. Reading from the rate conversion RAMs 18A to 18H is controlled by the RC block 19, and a total of 16 channels of audio data of channels 0 to 7 of the Adv system and channels 0 to 7 of the Conf system are supplied to the AIF block 20 in a time division manner. .
[0118]
FIG. 31 schematically shows a time division process of data transmission from the RC block 19 to the AIF block 20. FIG. 31 illustrates an example of audio data in which one sample is 24 bits. The sample top signal shown in FIG. 31A is a signal having an FS cycle corresponding to a sample cycle having a frequency of 48 KHz. With this sample top signal, a break for each sample of audio data transmitted as shown in FIG. 31B is identified. The data is transmitted with a data and an error flag and a bit width of 9 bits. Data for 16 channels of Adv series and Conf series are time-division multiplexed and transmitted.
[0119]
FIG. 31C and FIG. 31D show the 1FS period in FIG. 31A and FIG. 31B in more detail. Data of 24 bits / sample is handled by MSB (most significant byte), MDB (intermediate byte) and LSB (least significant byte) each having 8 bits. First, each of these MSB, MDB and LSB is output every 4 clocks with a clock (ck) which is 256 times faster than the FS cycle. First, the data of Adv series channel 0 is output, then the data of Adv series channels 2, 4, and 6 are sequentially output in the same manner, and further the data of channels 0, 2, 4, and 6 of the Conf series are output. Are output in order. Subsequently, data of Adv series channels 1, 3, 5, and 7 are output in order, and further, data of Conf series channels 1, 3, 5, and 7 are output in order. Each channel has an interval of 16 clocks. In this way, a total of 16 channels of audio data of Adv series channels 0 to 7 and Conf series channels 0 to 7 are transmitted to the AIF block 20 in a time division manner.
[0120]
FIG. 32 shows an example of the configuration of the AIF block 20. In the AIF block 20, the 16 channels supplied as parallel data from the RC block 19 are converted into serial data according to, for example, the AES / EBU standard for each channel. The AIF block 20 performs data correction based on an error flag attached to the supplied audio data, simple mute processing, filter processing (shuttle filter) at the time of variable speed reproduction, inclination level control processing, and the like.
[0121]
First, each process of data modification, simple mute, and shuttle filter will be schematically described with reference to FIG. In FIG. 33, “× (X)” indicates a sample that should originally have data but has been lost due to an error, and “Δ (triangle)” indicates actually complemented data. . In addition, “◯ (circle)” indicates a normal sample.
[0122]
FIG. 33A shows the data modification process. In this way, data correction is performed by complementing error data by taking the average of previous and subsequent samples. FIG. 33B shows a simple mute process. Simple mute performs simple mute when an error continues, or when playback is stopped by a video tape recorder, for example, and mute is necessary. The held normal data is shifted and the data value is reduced by half. Thereby, simple mute is performed. FIG. 33C shows shuttle filter processing. The shuttle filter reduces noise caused by data jumping and data steeply changing during shuttle playback in which playback is performed at a speed different from that during recording. The average of the data at that time and the next sample data is obtained, and the result data is output as processed sample data.
[0123]
FIG. 34 is a diagram for explaining the inclination level control process. The inclination level control process is a transitional state when a sound is generated from the mute state, so as not to have a steep waveform. For example, as shown in FIG. 34A, when the waveform becomes steep at the rising edge, a pulse-like noise “puchi” is generated at that time. In order to prevent this, the data value is gradually inclined so as not to have a steep waveform. Specifically, the upper 8 bits of the audio sample are initially shifted by 8 bits to a state of [0], and the shift amount is gradually decreased to increase the value by 2 times. Accordingly, as shown in FIG. 34B, the data level is controlled with a slope.
[0124]
In FIG. 32, the audio data input to the AIF block 20 is supplied to the delay circuit 201 and also to the first input terminal of each of the average value circuits 204 and 205, the selector control circuit 202. The delay circuit 201 delays the supplied data and the error flag by one FS cycle (that is, one sample). The data delayed by the delay circuit 201 and the error flag are supplied to the hold register unit 203, the second input terminals of the average value circuits 204 and 205, the slope level control circuit 206, and the selector control circuit 202, respectively.
[0125]
The error flags are stored in the registers of the Adv system channels 0 to 7 and the Conf system channels 0 to 7, respectively, provided in the hold register unit 203.
[0126]
To the selector 208, an error-free output from the delay circuit 201 is supplied as current data. The outputs of the hold register unit 203, the average value circuits 204 and 205, and the inclination level control circuit 206 are supplied to the selector 208, respectively. In the selector 208, the selection of the selection input terminal is controlled by the selector control circuit 202 based on the state of the error flag, and processing for audio data is selected.
[0127]
When there is an error flag and data correction processing is required, the average value circuit 204 calculates an average value from the output of the hold register unit 203 and the data directly supplied from the RC block 19, and the result Is used as modified data.
[0128]
When simple mute is required, the hold data held by the hold register unit 203 is output, and then the data is shifted by the 1/2 circuit 207 to reduce the data value to 1/2. Then, the hold data is recursively decreased by 1/2 so that the data is stored in the hold register unit 203, and simple mute is performed.
[0129]
The shuttle filter process is performed by always calculating the average value of the current data and the data supplied from the RC block 19 by the average value circuit 205 and using the result.
[0130]
The slope level control circuit 206 performs slope level control by controlling the shift amount of the upper 8 bits of the input data as necessary. For example, when the mute process is canceled by pressing the play button or the like, the control by the inclination level control circuit 206 is performed. For example, the hold register unit 203 is selected by the selector 208, and the mute process is performed by the simple mute process. When the mute is released, the inclination level control circuit 206 is selected by the selector 208, and the inclination level control is started. By the inclination level control, the sound is gradually started up from the silent state to the voiced state.
[0131]
A method of controlling the inclination level will be described with reference to FIG. In FIGS. 35A and 35B, the left side is a sample input earlier in time. “H” indicates that the notation is hexadecimal notation. Of the four digits in hexadecimal notation, the upper 2 digits indicate the upper 8 bits, and the lower 2 digits indicate the lower 8 bits.
[0132]
FIG. 35A is an example in which the bit shift amount is decreased by 1 for each sample, and the signal level is increased by 2 times. In the first sample of input data, the upper 8 bits are shifted by 8 bits, and the value is set to [0]. As a result, this sample is almost silent. By gradually decreasing the shift amount from here, the slope level control is performed in which the data value gradually increases and the sound rises.
[0133]
In this example, the value [5040h] of the first sample of the input data (upper stage) is shifted to 8 bits by shifting the upper 8 bits [50] to [00]. Therefore, the output data is [0040h] as shown in the lower part thereof. The next sample value [4068h] is shifted to 7 bits by shifting the upper 8 bits [40] to [00], and the output data is [0068h]. In the same manner, for example, the value [1045h] of the fifth sample is [0145h] by shifting the upper 8 bits [10] by 4 bits to [01]. The ninth and subsequent samples are not bit-shifted and the input data is output as it is.
[0134]
Such a bit shift can be easily realized by using, for example, two shift registers capable of 8-bit parallel loading. That is, one is for the upper 8 bits and the other is for the lower 8 bits. The shift register to which the upper 8 bits are input is right-shifted by a predetermined number of bits according to the sample. Shift processing is not performed in the shift register for the lower 8 bits. Then, the outputs of the upper and lower shift registers are latched and 16-bit parallel output is performed. Of course, the present invention is not limited to this configuration, and other configurations can be realized.
[0135]
In the example of FIG. 35A, in this way, the slope level control circuit 206 reduces the bit shift amount by 1 bit over 8 samples after the control is started. Since it does not become a steep waveform, it does not become noise. Further, the present invention is not limited to this example. For example, as shown in FIG. 35B, the signal level can be increased by two times every two samples. The bit shift period changes, the level inclination changes, and level control is performed more gently.
[0136]
In this embodiment, only the upper 8 bits are processed for 16 bits of data per sample. For example, when the data is D / A converted into an analog audio signal, the lower 8 bits correspond to a minute level and hardly cause noise. Since only the upper 8 bits are processed, the circuit is simplified. Since the circuit configuration is simple, it can be incorporated as a part of the configuration of the AIF block 20 together with a configuration for performing data correction, for example.
[0137]
The selector control circuit 202 monitors the status of the error flag, and selects each output of the hold register unit 203, the average value circuits 204 and 205, the gradient level control circuit 206, and the delay circuit 201 based on the status. Thereby, the simple mute processing, data modification processing, shuttle filter processing, inclination level control processing, and no processing (current data) are appropriately selected.
[0138]
The register group 209 corresponds to the channels 0/1, 2/3, 4/5, and 6/7 of the Adv system, and the channels 0/1, 2/3, 4/5, and 6/7 of the Conf system, respectively. It has 8 registers. The audio data supplied from the selector 208 by time division is temporarily stored in the corresponding registers of the register group 209, respectively. The audio data output from each of the registers of the register group 209 is sent to the P / S register group 210, and the registers are shifted to perform parallel / serial conversion. Then, audio data converted into serial data is output for each system and channel. Data is output as one signal for every two channels.
[0139]
In the above description, the present invention is applied to the digital video tape recorder VTR. However, the present invention is not limited to this example. The present invention can be applied to an audio recording / reproducing apparatus that performs only recording / reproducing of digital audio data, for example. In the present invention, recording and reproduction are not indispensable configurations, and can be applied to digital audio equipment that does not perform recording and reproduction.
[0140]
【The invention's effect】
As described above, according to the present invention, the input data is controlled so that the bit shift amount is reduced for each sample after the upper 8 bits are first shifted by 8 bits. The waveform is not steep, and there is an effect of eliminating noise when the mute of the audio signal is released.
[0141]
In addition, according to the present invention, since the inclination level control of digital audio data is performed by bit shift, there is an effect that the circuit configuration is simplified.
[0142]
Furthermore, since the circuit configuration is simplified, for example, a circuit that performs slope level control can be easily incorporated in the same block as the data correction circuit that is incorporated in the error correction decoder. Therefore, for example, even in a camera-integrated video tape recorder in which an IC dedicated for audio processing or the like is not incorporated, there is an effect that an audio signal can be tilted up.
[0143]
Furthermore, according to this embodiment, there is an effect that the amount of inclination at the time of starting up the inclination can be easily realized only by changing the bit shift period.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a recording side according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the configuration of the playback side according to the embodiment of the present invention.
FIG. 3 is a schematic diagram showing the types of audio error correction blocks that can be supported by the recording / reproducing apparatus according to the embodiment;
FIG. 4 is a schematic diagram showing types of audio error correction blocks that can be supported by the recording / reproducing apparatus according to the embodiment;
FIG. 5 is a schematic diagram showing types of audio error correction blocks that can be supported by the recording / reproducing apparatus according to the embodiment;
FIG. 6 is a schematic diagram illustrating a structure of a sync block.
FIG. 7 is a schematic diagram showing bit assignment of ID and DID in a sync block.
FIG. 8 is a schematic diagram showing a layout in an error correction block for audio of one channel and one field when frame (field) frequencies are 29.97 Hz and 59.94 Hz.
FIG. 9 is a schematic diagram showing a layout in an audio error correction block when a frame (field) frequency is 25 Hz / 50 Hz.
FIG. 10 is a schematic diagram illustrating a layout in an audio error correction block when a frame frequency is 23.976 Hz.
FIG. 11 is a schematic diagram illustrating an example of channel allocation on a footprint in the format SD1.
FIG. 12 is a schematic diagram illustrating an example of channel allocation on a footprint in the format SD2.
FIG. 13 is a schematic diagram illustrating an example of channel allocation on a footprint in the format SD3.
FIG. 14 is a schematic diagram illustrating an example of channel allocation on a footprint in the format SD4.
FIG. 15 is a schematic diagram showing audio outer code number allocation in each format;
FIG. 16 is a block diagram showing an example of a configuration of an audio decoder according to the present invention.
FIG. 17 is a schematic diagram for explaining address assignment of SDRAM;
FIG. 18 is a schematic diagram for explaining address assignment of SDRAM;
FIG. 19 is a schematic diagram for explaining address assignment of SDRAM;
FIG. 20 is a schematic diagram for explaining processing in a channel deshuffling RAM;
FIG. 21 is a schematic diagram for explaining a method for obtaining a sector number in a track;
FIG. 22 is a schematic diagram illustrating an example of bit allocation between a sector number in a track and an SEG number supplied to a channel deshuffling RAM;
FIG. 23 is a schematic diagram for explaining processing in a sync deshuffling RAM;
FIG. 24 is a schematic diagram showing bit assignment of a sector number in an channel field, an azimuth number, a sync number in a sector, and an outer code number in each format.
FIG. 25 is a schematic diagram illustrating a more specific example of obtaining an outer code number.
FIG. 26 is a schematic diagram illustrating a more specific example of obtaining an outer code number.
FIG. 27 is a timing chart of audio processing in an AOT block.
FIG. 28 is a schematic diagram illustrating how a pass number is written and read.
FIG. 29 is a schematic diagram illustrating an example of address assignment of an outer code RAM.
FIG. 30 is a schematic diagram illustrating an example of address assignment of a rate conversion RAM;
FIG. 31 is a schematic diagram schematically illustrating time division processing for data transmission from an RC block to an AIF block;
FIG. 32 is a block diagram illustrating an example of a configuration of an AIF block.
FIG. 33 is a schematic diagram for schematically illustrating each process of data modification, simple mute, and shuttle filter.
FIG. 34 is a schematic diagram for explaining an inclination level control process;
FIG. 35 is a schematic diagram for explaining inclination level control processing;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Decoder, 11 ... Deshuffling part, 13 ... SDRAM, 14 ... Channel deshuffling RAM, 15 ... Sync deshuffling RAM, 16 ... AOT block, 17A, 17B: RAM for outer codes, 18A to 18H: RAM for rate conversion, 19: RC block, 20: AIF block, 133: Inner code decoder, 124: ID interpolation circuit, 151: Deshuffling circuit, 152 ... Outer code decoder, 201 ... Delay circuit, 202 ... Selector control circuit, 203 ... Hold register unit, 204 ... Average value circuit, 205 ... Average value circuit, 206... Slope level control circuit, 208... Selector, 209... Register group, 210.

Claims (3)

In an audio signal processing apparatus for processing a digital audio signal,
When starting from the silent state to the voiced state, only the upper bits of the input audio data are bit-shifted to the lower side, and the amount of the bit shift is reduced with time from the start-up to reduce the audio. An audio signal processing apparatus characterized by adding a slope to a data level. In a video signal recording / reproducing apparatus adapted to reproduce video data and audio data recorded on a recording medium by performing error correction encoding using video codes and audio data, respectively, on a recording medium,
Recording means for performing error correction encoding using product codes on the input video data and audio data, and adding ID information and a synchronization signal to record on the recording medium;
The video data and audio data recorded on the recording medium are reproduced, and the reproduced video data and audio data are subjected to error correction coding by the product code based on the synchronization signal and the ID information, respectively. Playback means for decoding;
When the audio data reproduced by the reproduction means is raised from a silent state to a voiced state, only the upper bits of the audio data are bit-shifted to the lower side, and the amount of the bit shift is And a means for inclining the level of the audio data by decreasing with time. In an audio signal processing method for processing a digital audio signal,
When starting from the silent state to the voiced state, only the upper bits of the input audio data are bit-shifted to the lower side, and the amount of the bit shift is reduced with time from the start-up to reduce the audio. An audio signal processing method characterized by adding a slope to a data level.

Images