JP4182963B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor package called a COF (Chip On Film) structure in which a substrate and a semiconductor element are connected by a flip-flop method.

FIG. 6 is a bottom view of a semiconductor element in a conventional COF structure, and FIGS. 7A and 7B are a top view of a substrate in a conventional COF structure and a cross-sectional view taken along line AA ′. FIG. 8 is a cross-sectional view taken along the line AA ′ showing the connection state between the substrate and the semiconductor element in the conventional example, and FIG. 9 is a cross-sectional view taken along the line AA ′ showing the sealed state in the COF structure of the conventional example. A conventional COF structure is shown below.

As shown in FIG. 6, a bump electrode 2 is formed on the lower surface of the semiconductor element 1. Usually, the bump electrode 2 is formed in the peripheral part in the semiconductor element 1.

As shown in FIGS. 7A and 7B, a plurality of wirings 4 are formed on the substrate 3, and the substrate 3 and the wirings 4 are covered with an insulating film 5. Usually, a flexible polyimide film having a thickness of 25 · m or 40 · m is used for the substrate 3, but the thickness of the substrate 3 here can be set as appropriate. The wiring 4 is formed by sputtering a barrier metal 6 (nickel [Ni] and chromium [Cr], or nickel [Ni] and copper [Cu]) on the surface of the substrate 3, and depositing copper on the barrier metal 6 by a plating method. Are formed by photolithography and etching. At least the wiring 4 at the bump electrode connection position 7 is tin-plated. The wiring 4 extends from the periphery of the substrate 3 to the semiconductor element mounting area 8, and the wiring 4 at the bump electrode connection position 7 is located in the semiconductor element mounting area 8 so as to correspond to the bump electrode 2 of the semiconductor element 1. Yes. The insulating film 5 is formed so as to expose at least the semiconductor element mounting region 8. As shown in FIG. 9, when the space between the substrate 3 and the semiconductor element 1 is sealed with the sealing material 9, the end of the substrate 3 and the semiconductor element 1 serving as an inlet for the sealing material 9 is used. This is to keep the space between the parts and facilitate the injection of the sealing material 9.

As shown in FIG. 8, the wiring 4 at the bump electrode connection position 7 on the substrate 3 and the bump electrode 2 formed on the semiconductor element 1 are aligned and electrically connected by a bonding apparatus. Usually, a thermocompression bonding method or the like is used as a connection method. The thermocompression bonding method is a method in which heat and pressure are applied to the wiring 4 and the bump electrode 2 at the bump electrode connection position 7 to melt the tin plated on the wiring 4 at the bump electrode connection position 7 and connect to the bump electrode 2. It is.

As shown in FIG. 9, the space between the substrate 3 and the semiconductor element 1 is sealed with a sealing material 9 injected from between the substrate 3 and the end of the semiconductor element 1. Usually, a resin is used for the sealing material 9.

FIG. 10 is a cross-sectional view taken along line AA ′ of the COF structure in the conventional example when an edge short circuit occurs. As shown in FIG. 10, in the conventional COF structure, when the wiring 4 and the bump electrode 2 are thermocompression bonded, the substrate 3 may be deformed as indicated by reference numeral 10 due to heat or pressure. In this case, since the wiring 4 located below or around the semiconductor element 1 is not covered with the insulating film 5, the wiring 4 is in contact with the semiconductor element 1 at a location indicated by reference numeral 10. There is a possibility that a problem of edge short-circuit between the semiconductor element 1 and the semiconductor element 1 may occur.

In the present invention, by extending the insulating film covering the wiring on the substrate to the lower side of the semiconductor element, the substrate is deformed by thermocompression bonding, and the wiring contacts the part other than the semiconductor element and the bump electrode. However, since the wiring is covered with an insulating film, the possibility of an edge short circuit is reduced.

By extending the insulating film to the lower side of the semiconductor element, the substrate is bent due to heat and pressure during thermocompression bonding, and the wiring is covered with the insulating film even if the wiring contacts the end of the semiconductor element. The occurrence of edge shorts is reduced and the quality reliability is improved. Further, a notch for injecting a sealing material is provided in the insulating film, and when sealing between the substrate and the semiconductor element, the substrate is warped and the gap between the substrate and the end of the semiconductor element is widened. Therefore, the sealing material can be easily injected, and even a sealing material with low fluidity can be sealed. Therefore, the width of the sealing material that can be selected is widened, and the degree of freedom in design is increased.

Reference forms in the COF structure of the present invention will be described below. In the COF structure, a semiconductor element is formed on a wiring board, the substrate and the semiconductor element are electrically connected by a conductor, and the space between the wiring board and the semiconductor element is made of resin to protect the conductor. A structure that is sealed.

Figure 1 is a bottom view of the semiconductor device in the COF structure reference embodiment of the present invention, FIG. 2 (a), (b) is a top view of the substrate COF structure reference embodiment of the present invention, A-A' FIGS. 3A and 3B are cross-sectional views taken along line AA ′ and BB ′ in a state where the substrate and the semiconductor element are connected and sealed in the COF structure according to the embodiment of the present invention. FIG. 4 is a cross-sectional view taken along line AA ′ of the COF structure when the substrate is bent in the COF structure according to the reference embodiment of the present invention.
As shown in FIG. 1, a bump electrode 2 is formed on the lower surface of the semiconductor element 1.

Next, before explaining the substrate 3, for convenience of explanation, the substrate 3 is divided into three regions as shown in FIGS. A region in which the semiconductor element 1 is mounted is a first region 8a, a periphery thereof is a second region 8b, and a central portion of the first region 8a is a third region 8c (this third region 8c As described in (1), since it is an area where the wiring is exposed, it may be referred to as a wiring exposed area).

As shown in FIGS. 2A and 2B, the wiring 4 extending from the second region 8b to the third region 8c is formed on the substrate 3, and the wiring 4 at the bump electrode connection position 7 is formed in the third region 8c. A plurality of wirings 4 are formed so as to be positioned. For example, a flexible plastic insulating film such as polyimide or polyester is used for the substrate 3, but the thickness and material of the substrate 3 can be appropriately set. The wiring 4 is formed on the substrate 3 through a barrier metal 6 layer. A barrier metal 6 (nickel [Ni] and chromium [Cr], or nickel [Ni] and copper [Cu]) is sputtered on the surface of the substrate 3, and copper is deposited on the barrier metal 6 by a plating method to form a copper foil. By photolithography and etching, a plurality of wirings 4 are formed close to each other at a predetermined pitch. At least the wiring 4 at the bump electrode connection position 7 is tin-plated.

The substrate 3 and the wiring 4 are covered with an insulating film (for example, solder resist, epoxy resin) 5. The insulating film 5 is used to reduce the possibility that foreign matter enters the wiring 4 from the outside, and to reduce the possibility that the wiring 4 contacts the semiconductor element 1 or the like at a place other than a predetermined portion and short-circuits. Is provided. Further, when sealing the space between the substrate 3 and the semiconductor element 1, a notch for injecting the sealing material into a predetermined portion of the insulating film 5 is provided so that the injection of the sealing material is facilitated. Part 11 is provided.

The insulating film 5 is formed in the first region 8a and the second region 8b excluding the third region 8c and the notch 11. Here, as described above, the insulating film 5 only needs to cover at least the wiring 4 for the purpose. However, in order to improve the strength of the substrate 3, the insulating film 5 is formed on the wiring 4 excluding the third region 8c. It is desirable to cover the entire area of the substrate 3 including it. That is, the insulating film 5 covering the wiring 4 has a function as a reinforcing plate for supporting the substrate 3 as well as a function of insulating the wiring 4 from the surroundings. Furthermore, in this case, if the insulating film 5 is composed of a solder resist used in the conventional process, only the size of the opening area of the conventional solder resist (area corresponding to the third area 8c) is changed. Therefore, it can be applied to this embodiment. Therefore, the present invention can be realized without significantly changing the conventional process, that is, without significantly increasing the cost.

The cutout portion 11 is provided in a region other than on the wiring 4 of the insulating film 5 so as to extend from the boundary line 8'c of the third region 8c to the second region 8b. The notch 11 is used to seal the space between the substrate 3 and the semiconductor element 1, or to discharge the air between the substrate 3 and the semiconductor element 1 in order to inject a sealing material. It functions as an exhaust port. Considering the ease of flow of the injected sealing material, a structure in which air in the space between the substrate 3 and the semiconductor element 1 is easily discharged when the sealing material is injected is preferable. It is preferable to provide each of the cutout portions so that the cutout portions serving as the exhaust ports are located at positions as far as possible from the cutout portions serving as the injection ports in at least two places. For example, the notch 11 provided in the longitudinal direction of the substrate 3 so as to be symmetric with respect to the center of the substrate 3 or the notch provided so as to be diagonal to the center of the substrate 3. Part 11 or the like is preferable. In order to facilitate the injection of the sealing material, it is preferable that the width of the notch in the boundary line 8 ′ c is as long as possible within the pitch of the wiring 4. That is, the size of the inlet is made as wide as possible. The notch 11 shown in FIG. 2A is an example of the notch 11 having a preferable position and shape.

As shown in FIGS. 3A and 3B, the wiring 4 in the third region 8c on the substrate 3 and the bump electrode 2 formed on the semiconductor element 1 are aligned by a bonding apparatus, and are bonded by a thermocompression bonding method. Electrically connected, the semiconductor element 1 is mounted on the first region 8 a on the substrate 3. The space between the substrate 3 and the semiconductor element 1 is sealed with a sealing material (for example, epoxy resin, silicone resin, etc.) 9 injected from the notch 11.

As described above, in the reference embodiment of the present invention, since the insulating film 5 extends to the lower side of the semiconductor element 1, the substrate 3 is heated and pressured when the wiring 4 and the bump electrode 2 are thermocompression bonded. However, even when the wiring 4 is deformed as indicated by reference numeral 10 in FIG. 4 and the wiring 4 is in contact with the end portion of the semiconductor element 1, since the wiring 4 is covered with the insulating film 5, the occurrence of edge shorting is reduced. Quality reliability is improved. Further, as a structure for preventing the occurrence of an edge short circuit, a structure in which the wirings 4 are covered with insulation one by one is conceivable. However, in the reference embodiment , a solder resist is used for the insulating film 5 in the reference embodiment . The strength of the substrate 3 is large and the substrate 3 is difficult to bend. In addition, since the insulating film 5 can be formed without significantly changing the conventional process, it can be realized without significant cost increase. Further, since the third region on the upper surface of the substrate 3 is surrounded by the insulating film 5, the sealing material 9 injected into the space between the substrate 3 and the semiconductor element 1 is around the third region. Since it is blocked by the insulating film 5 and hardly flows out around the substrate 3, a predetermined portion can be sealed with an appropriate amount of sealing material.

Further, the notch 11 spreads the gap between the substrate 3 and the end of the semiconductor element 1 by the thickness of the insulating film 5 as shown by reference numeral 12 in FIG. Since sealing is possible even with a sealing material having low fluidity, the width of the sealing material 9 that can be selected is widened, and the degree of freedom in design is increased. In addition, while it spreads, it can be sealed with the sealing material 9 thicker than the thickness of the insulating film 5, and the substrate 3 becomes difficult to bend at that portion, so there is a possibility that an edge short occurs in the notch portion 11. By providing in the part, edge short-circuit can be prevented.

The second embodiment of the present invention relates to another method for manufacturing a semiconductor device having a COF structure. FIG. 5 is a cross-sectional view showing a process at the time of sealing in the semiconductor device manufacturing method according to the second embodiment of the present invention.

In the second embodiment, when the space between the substrate 3 and the semiconductor element 1 is sealed with the sealing material 9, stress is applied to the periphery of the substrate 3 to warp the periphery of the substrate 3 downward. The space between the substrate 3 and the end of the semiconductor element 1 is widened.

The first method for widening the gap between the substrate 3 and the end of the semiconductor element 1 is to place a support base (for example, a convex support base) 13 whose central portion is higher than the surrounding area on the lower side of the substrate 3. The semiconductor device is placed so that the central portion of the substrate is located at the central portion (or also referred to as a top portion or a convex portion) of the support base 13, and the periphery of the substrate 3 is surrounded by the pressing jig (for example, a pin). In this method, the substrate 3 and the support 13 are fixed to bend and the substrate 3 is warped, and the space between the substrate 3 and the end of the semiconductor element 1 is widened.

The second method is to place the substrate 3 on the flexible support base 13 and apply stress to the periphery of the substrate 3 to bend the support base 13 and warp the periphery of the substrate 3 downward. In this method, the space between the substrate 3 and the end of the semiconductor element 1 is widened.

Next, the sealing material 9 is injected from this expanded area (location indicated by reference numeral 14 in FIG. 5) to seal the space between the substrate 3 and the semiconductor element 1. Here, depending on the shape of the support base 13, the central portion of the substrate 3 is lifted and the space between the substrate 3 and the semiconductor element 1 is somewhat narrowed, but the sealing injected from between the substrate 3 and the end portion of the semiconductor element 1. The material 9 easily spreads between the substrate 3 and the semiconductor element 1 by capillary action and can seal a predetermined region, so that the material 9 does not hinder the sealing.

As described above, in the second embodiment of the present invention, the gap between the substrate 3 and the end of the semiconductor element 1 is widened at the time of sealing, thereby facilitating the injection of the sealing material 9 and the fluidity. Since sealing is possible even with the low sealing material 9, the width of the sealing material that can be selected is widened, and the degree of freedom in design is increased.

The sealing method shown here can also be used for a semiconductor device having a COF structure according to a reference embodiment of the present invention.

It is a bottom view of the semiconductor element in the reference form of the present invention. (A), (b) is the top view of the board | substrate in the reference form of this invention, and sectional drawing in AA '. (A), (b) is sectional drawing in AA 'and BB' of the state with which the board | substrate and the semiconductor element were connected and sealed in the reference form of this invention. In the reference form of this invention, it is sectional drawing in AA 'of the COF structure when a board | substrate is bent. It is sectional drawing which showed the process in the case of the sealing of the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention. It is a bottom view of the semiconductor device in a prior art example. (A), (b) is the top view of the board | substrate in a prior art example, and sectional drawing in AA '. It is sectional drawing in AA 'which shows the connection state of the board | substrate and semiconductor element in a prior art example. It is sectional drawing in AA 'which shows the sealing state in the semiconductor device of a prior art example. In the semiconductor device of a prior art example, it is sectional drawing in AA 'when edge short-circuit generate | occur | produces.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Bump electrode 3 Substrate 4 Wiring 5 Insulating film 6 Barrier metal 7 Bump electrode connection position 8 Semiconductor element mounting area 8a First area 8b Second area 8c Third area 9 Sealing material 11 Notch 13 Support stand

Claims (4)

A flexible substrate in which a plurality of wirings are formed on the surface so as to extend from the periphery to the central part, and a semiconductor element placed on the central part and the wiring are electrically connected, and the semiconductor element In a method of manufacturing a semiconductor device, comprising: a conductor formed on a lower side; and an insulating film that covers the substrate and the wiring so as to expose the conductor and is spaced apart from the semiconductor element by a predetermined distance.
Warping the periphery of the substrate to the side opposite to the side on which the semiconductor element is mounted, and widening a space between the substrate and the end of the semiconductor element; and injecting a sealing material from the widened space And a step of sealing a space formed at a predetermined distance between the substrate and the semiconductor element.   Placing the substrate on the support base such that a portion of the back surface of the substrate facing the central portion is on the top of the convex support base; and applying stress to the periphery of the substrate 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of widening the space by curving the periphery to the side opposite to the side on which the semiconductor element is mounted.   The method of manufacturing a semiconductor device according to claim 2, wherein the space is widened by fixing the periphery with a pressing jig and bringing the support and the substrate into close contact with each other.   Placing the substrate on the support table such that a portion of the back surface of the substrate facing the periphery is in contact with the upper surface of the support table having flexibility; and applying stress to the periphery of the substrate 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of widening the space by curving the periphery to the side opposite to the side on which the semiconductor element is mounted.

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