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JP4167194B2 - Manufacturing method of chip parts - Google Patents

Manufacturing method of chip parts Download PDF

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JP4167194B2
JP4167194B2 JP2004067657A JP2004067657A JP4167194B2 JP 4167194 B2 JP4167194 B2 JP 4167194B2 JP 2004067657 A JP2004067657 A JP 2004067657A JP 2004067657 A JP2004067657 A JP 2004067657A JP 4167194 B2 JP4167194 B2 JP 4167194B2
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electrode
forming step
substrate
forming
slit
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JP2005259892A (en
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順 木下
比呂六 坂井
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Koa Corp
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Description

本発明はチップ抵抗器の製造方法に係り、特に、外形寸法が小型化された場合に用いて好適なチップ抵抗器の製造方法に関するものである。   The present invention relates to a method of manufacturing a chip resistor, and more particularly to a method of manufacturing a chip resistor suitable for use when the external dimensions are reduced.

図6は従来より一般的に知られているチップ抵抗器の断面図であり、同図に示すチップ抵抗器1はアルミナ等からなる絶縁性基板2を有し、この絶縁性基板2上に抵抗体3と該抵抗体3の両端部に重なり合う一対の表面電極4とが形成されている。抵抗体3はガラスコート層5で覆われ、さらにガラスコート層5はエポキシ系樹脂等からなるオーバーコート層6で覆われている。これらのガラスコート層5とオーバーコート層6は抵抗体3の保護膜として機能している。絶縁性基板2の裏面には表面電極4と対応する両端部に一対の裏面電極7が形成されており、また、絶縁性基板2の両側端面にはそれぞれ表面電極4と裏面電極7とを橋絡する端面電極8が形成されている。表面電極4と裏面電極7は銀(Ag)を主成分とするペーストをスクリーン印刷等によって形成したものであり、端面電極8は例えばニッケルクロム(Ni/Cr)をスパッタ等によって形成したものである。表面電極4と裏面電極7および端面電極8はチップ抵抗器1の下地電極層を構成しており、製造工程の最終段階で該下地電極層をめっき処理することにより、ニッケル(Ni)めっき層9と半田(SN/Pb)めっき層10という二層構造のめっき層によって該下地電極層は被覆される。なお、これらめっき層9,10は、電極くわれの防止や半田付けの信頼性向上を図るためのものであり、半田めっき層の代わりに錫(Sn)めっき層を用いることもある。   FIG. 6 is a cross-sectional view of a chip resistor generally known from the prior art. A chip resistor 1 shown in FIG. 6 has an insulating substrate 2 made of alumina or the like, and a resistor is provided on the insulating substrate 2. A body 3 and a pair of surface electrodes 4 overlapping each other on both ends of the resistor 3 are formed. The resistor 3 is covered with a glass coat layer 5, and the glass coat layer 5 is further covered with an overcoat layer 6 made of an epoxy resin or the like. The glass coat layer 5 and the overcoat layer 6 function as a protective film for the resistor 3. A pair of back surface electrodes 7 are formed at both ends corresponding to the front surface electrode 4 on the back surface of the insulating substrate 2, and the front surface electrode 4 and the back surface electrode 7 are respectively bridged on both end surfaces of the insulating substrate 2. An end face electrode 8 is formed. The front electrode 4 and the back electrode 7 are formed by screen printing or the like using a paste mainly composed of silver (Ag), and the end electrode 8 is formed by sputtering nickel chrome (Ni / Cr), for example. . The front electrode 4, the back electrode 7 and the end electrode 8 constitute a base electrode layer of the chip resistor 1, and a nickel (Ni) plating layer 9 is formed by plating the base electrode layer at the final stage of the manufacturing process. The base electrode layer is covered with a two-layered plating layer of a solder (SN / Pb) plating layer 10. The plating layers 9 and 10 are for preventing electrode cracking and improving the reliability of soldering, and a tin (Sn) plating layer may be used instead of the solder plating layer.

従来、このように構成されたチップ抵抗器1は、以下に説明する工程によって製造されるようになっている(例えば、特許文献1参照)。すなわち、まず各チップ領域を区切る位置に縦横に延びる分割溝が形成された大判基板を準備し、この大判基板に個々のチップ抵抗器1に対応する多数の表面電極4と裏面電極7を形成すると共に、隣接する表面電極4間にそれぞれ抵抗体3を形成した後、各抵抗体3上にガラスコート層5とオーバーコート層6を順次形成する。次いで、大判基板を一方の分割溝に沿って分割(一次分割)して多数の短冊状分割片を得た後、これら短冊状分割片を重ね合わせた状態で各々の長手方向に沿う両端面に端面電極8を形成する。しかる後、各短冊状分割片を他方の分割溝に沿ってチップサイズに分割(二次分割)し、最後にニッケル(Ni)と半田(SN/Pb)めっき層10を施すことにより、図6に示すようなチップ抵抗器1が多数個取りされる。
特開平6−120013号公報(第2−3頁、図1)
Conventionally, the chip resistor 1 configured as described above is manufactured by a process described below (see, for example, Patent Document 1). That is, first, a large-sized substrate in which dividing grooves extending vertically and horizontally are formed at positions that divide each chip region, and a large number of front surface electrodes 4 and back surface electrodes 7 corresponding to the individual chip resistors 1 are formed on the large-sized substrate. At the same time, after the resistor 3 is formed between the adjacent surface electrodes 4, the glass coat layer 5 and the overcoat layer 6 are sequentially formed on each resistor 3. Next, after dividing the large substrate along one dividing groove (primary division) to obtain a large number of strip-shaped divided pieces, the strip-shaped divided pieces are stacked on both end surfaces along the respective longitudinal directions. The end face electrode 8 is formed. Thereafter, each strip-shaped divided piece is divided into chip sizes (secondary division) along the other divided groove, and finally, nickel (Ni) and solder (SN / Pb) plating layer 10 is applied, whereby FIG. A large number of chip resistors 1 as shown in FIG.
JP-A-6-120013 (page 2-3, FIG. 1)

ところで近年、各種電子機器の小型化に伴ってチップ抵抗器も小型化されてきており、例えば平面的な外形寸法を0.6mm×0.3mmとした超小型のチップ抵抗器が実現されており、さらに小型化されたチップ抵抗器も要望されている。   By the way, in recent years, chip resistors have been miniaturized along with miniaturization of various electronic devices. For example, an ultra-small chip resistor having a planar outer dimension of 0.6 mm × 0.3 mm has been realized. There is also a need for miniaturized chip resistors.

しかしながら前述した従来の製造方法では、大判基板を一次分割して得られる短冊状分割片の端面に端面電極を形成しており、端面電極を形成する前工程として大判基板を短冊状に分割する一次分割が必要となるため、チップ抵抗器の小型化に伴って短冊状分割片の幅寸法が非常に小さくなると、大判基板を短冊状分割片に一次分割すること自体が困難となる。また、仮に大判基板から多数の短冊状分割片を得ることができたとしても、幅寸法が小さくなるほど短冊状分割片の機械的強度が低下するため、複数の短冊状分割片を重ね合わせた状態でそれらの両端面に端面電極を形成する際に、短冊状分割片が不用意に割れてしまうという問題が発生する。さらに、チップ抵抗器が小型化されていくと、互いに重ね合わされた複数の短冊状分割片の僅かな位置ズレが端面電極の不良要因となるため、端面電極を高精度に形成することが困難になるという問題も発生する。   However, in the above-described conventional manufacturing method, the end face electrode is formed on the end face of the strip-shaped divided piece obtained by first dividing the large-sized substrate, and the primary step of dividing the large-sized substrate into the strip shape as a pre-process for forming the end face electrode. Since division is required, if the width of the strip-shaped divided piece becomes very small as the chip resistor is miniaturized, it becomes difficult to primarily divide the large substrate into strip-shaped divided pieces. In addition, even if a large number of strip-shaped divided pieces can be obtained from a large-sized substrate, the mechanical strength of the strip-shaped divided pieces decreases as the width dimension becomes smaller. Thus, when the end face electrodes are formed on both end faces, there arises a problem that the strip-like divided pieces are carelessly cracked. Further, as chip resistors are miniaturized, slight positional misalignment of a plurality of strip-shaped divided pieces superimposed on each other becomes a cause of defective end face electrodes, making it difficult to form end face electrodes with high accuracy. The problem that becomes.

本発明は、このような従来技術の実情に鑑みてなされたもので、その目的は、外形寸法が小型化されても端面電極を簡単かつ高精度に形成することができるチップ抵抗器を提供することにある。   The present invention has been made in view of the actual situation of the prior art, and an object of the present invention is to provide a chip resistor that can easily and highly accurately form an end face electrode even if the external dimensions are reduced. There is.

上記の目的を達成するために、本発明によるチップ抵抗器の製造方法では、所定サイズの大判基板の表裏両面に多数の電極をマトリックス状に形成する電極形成工程と、前記大判基板の一面に両端が前記電極に接続された多数の抵抗体を形成する抵抗体形成工程と、前記大判基板の表裏両面に少なくとも前記電極を覆うように保護層を形成する保護層形成工程と、この保護層形成工程後の前記大判基板を前記保護層の粘着力によって可撓性シートからなる支持台上に固定する基板固定工程と、前記支持台上に固定された前記大判基板に互いに平行な多数の一次スリットを形成して隣接する前記抵抗体を繋ぐ前記電極を2分割する一次スリット形成工程と、前記支持台を湾曲させて前記一次スリットの内部で表裏両面の前記電極どうしを接続する端面電極をスパッタにより形成する端面電極形成工程と、この端面電極形成工程後の前記大判基板に前記一次スリットと直交する方向に延びる多数の二次スリットを形成する二次スリット形成工程と、この二次スリット形成工程後に前記大判基板を前記支持台から剥離して個々の部品を得る部品分離工程とを具備することとする。 In order to achieve the above object, in the method of manufacturing a chip resistor according to the present invention, an electrode forming step of forming a large number of electrodes in a matrix on both front and back surfaces of a large substrate of a predetermined size, and both ends on one surface of the large substrate Forming a plurality of resistors connected to the electrodes, a protective layer forming step of forming a protective layer so as to cover at least the electrodes on the front and back surfaces of the large substrate, and the protective layer forming step Substrate fixing step of fixing the subsequent large-size substrate on a support base made of a flexible sheet by the adhesive force of the protective layer, and a plurality of primary slits parallel to the large-size substrate fixed on the support base. Forming a primary slit that divides the electrode that connects the adjacent resistors, and connecting the electrodes on the front and back surfaces inside the primary slit by curving the support base; An end face electrode forming step for forming end face electrodes by sputtering, a secondary slit forming step for forming a number of secondary slits extending in a direction orthogonal to the primary slit on the large substrate after the end face electrode forming step, And a component separation step of separating the large substrate from the support base after the next slit forming step to obtain individual components.

このような各工程を備えたチップ抵抗器の製造方法によれば、大判基板を可撓性シートからなる支持台上に固定した状態で多数の一次スリットを形成した後、この支持台を湾曲させて一次スリットの間隔を拡げた状態で端面電極をスパッタにより形成するようにしたので、チップ抵抗器の小型化に伴って各一次スリット間の幅寸法が非常に小さくなったとしても、端面電極を簡単かつ高精度に形成することができる。また、大判基板の表裏両面の電極が保護層によって覆われているので、端面電極が大判基板の表裏両面の電極まで回り込むことはなく、この点からも端面電極を高精度に形成することができる。   According to the manufacturing method of the chip resistor including each step as described above, after forming a large number of primary slits in a state where a large-sized substrate is fixed on a support base made of a flexible sheet, the support base is curved. Since the end face electrodes are formed by sputtering in a state where the interval between the primary slits is widened, the end face electrodes are formed even if the width dimension between the primary slits becomes very small due to the downsizing of the chip resistor. It can be formed easily and with high accuracy. In addition, since the electrodes on both the front and back surfaces of the large substrate are covered with the protective layer, the end surface electrodes do not wrap around to the electrodes on both the front and back surfaces of the large substrate, and the end surface electrodes can be formed with high accuracy also from this point. .

上記の構成において、端面電極形成工程で支持台を円筒状治具の外周面に固定し、この治具を回転させながら端面電極をスパッタにより形成することが好ましく、また、二次スリット形成工程時に支持台を平坦状に戻してから二次スリットを形成することが好ましい。   In the above configuration, it is preferable that the support table is fixed to the outer peripheral surface of the cylindrical jig in the end face electrode forming step, and the end face electrode is formed by sputtering while rotating the jig. It is preferable to form the secondary slit after returning the support base to a flat shape.

また、上記の構成において、一次スリットと二次スリットを形成する加工手段としてレーザやウォータージェットを用いることも可能であるが、これら一次スリットと二次スリットをダイシングにより形成することが好ましい。   In the above configuration, a laser or a water jet can be used as a processing means for forming the primary slit and the secondary slit, but it is preferable to form the primary slit and the secondary slit by dicing.

本発明によるチップ抵抗器の製造方法は、所定サイズの大判基板に個々のチップ抵抗器に対応する電極と抵抗体を一括して形成した後、この大判基板を支持台上に固定した状態で多数の一次スリットを形成し、支持台の可撓性を利用して一次スリットの間隔を拡げた状態で端面電極をスパッタにより形成するようにしたので、チップ抵抗器の小型化に伴って各一次スリット間の幅寸法が非常に小さくなったとしても、端面電極を簡単かつ高精度に形成することができ、しかも、この端面電極の形成時に大判基板の表裏両面の電極が保護層によって覆われているので、端面電極が大判基板の表裏両面の電極まで回り込むことはなく、この点からも端面電極を高精度に形成することができる。   In the chip resistor manufacturing method according to the present invention, electrodes and resistors corresponding to individual chip resistors are collectively formed on a large substrate having a predetermined size, and then the large substrate is fixed on a support base. Since the end face electrodes are formed by sputtering in the state where the primary slits are formed and the interval between the primary slits is widened by utilizing the flexibility of the support base, each primary slit is formed along with the downsizing of the chip resistor. Even if the width dimension between them becomes very small, the end face electrodes can be formed easily and with high precision, and the electrodes on both the front and back sides of the large-sized substrate are covered with a protective layer when the end face electrodes are formed. Therefore, the end face electrode does not go around to the electrodes on the front and back sides of the large-sized substrate, and the end face electrode can be formed with high accuracy from this point.

発明の実施の形態について図面を参照して説明すると、図1は本発明の実施形態例に係るチップ抵抗器の断面図、図2は該チップ抵抗器の製造工程を示す断面図、図3は該チップ抵抗器の製造工程を示す平面図、図4は該チップ抵抗器の製造工程における端面電極形成工程を示す説明図、図5は図4の要部拡大図である。   1 is a cross-sectional view of a chip resistor according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a manufacturing process of the chip resistor, and FIG. 4 is a plan view showing the manufacturing process of the chip resistor, FIG. 4 is an explanatory view showing an end face electrode forming process in the manufacturing process of the chip resistor, and FIG. 5 is an enlarged view of a main part of FIG.

図1に示すチップ抵抗器11は、アルミナ(Al)を主成分とする絶縁性基板12の表面側に、酸化ルテニウム等からなる抵抗体13と、この抵抗体13の両端部に重なり合う一対の表面電極14と、抵抗体13を覆うガラスコート層15およびオーバーコート層16とが形成されている。オーバーコート層16はエポキシ系樹脂等からなり、これらガラスコート層15とオーバーコート層16は抵抗体13の保護膜17として機能する。また、絶縁性基板12の裏面側には表面電極14と対応する両端部に一対の裏面電極18が形成されており、さらに、絶縁性基板12の両側端面にはそれぞれ表面電極14と裏面電極18とを橋絡する端面電極19が形成されている。表面電極14と裏面電極18はAgまたはAg−Pdを主成分とするペーストをスクリーン印刷等を用いて形成したものであり、端面電極19はニッケルクロム(Ni/Cr)をスパッタすることによって形成したものである。表面電極14と裏面電極18および端面電極19はチップ抵抗器11の下地電極層を構成しており、後述する製造工程の最終段階で該下地電極層をめっき処理することにより、ニッケル(Ni)メッキ層20と半田(SN/Pb)めっき層21という二層構造のめっき層22によって該下地電極層は被覆される。なお、該めっき層22(20,21)は、電極くわれの防止や半田付けの信頼性向上を図るためのものであり、半田めっき層の代わりに錫(Sn)めっき層を用いることも可能である。 A chip resistor 11 shown in FIG. 1 overlaps a resistor 13 made of ruthenium oxide or the like on both sides of the resistor 13 on the surface side of an insulating substrate 12 mainly composed of alumina (Al 2 O 3 ). A pair of surface electrodes 14 and a glass coat layer 15 and an overcoat layer 16 that cover the resistor 13 are formed. The overcoat layer 16 is made of an epoxy resin or the like, and the glass coat layer 15 and the overcoat layer 16 function as a protective film 17 for the resistor 13. Further, a pair of back surface electrodes 18 are formed on both end portions corresponding to the front surface electrode 14 on the back surface side of the insulating substrate 12, and the front surface electrode 14 and the back surface electrode 18 are respectively formed on both side end surfaces of the insulating substrate 12. Are formed. The front electrode 14 and the back electrode 18 are formed by using a screen printing or the like with a paste mainly composed of Ag or Ag-Pd, and the end electrode 19 is formed by sputtering nickel chrome (Ni / Cr). Is. The front electrode 14, the back electrode 18 and the end electrode 19 constitute a base electrode layer of the chip resistor 11, and nickel (Ni) plating is performed by plating the base electrode layer in the final stage of the manufacturing process described later. The underlying electrode layer is covered with a two-layered plating layer 22 of a layer 20 and a solder (SN / Pb) plating layer 21. The plating layer 22 (20, 21) is for preventing electrode cracking and improving the reliability of soldering, and a tin (Sn) plating layer can be used instead of the solder plating layer. It is.

次に、このように構成されたチップ抵抗器11の製造工程を図2と図3に基づいて説明する。   Next, the manufacturing process of the chip resistor 11 configured as described above will be described with reference to FIGS.

まず、図2(a)と図3(a)に示すように、多数個取り用の大判基板12Aを準備する。この大判基板12Aはチップ抵抗器11の絶縁性基板12となるものであり、図2と図3では1個または複数個のチップ領域のみを示してあるが、実際には1つの大判基板12Aから多数のチップ抵抗器11が一括して得られるようになっている。   First, as shown in FIGS. 2 (a) and 3 (a), a large-sized substrate 12A for preparing multiple pieces is prepared. The large substrate 12A serves as the insulating substrate 12 of the chip resistor 11. In FIGS. 2 and 3, only one or a plurality of chip regions are shown. A large number of chip resistors 11 can be obtained collectively.

次いで、図2(b)と図3(b)に示すように、大判基板12Aの表裏両面にAgまたはAg−Pdペーストをスクリーン印刷し、これを850°C程度の温度で焼成することにより、個々のチップ抵抗器11に対応する多数の表面電極14と裏面電極18を形成する(電極形成工程)。これら表面電極14と裏面電極18はどちらを先に形成しても良いが、表面電極14は大判基板12Aの表面側にマトリックス状に配列され、裏面電極18も大判基板12Aの裏面側にマトリックス状に配列される。   Next, as shown in FIG. 2 (b) and FIG. 3 (b), Ag or Ag-Pd paste is screen-printed on both the front and back surfaces of the large substrate 12A, and this is baked at a temperature of about 850 ° C. A large number of front surface electrodes 14 and back surface electrodes 18 corresponding to the individual chip resistors 11 are formed (electrode formation step). Either the front electrode 14 or the rear electrode 18 may be formed first, but the front electrode 14 is arranged in a matrix on the front side of the large substrate 12A, and the rear electrode 18 is also formed in a matrix on the rear side of the large substrate 12A. Arranged.

次いで、図2(c)と図3(c)に示すように、大判基板12Aの表面側に酸化ルテニウム等の抵抗体ペーストをスクリーン印刷して焼成することにより、図3(b)のX方向に沿って隣接する一対の表面電極14間にそれぞれ抵抗体13を形成する(抵抗体形成工程)。なお、これら抵抗体13と表面電極14はどちらを先に形成しても良く、要は抵抗体13の両端に隣接する表面電極14が接続されれば良い。   Next, as shown in FIGS. 2 (c) and 3 (c), a resistor paste such as ruthenium oxide is screen-printed on the surface side of the large substrate 12A and baked, so that the X direction in FIG. 3 (b). Each of the resistors 13 is formed between a pair of surface electrodes 14 adjacent to each other (resistor forming step). It should be noted that either the resistor 13 or the surface electrode 14 may be formed first, and the surface electrode 14 adjacent to both ends of the resistor 13 may be connected.

次いで、図2(d)と図3(d)に示すように、各抵抗体13を覆うようにガラスペーストをスクリーン印刷して焼成することにより、図3(b)のY方向に沿って帯状に延びるガラスコート層15を形成する。しかる後、図2(e)と図3(e)に示すように、ガラスコート層15上にエポキシ等の樹脂ペーストをスクリーン印刷して加温硬化することにより、ガラスコート層15を覆って帯状に延びるオーバーコート層16を形成し、各抵抗体13を保護する二層構造の保護膜17を形成する(保護膜形成工程)。   Next, as shown in FIGS. 2 (d) and 3 (d), a glass paste is screen-printed and fired so as to cover each resistor 13, thereby forming a strip shape along the Y direction in FIG. 3 (b). A glass coat layer 15 is formed extending in the direction. Thereafter, as shown in FIGS. 2 (e) and 3 (e), a resin paste such as epoxy is screen-printed on the glass coat layer 15 and heated and cured to cover the glass coat layer 15 and form a belt-like shape. An overcoat layer 16 extending in the direction of 2 is formed, and a protective film 17 having a two-layer structure for protecting each resistor 13 is formed (protective film forming step).

このように大判基板12Aに多数のチップ抵抗器11に対応する表裏両面電極14,18と抵抗体13および保護膜17(ガラスコート層15とオーバーコート層16)を一括して形成した後、この大判基板12Aの表裏両面に上部保護層23と下部保護層24を形成し、図2(f)と図3(f)に示すように、この下部保護層24の粘着力によって大判基板12Aをポリイミド等の可撓性シートからなる支持台25上に固定する(基板固定工程)。これら上部保護層23と下部保護層24はいずれもワックスからなり、大判基板12Aの表裏両面に均一厚に形成される。   Thus, after forming the front and back double-sided electrodes 14 and 18 corresponding to many chip resistors 11, the resistor 13, and the protective film 17 (the glass coat layer 15 and the overcoat layer 16) collectively on the large substrate 12A, An upper protective layer 23 and a lower protective layer 24 are formed on the front and back surfaces of the large-sized substrate 12A, and the large-sized substrate 12A is made of polyimide by the adhesive force of the lower protective layer 24 as shown in FIGS. 2 (f) and 3 (f). It fixes on the support stand 25 which consists of flexible sheets, such as (a board | substrate fixing process). Both the upper protective layer 23 and the lower protective layer 24 are made of wax, and are formed to have a uniform thickness on both the front and back surfaces of the large substrate 12A.

次いで、図2(g)と図3(g)に示すように、ダイシングによって大判基板12Aに互いに平行な複数本の一次スリット26を形成し、これら一次スリット26によって表面電極14と裏面電極18の各対を図3(b)のY方向に沿って2分割する(一次スリット形成工程)。これら一次スリット26の両端は大判基板12Aの周縁部まで達しているが、隣接する一対の一次スリット26で挟まれた短冊状部分27が下部保護層24の粘着力によって支持台25上に固定されているため、一次スリット26を有する大判基板12Aは支持台25に保持されたままで分離することはない。   Next, as shown in FIGS. 2G and 3G, a plurality of primary slits 26 parallel to each other are formed on the large substrate 12A by dicing, and the front electrode 14 and the back electrode 18 are formed by these primary slits 26. Each pair is divided into two along the Y direction in FIG. 3B (primary slit forming step). Both ends of these primary slits 26 reach the peripheral edge of the large substrate 12A, but a strip-like portion 27 sandwiched between a pair of adjacent primary slits 26 is fixed on the support base 25 by the adhesive force of the lower protective layer 24. Therefore, the large-sized substrate 12 </ b> A having the primary slit 26 is not separated while being held by the support base 25.

次いで、図2(h)に示すように、一次スリット26の内側面にニッケルクロム(Ni/Cr)をスパッタすることにより、一次スリット26内に露出する表面電極14と裏面電極18の端面どうしを橋絡する端面電極19を形成する(端面電極形成工程)。この場合、図4に示すように、支持台25を円筒状治具28の外周面に巻回・固定して一次スリット26の間隔を外側に向けて拡げ、この状態で治具28を回転させながらニッケルクロム(ターゲット)を矢印A方向へスパッタすることにより、端面電極19を形成するようにしている。これにより、図5に示すように、矢印A方向に対して傾斜する大判基板12A(短冊状部分27)の端面P1にスパッタ膜が廻り込みやすくなるため、本来形成する必要のない表面P2にスパッタ膜が厚く形成され過ぎることがなくなり、膜厚の不均一に起因する大判基板12Aの反りを防止することができる。なお、図4と図5には省略されているが、かかる端面電極19の形成時に、表面電極14と裏面電極18はそれぞれ上部保護層23と下部保護層24によって覆われているため、端面電極19が大判基板12Aの表裏両面の表面電極14と裏面電極18まで回り込むことはない。   Next, as shown in FIG. 2 (h), nickel chromium (Ni / Cr) is sputtered on the inner surface of the primary slit 26, so that the end surfaces of the surface electrode 14 and the back electrode 18 exposed in the primary slit 26 are separated from each other. A bridging end face electrode 19 is formed (end face electrode forming step). In this case, as shown in FIG. 4, the support base 25 is wound and fixed on the outer peripheral surface of the cylindrical jig 28 to widen the interval between the primary slits 26 outward, and the jig 28 is rotated in this state. However, the end face electrode 19 is formed by sputtering nickel chrome (target) in the direction of arrow A. As a result, as shown in FIG. 5, the sputtered film easily goes around the end face P1 of the large-sized substrate 12A (strip-shaped portion 27) inclined with respect to the direction of the arrow A. The film is not formed too thick, and the warping of the large substrate 12A due to the non-uniform film thickness can be prevented. Although omitted in FIGS. 4 and 5, when the end face electrode 19 is formed, the front face electrode 14 and the back face electrode 18 are covered with the upper protective layer 23 and the lower protective layer 24, respectively. 19 does not reach the front surface electrode 14 and the back surface electrode 18 on both the front and back surfaces of the large substrate 12A.

次いで、支持台25を円筒状治具28から取り外して平坦状に戻した後、図3(h)に示すように、ダイシングによって大判基板12Aに各一次スリット26と直交する方向に延びる互いに平行な複数本の二次スリット29を形成し、大判基板12Aを一次スリット26と二次スリット29で囲まれた多数のチップ単体30に細分割する(二次スリット形成工程)。   Next, after removing the support base 25 from the cylindrical jig 28 and returning it to a flat shape, as shown in FIG. 3 (h), the large substrate 12A is parallel to each other extending in a direction orthogonal to the primary slits 26 by dicing. A plurality of secondary slits 29 are formed, and the large substrate 12A is subdivided into a large number of single chips 30 surrounded by the primary slits 26 and the secondary slits 29 (secondary slit forming step).

しかる後、上部保護層23と下部保護層24を洗浄することにより、大判基板12Aに設けられた各チップ単体30を支持台25から剥離し(部品分離工程)、最後に、各チップ単体30の下地電極層に電解めっきを施してニッケル(Ni)メッキ層20と半田(SN/Pb)めっき層21を形成することにより、図1に示すようなチップ抵抗器11が多数個取りされる。   Thereafter, by cleaning the upper protective layer 23 and the lower protective layer 24, each chip unit 30 provided on the large substrate 12A is peeled off from the support base 25 (part separation step). By applying electrolytic plating to the base electrode layer to form a nickel (Ni) plating layer 20 and a solder (SN / Pb) plating layer 21, a large number of chip resistors 11 as shown in FIG. 1 are obtained.

このようにして製造されるチップ抵抗器11は、所定サイズの大判基板12Aに多数個取りされるチップ抵抗器11に対応する表裏両面電極14,18と抵抗体13および保護膜17(ガラスコート層15とオーバーコート層16)を一括して形成した後、この大判基板12Aを可撓性シートからなる支持台25上に固定した状態で多数の一次スリット26を形成し、次いで、この支持台25を円筒状治具28に巻回・固定して一次スリット26の間隔を拡げた状態で端面電極19をスパッタにより形成するようにしたので、チップ抵抗器11の小型化に伴って各一次スリット26間の幅寸法が非常に小さくなったとしても、端面電極19を簡単かつ高精度に形成することができる。しかも、端面電極19の形成時に表面電極14と裏面電極18はそれぞれ上部保護層23と下部保護層24によって覆われているため、端面電極19が大判基板12Aの表裏両面の表面電極14と裏面電極18まで回り込むことはなく、表面電極14と裏面電極18のスクリーン印刷での寸法精度が維持されたまま端面電極19を高精度に形成することができる。   The chip resistor 11 manufactured in this way has the front and back double-sided electrodes 14 and 18 corresponding to the chip resistor 11 taken in large numbers on a large substrate 12A of a predetermined size, the resistor 13, and the protective film 17 (glass coating layer). 15 and the overcoat layer 16) are collectively formed, and then a large number of primary slits 26 are formed in a state in which the large-sized substrate 12A is fixed on the support base 25 made of a flexible sheet. Since the end face electrode 19 is formed by sputtering in a state where the space between the primary slits 26 is widened by winding and fixing them on the cylindrical jig 28, each primary slit 26 is reduced along with the downsizing of the chip resistor 11. Even if the width dimension between them becomes very small, the end face electrode 19 can be formed easily and with high accuracy. Moreover, since the surface electrode 14 and the back surface electrode 18 are covered with the upper protective layer 23 and the lower protective layer 24, respectively, when the end surface electrode 19 is formed, the end surface electrode 19 is formed on the front and back surfaces of the large substrate 12A. The end surface electrode 19 can be formed with high accuracy while maintaining the dimensional accuracy of the front surface electrode 14 and the back surface electrode 18 in screen printing.

また、このチップ抵抗器11は抵抗体13と表面電極14および裏面電極18を厚膜形成したものであるが、上部保護層23と下部保護層24としてワックスを用いているため、ダイシングによって大判基板12Aに一次スリット26を形成する際に懸念される表面電極14と裏面電極18の欠けを防止できる。   The chip resistor 11 is formed by forming a thick film of the resistor 13, the front electrode 14, and the back electrode 18. Since the upper protective layer 23 and the lower protective layer 24 are made of wax, a large substrate is formed by dicing. It is possible to prevent the front electrode 14 and the back electrode 18 from being chipped when the primary slit 26 is formed in 12A.

なお、上記実施形態例では、抵抗体13と表面電極14および裏面電極18を厚膜形成した厚膜タイプのチップ抵抗器11について説明したが、これら抵抗体と表面電極および裏面電極をスパッタ等で薄膜形成した薄膜タイプのチップ抵抗器にも適用可能である。この場合、一次スリット26の形成時にダイシングによって表面電極14と裏面電極18が欠ける虞がなくなるため、上部保護層23ととしてワックスの代わりにレジストを用いても良い。 In the above embodiment, the thick film type chip resistor 11 in which the resistor 13, the surface electrode 14, and the back electrode 18 are formed thick has been described. However, the resistor, the surface electrode, and the back electrode are formed by sputtering or the like. It can also be applied to a thin film type chip resistor formed into a thin film. In this case, since there is no possibility that the front electrode 14 and the rear electrode 18 are lost due to dicing when the primary slit 26 is formed, a resist may be used instead of wax as the upper protective layer 23 .

また、上記実施形態例では、一次スリット26と二次スリット29を形成する加工手段としてダイシングを例示したが、ダイシングの代わりにレーザやウォータージェットを用いることも可能である。   In the above embodiment, dicing is exemplified as the processing means for forming the primary slit 26 and the secondary slit 29. However, a laser or a water jet can be used instead of dicing.

本発明の実施形態例に係るチップ抵抗器の断面図 である。It is sectional drawing of the chip resistor which concerns on the example of embodiment of this invention. 該チップ抵抗器の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of this chip resistor. 該チップ抵抗器の製造工程を示す平面図である。It is a top view which shows the manufacturing process of this chip resistor. 該チップ抵抗器の製造工程における端面電極形成工程を示す説明図である。It is explanatory drawing which shows the end surface electrode formation process in the manufacturing process of this chip resistor. 図4の要部拡大図である。It is a principal part enlarged view of FIG. 従来例に係るチップ抵抗器の断面図である。It is sectional drawing of the chip resistor which concerns on a prior art example.

符号の説明Explanation of symbols

11 チップ抵抗器
12 絶縁性基板
12A 大判基板
13 抵抗体
14 表面電極
15 ガラスコート層
16 オーバーコート
17 保護膜
18 裏面電極
19 端面電極
22 めっき層
23 上部保護層
24 下部保護層
25 支持台
26 一次スリット
27 短冊状部分
28 円筒状治具28
29 二次スリット
30 チップ単体
DESCRIPTION OF SYMBOLS 11 Chip resistor 12 Insulating board | substrate 12A Large format board 13 Resistor 14 Front surface electrode 15 Glass coat layer 16 Overcoat 17 Protective film 18 Back surface electrode 19 End surface electrode 22 Plating layer 23 Upper protective layer 24 Lower protective layer 25 Support stand 26 Primary slit 27 Strip-shaped portion 28 Cylindrical jig 28
29 Secondary slit 30 Single chip

Claims (4)

所定サイズの大判基板の表裏両面に多数の電極をマトリックス状に形成する電極形成工程と、
前記大判基板の一面に両端が前記電極に接続された多数の抵抗体を形成する抵抗体形成工程と、
前記大判基板の表裏両面に少なくとも前記電極を覆うように保護層を形成する保護層形成工程と、
この保護層形成工程後の前記大判基板を前記保護層の粘着力によって可撓性シートからなる支持台上に固定する基板固定工程と、
前記支持台上に固定された前記大判基板に互いに平行な多数の一次スリットを形成して隣接する前記抵抗体を繋ぐ前記電極を2分割する一次スリット形成工程と、
前記支持台を湾曲させて前記一次スリットの内部で表裏両面の前記電極どうしを接続する端面電極をスパッタにより形成する端面電極形成工程と、
この端面電極形成工程後の前記大判基板に前記一次スリットと直交する方向に延びる多数の二次スリットを形成する二次スリット形成工程と、
この二次スリット形成工程後に前記大判基板を前記支持台から剥離して個々の部品を得る部品分離工程と、
を具備してなるチップ抵抗器の製造方法。
An electrode forming step of forming a large number of electrodes in a matrix on both front and back surfaces of a large substrate of a predetermined size;
A resistor forming step of forming a large number of resistors whose both ends are connected to the electrodes on one surface of the large substrate,
A protective layer forming step of forming a protective layer so as to cover at least the electrodes on both the front and back surfaces of the large substrate;
A substrate fixing step of fixing the large-sized substrate after the protective layer forming step on a support base made of a flexible sheet by the adhesive force of the protective layer ;
A primary slit forming step of dividing the electrode that connects the adjacent resistors by forming a large number of primary slits parallel to each other on the large substrate fixed on the support;
An end face electrode forming step of forming an end face electrode by sputtering the end face electrode that connects the electrodes on both the front and back sides inside the primary slit by curving the support base;
A secondary slit forming step of forming a number of secondary slits extending in a direction orthogonal to the primary slit in the large substrate after the end face electrode forming step;
A component separation step of separating the large substrate from the support base after the secondary slit forming step to obtain individual components;
A method of manufacturing a chip resistor comprising:
請求項1の記載において、前記端面電極形成工程で前記支持台を円筒状治具の外周面に固定し、この治具を回転させながら前記端面電極をスパッタにより形成することを特徴とするチップ抵抗器の製造方法。 2. The chip resistor according to claim 1, wherein the support table is fixed to an outer peripheral surface of a cylindrical jig in the end face electrode forming step, and the end face electrode is formed by sputtering while rotating the jig. method of manufacturing a vessel. 請求項1または2の記載において、前記二次スリット形成工程で前記支持台を平坦状に戻してから前記二次スリットを形成することを特徴とするチップ抵抗器の製造方法。 3. The method of manufacturing a chip resistor according to claim 1, wherein the secondary slit is formed after the support base is returned to a flat shape in the secondary slit forming step. 請求項1〜3のいずれか1項の記載において、前記一次スリットと前記二次スリットがダイシングにより形成されることを特徴とするチップ抵抗器の製造方法。 4. The method of manufacturing a chip resistor according to claim 1, wherein the primary slit and the secondary slit are formed by dicing.
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