JP4154074B2 - surge absorber - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a surge absorber, and more particularly, to a surge absorber using a semiconductor crystal having a high band gap energy and a low operating resistance and a high surge resistance.
[0002]
[Prior art]
Conventionally, as a surge absorber for protecting electrical equipment from overvoltage, a constant voltage diode using a breakdown phenomenon of a pn junction formed of a Si semiconductor has been used. The constant voltage diode is, for example, a pn junction 2 formed of a Si semiconductor as described in detail on page 774 of the electronic information communication society edition, “electronic information communication handbook”, volume 9, semiconductor device, page 2, 774. The type of breakdown phenomenon, that is, a phenomenon in which the avalanche breakdown voltage and the Zener breakdown voltage exhibit a constant value over a wide range of reverse currents is used.
[0003]
6A and 6B are diagrams showing an epitaxial constant voltage diode using avalanche breakdown. FIG. 6A is a cross-sectional view of the epitaxial constant voltage diode, and FIG. 6B shows its voltage-current characteristics.
[0004]
In FIG. 1A, 101 is an epitaxial constant voltage diode, 102 is an n-type Si semiconductor substrate, 103 is an n + type layer formed on the substrate 102, 104 is a p + type epitaxial layer, 105 is an anode electrode, and 106 is a cathode electrode. 107 is a p-type diffusion layer formed by diffusing p + -type impurities into the Si semiconductor substrate 102 by heat treatment after growing the p + -type epitaxial layer 104, 108 is a guard ring formed by a p-type layer, and 109 is SiO 2. It is a membrane.
[0005]
The breakdown voltage of the epitaxial constant voltage diode 101 depends on the concentration gradient near the pn junction of the p-type diffusion layer 107 formed by diffusing the p-type impurity in the Si substrate 102 and the amount of impurities in the n-type Si semiconductor substrate 102. Subtle control is possible. The p-type diffusion layer can also be formed by ion implantation of p-type impurities and subsequent thermal diffusion.
[0006]
FIG. 2B shows the voltage-current characteristics of the epitaxial constant voltage diode 101. When a reverse voltage is applied to the diode 101, an avalanche breakdown occurs in the breakdown region of the predetermined voltage, and the reverse current increases significantly. The performance of the constant voltage diode can be judged by the ratio of the breakdown region voltage (Vz) to the current (Iz), that is, the operating resistance (Zz = Vz / Iz). Good. The voltage-current characteristic can be approximated by the following equation.
[0007]
Iz = (Vz / C) ^α
Here, C is a constant, α is a voltage ratio linear index, α = 1 is a normal resistance, and the larger α is, the better.
[0008]
A constant voltage diode using a Si semiconductor can obtain an element with α = 100 to 500, and can withstand repeated operations, and is therefore widely used as a protective element for electrical equipment.
[0009]
However, a constant voltage diode using Si as a semiconductor material has a significantly lower surge resistance than a sintered body varistor. For example, the constant voltage diode has an operating voltage of several volts to several hundred volts and a peak pulse current of several hundred volts even if the peak pulse current is large. The application is limited to electronic devices with a relatively small capacity. That is, in a constant voltage diode using Si as a semiconductor material, the upper limit operating temperature of the pn junction is normally 150 to 200 ° C., and the heat capacity of Si is relatively small. Therefore, the absorbed energy allowed for the constant voltage diode is significantly limited as compared with a ceramic surge absorber such as a sintered body varistor. As described above, there is no surge absorber that has low operating resistance, good operating voltage flatness, high surge withstand capability, and can be used in a wide voltage and current range. Appearance is desired.
[0010]
A surge absorber using a wide band gap semiconductor can be considered to meet such a demand. For example, the band gap energy Eg of SiC is 3.2 eV, which is about three times the band gap energy 1.12 eV of Si. Furthermore, the upper limit operating temperature of the semiconductor junction is 1000 ° C., the melting temperature of the crystal is 2300 ° C., and the thermal conductivity is about three times that of Si. Therefore, when such a semiconductor material is used, there is a possibility of realizing a surge absorber capable of meeting the above-mentioned demands, such as a higher surge resistance than a surge absorber using a Si semiconductor.
[0011]
[Problems to be solved by the invention]
However, there are several problems in fabricating a surge absorber using a wide band gap semiconductor. That is,
The surge absorber needs to precisely control the breakdown voltage of the pn junction, which is the operation start voltage of the element, to a predetermined value. However, since a dopant impurity hardly diffuses in a wide band gap semiconductor, it is almost impossible to freely control a breakdown voltage by impurity diffusion applied to the Si semiconductor.
[0012]
Further, since the control accuracy of the impurity concentration of the wide band gap semiconductor substrate is low, precise control of the avalanche breakdown voltage is difficult.
[0013]
Furthermore, it is necessary to operate a pn junction with a large area uniformly in order to produce a device with a large surge resistance, but it is difficult to ensure uniform operation over the entire area, and obtaining the required surge resistance Have difficulty.
[0014]
The present invention has been made in view of the above problems, and provides a surge absorber that has a low operating resistance, good operating voltage flatness, a high surge resistance, and can be used in a wide voltage-current region.
[0015]
[Means for Solving the Problems]
The present invention employs the following means in order to solve the above problems.
[0016]
A first conductivity type semiconductor substrate ; a second conductivity type semiconductor layer formed on one main surface of the semiconductor substrate; and the second conductivity type semiconductor layer disposed at predetermined intervals on the second conductivity type semiconductor layer. A second conductivity type impurity layer having a concentration higher than the impurity concentration of the semiconductor layer; a first electrode conductively connected to the second conductivity type semiconductor layer and the second conductivity type impurity layer; and the other of the substrate A second electrode formed on the main surface of the first conductive type semiconductor substrate , wherein the first conductive type semiconductor substrate is made of a semiconductor material having a band gap of 2.0 eV or more, and the impurity concentration of the second conductive type semiconductor layer is When a pn junction composed of a first conductivity type semiconductor substrate and the second conductivity type semiconductor layer is reverse-biased, a depletion layer formed in the pn junction reaches the surface of the second conductivity type semiconductor layer. The punch-through voltage is an avalanche of the pn junction. It was set to a concentration lower than the voltage.
[0018]
In the surge absorber,
The impurity layer of the second conductivity type is formed shallower than the semiconductor layer of the second conductivity type.
[0019]
In the surge absorber,
The vicinity of the other main surface of the semiconductor substrate is a relatively high concentration impurity layer of the first conductivity type.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a view showing a surge absorber according to a first embodiment of the present invention. In the figure, 1 is a SiC single crystal semiconductor substrate having a main surface above and below, 2 is a relatively thick n-type layer having an impurity concentration of 5 to 8 × 10 15 / cm ³ , and a thickness of about 200 μm, and 3 is an impurity. This is a p-type layer having a total amount of about 7 × 10 12 / cm ² and an average impurity concentration of about 8 × 10 16 / cm ³ . The semiconductor substrate 1 includes the n-type layer 2 and the p-type layer 3, and a pn junction 32 is formed between these semiconductor layers. 4 is an electrode made of, for example, Ni metal in ohmic contact with one main surface where the n-type layer 2 is exposed, 5 is an electrode made of, for example, Al metal, which is made in ohmic contact with the other main surface where the p-type layer 3 is exposed, The p + type layer 6 is a relatively high concentration p + type layer having an average impurity concentration of 2 * 10 <17> / cm < ³ > and a depth of about 0.7 [mu] m. Provide from the surface. The p + type layer 6 is in ohmic contact with the electrode 5 at a low resistance.
[0021]
When a reverse voltage is applied to the pn junction 32 so that the electrode 4 is at a positive potential with respect to the electrode 5, the depletion layer extends into the n-type layer 2 and the p-type layer 3 from the pn junction 32 to prevent the reverse voltage. To do. The spread of the depletion layer to the n-type layer 2 and the p-type layer 3 increases as the applied reverse voltage increases. If the depletion layer width and average impurity concentration in the n-type layer 2 and the p-type layer 3 are Xn, Nn, Xp, and Np, respectively, the relationship Xn · Nn = Xp · Np is maintained.
[0022]
In this embodiment, since Np >> Nn, Xp << Xn. In this embodiment, since the thickness of the p-type layer 3 is extremely small, Xp is the p-type layer before the electric field at the pn junction reaches the breakdown electric field (in the case of SiC, approximately 2 × 10 6 V / cm). It spreads throughout and reaches the main surface on the electrode 5 side. The punch-through phenomenon occurs at this voltage, and the pn junction breaks down. That is, the punch-through breakdown occurs before the pn junction causes the avalanche breakdown.
[0023]
In this embodiment, the avalanche voltage is about 1400V, while the punch-through voltage is 1000V. The punch-through voltage depends on the total amount of impurities in the p-type layer 3. Therefore, the punch-through voltage can be accurately controlled to a required value by precisely adjusting the dopant implantation amount by ion implantation or the like.
[0024]
FIG. 2 is a diagram showing voltage-current characteristics of the surge absorber according to the present embodiment. As shown in the figure, when the reverse voltage is sequentially increased, the p-type layer causes punch-through at the voltage Vz, and the reverse current starts to flow rapidly. On the other hand, an avalanche breakdown occurs at an avalanche voltage VB in a normal pn junction with a large amount of impurities in the p-type layer 3.
[0025]
The surge absorber according to the present embodiment starts punch-through breakdown at a predetermined voltage Vz where Vz <VB. In the energization time of 100 μs, the device operated normally even when a reverse current of about 1000 A was repeatedly applied. Further, the potential difference between the electrodes when the reverse current is 1000 A is about 40 V, the voltage non-linear index α is about 350, and it has high-performance surge absorption characteristics.
[0026]
Note that the p + -type layer 6 is a guard ring that prevents a breakdown voltage from being lowered due to a locally concentrated electric field applied to the end of the pn junction 32. In the figure, a guard ring structure that is commonly used is shown, but other structures such as a field limiting ring (FLR), a field plate (FP), or a junction termination extension (JTE) can be applied.
[0027]
The electrodes 4 and 5 are in ohmic contact with the n-type layer 2 and the p-type layer 3, respectively, but may be a Schottky contact with a low barrier that breaks down at a voltage sufficiently lower than the punch-through voltage. This is because the operating voltage and the operating resistance are not greatly affected.
[0028]
Next, a second embodiment of the present invention will be described with reference to FIGS. 3A is a sectional view, and FIG. 3B is a plan view. In FIG. 3, reference numeral 7 denotes a p + type layer provided in the p type layer 3 from the main surface on the electrode 5 side of the substrate 2. A plurality of p + type layers 7 are provided at a relatively high concentration and shallower than the p type layer 3. The p + type layer 7 has an average impurity concentration and a depth of 1 × 10 17 power / cm ³ and 0.3 μm, respectively, and is dispersedly arranged with a width and an interval of 50 μm. In the figure, the same parts as those shown in FIG.
[0029]
When a reverse voltage is applied to the pn junction 32 so that the electrode 4 is at a positive potential with respect to the electrode 5, the depletion layer extends into the n-type layer 2 and the p-type layer 3 from the pn junction 32 to prevent the reverse voltage. To do. The spread of the depletion layer to the n-type layer 2 and the p-type layer 3 increases as the applied reverse voltage increases. The depletion layer extending in the p-type layer 3 expands in the region without the p + -type layer 7 in the same manner as in the first embodiment described above, and is punched with the voltage Vz at which the tip reaches the main surface on the electrode 5 side. Surrender through. However, in the region where the p + -type layer 7 is formed, the tip of the depletion layer reaches the p + -type layer 7 and then expands into the p + -type layer 7, so that punch-through does not occur at the voltage Vz. That is, the punch through region is divided, and the punch through operation is performed uniformly over a wide area of the pn junction. Thus, by providing the p + type region 7, it becomes possible to manufacture a large-diameter element having a pn junction area of 10 cm ² or more, and an element having a surge resistance of 5000 A or more can be obtained.
[0030]
In the above, an example in which the depth of the p + type layer 7 is shallower than that of the p type layer 3 is shown. However, even if the depth of the p + type layer 7 is equal to or deeper than that of the p type layer 3, the same effect as described above. Can be obtained. Further, the p + type layer 7 has a striped planar structure as shown in FIG. 3B, and each stripe p + type layer 7 is terminated by a p + type layer 6 forming a guard ring. .
[0031]
FIG. 4 is a diagram showing another planar structure of the p + type layer 7. FIG. 4A shows an example in which the p + type layer 7 is formed in a mesh shape, and FIG. 4B shows an example in which the p + type layer 7 is arranged in a polka dot pattern. The same effect as the formed example can be obtained. In the figure, the same parts as those shown in FIGS. 1 to 3 are denoted by the same reference numerals, and the description thereof is omitted.
[0032]
Next, a third embodiment of the present invention will be described with reference to FIG. In the figure, 1a is a SiC single crystal substrate, 2a is an n + type SiC single crystal semiconductor layer having a relatively high impurity concentration, and 2b is doped with impurities at a relatively low concentration on the semiconductor layer 2a by an epitaxial growth method or the like. A thin n-type layer formed. In the figure, the same parts as those shown in FIG.
[0033]
If the n-type layer 2b is formed by the epitaxial growth method in this way, the impurity concentration at the pn junction formation position of the substrate 1a can be controlled with high accuracy and lattice defects can be reduced. A surge absorber with excellent stability can be obtained.
[0034]
Further, when the substrate 1a having the semiconductor layer 2a having a relatively high concentration is used, the operating resistance is reduced and a higher performance surge absorber can be obtained.
[0035]
In the above description, an n-type semiconductor substrate has been described as an example, but it is needless to say that the present invention can be similarly applied to a p-type semiconductor substrate.
[0036]
【The invention's effect】
As described above, according to the present invention, in the surge absorber using the wide band gap semiconductor material, the dopant impurity of the semiconductor layer having a high concentration among the p-type semiconductor layer and the n-type semiconductor layer constituting the pn junction. Since the reverse voltage at which the punch-through phenomenon occurs is controlled and the breakdown voltage of the pn junction is controlled, a surge absorber having a large surge resistance and an accurate operation start voltage can be obtained.
[Brief description of the drawings]
FIG. 1 is a diagram showing a surge absorber according to a first embodiment of the present invention.
FIG. 2 is a graph showing voltage-current characteristics of a surge absorber.
FIG. 3 is a view showing a surge absorber according to a second embodiment of the present invention.
FIG. 4 is a diagram showing another planar structure of a p + type layer.
FIG. 5 is a view showing a surge absorber according to a third embodiment of the present invention.
FIG. 6 is a diagram illustrating a conventional constant voltage diode.
[Explanation of symbols]
1, 1a Semiconductor substrate 2, 2b n-type layer 2a n + type semiconductor layer 3 p-type layer 4, 5 electrode 6 p + -type layer 32 pn junction 7 p + -type layer

Claims (3)

A first conductivity type semiconductor substrate;
A second conductivity type semiconductor layer formed on one main surface of the semiconductor substrate;
A second conductivity type impurity layer having a higher concentration than the impurity concentration of the second conductivity type semiconductor layer, disposed at a predetermined interval in the second conductivity type semiconductor layer;
A first electrode conductively connected to the second conductivity type semiconductor layer and the second conductivity type impurity layer ;
A second electrode formed on the other main surface of the substrate ;
The semiconductor substrate of the first conductivity type is made of a semiconductor material having a band gap of 2.0 eV or more, and the impurity concentration of the semiconductor layer of the second conductivity type is that of the semiconductor substrate of the first conductivity type and that of the second conductivity type. When a pn junction made of a semiconductor layer is reverse-biased, a punch-through voltage generated when a depletion layer formed in the pn junction reaches the surface of the semiconductor layer of the second conductivity type is higher than an avalanche voltage of the pn junction. A surge absorber characterized by a low concentration. In the surge absorber of claim 1, wherein the second conductivity type impurity layer of the surge absorber, characterized in that formed shallower than the semiconductor layer of the second conductivity type. 3. The surge absorber according to claim 1 , wherein the vicinity of the other main surface of the semiconductor substrate is a relatively high concentration impurity layer of the first conductivity type.

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