JP4147441B2 - Compound semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a compound semiconductor device, and more particularly to a compound semiconductor device characterized by a combination of metal materials for forming a non-alloy electrode having low contact resistance and excellent thermal stability using a lift-off method. is there.
[0002]
[Prior art]
In recent years, high-frequency compound semiconductor devices such as GaAs field effect transistors or HEMTs (High Electron Mobility Transistors), polarization devices, etc. are used as semiconductor devices for constructing communication systems in order to meet demands for high-speed or large-capacity communication. A compound optical semiconductor device such as an independent semiconductor laser or a PIN photodiode is used.
[0003]
As an electrode formed in such a compound semiconductor device, an alloy electrode such as an AuGe / Ni / Au electrode or a Ti / Al electrode, or a non-alloy electrode such as a Ti / Pt / Au electrode is used.
[0004]
Among these, alloy electrodes such as AuGe / Ni / Au electrodes and Ti / Al electrodes are mainly used as ohmic electrodes, and after forming a metal layer to be an electrode on the semiconductor layer, heat treatment is applied to the semiconductor and An electrode is formed by reacting with a metal and alloying (alloying) it.
[0005]
Therefore, the reaction between the metal constituting the electrode such as Au and Ti and the underlying semiconductor layer such as InGaAs proceeds excessively due to heat applied in the wiring formation process after the electrode formation, etc., and the metal-semiconductor intermediate compound having high resistance There is a problem in thermal stability such that the contact resistance value increases or hillocks appear on the surface of the electrode due to thermal stress and the surface shape becomes rough.
[0006]
On the other hand, non-alloy electrodes such as Ti / Pt / Au electrodes are used as ohmic electrodes and Schottky electrodes. However, since the Ti layer constituting the contact portion with the underlying semiconductor layer is a refractory metal, The film deposition process is a high-speed film deposition process. Therefore, it is difficult to control the film thickness when forming a thin film, and it is necessary to set the film thickness to 5 nm or more in order to ensure uniformity as an electrode.
[0007]
However, when a Ti layer having a thickness of 5 nm or more is formed on a semiconductor layer having high reactivity with a metal such as InGaAs or InAlAs, an intermediate compound between Ti and the semiconductor by heat applied in a wiring forming process after electrode formation There is a problem in thermal stability, such as a reaction in which the contact resistance is increased, the contact resistance value is increased, or the height of the Schottky barrier is changed.
[0008]
In order to solve such a problem of thermal stability, it has been proposed to use a non-alloy electrode using W having a low reactivity with a semiconductor or a W compound such as WSi or WSiN. A conventional process for forming a non-alloy electrode using a W-based material will be described with reference to FIG. 4 (refer to Japanese Patent Laid-Open No. 2-234442 if necessary).
FIG. 4 is an explanatory view of a manufacturing process of a conventional GaAs field effect transistor, and a non-alloy electrode using a W-based material is used as a Schottky barrier gate electrode of the GaAs field effect transistor.
[0009]
4A. First, an undoped GaAs layer 32 having a thickness of 0.5 μm and a thickness of 2 × 10 ¹⁸ cm are formed on a semi-insulating GaAs substrate 31 by using MBE (Molecular Beam Epitaxy) method. The n-type GaAs layer 32 having an impurity concentration of ⁻³ is grown sequentially. Next, after depositing the WSi layer 34 using the sputtering method, the LaB ₆ layer 35 having a high melting point for relieving stress is deposited using the vapor deposition method, and then again the W layer 36 using the sputtering method. Then, a resist is applied on the entire surface, and exposed and developed to form a resist pattern 37 having a shape corresponding to the gate electrode.
[0010]
Next, referring to FIG. 4B, using the resist pattern 37 as a mask, the W layer 36 is selectively etched by performing dry etching using CF ₄ , and then the LaB ₆ layer is formed by ion milling using Ar ions. 35 is selectively removed, and dry etching is performed again with an etching gas 38 using CF ₄ to selectively etch the WSi layer 34 to form a non-alloy Schottky barrier gate electrode.
[0011]
4C. Next, after removing the resist pattern 37, an ohmic electrode made of Ni / Au / Ge is selectively formed on both sides of the gate electrode to form a source electrode 39 and a drain electrode 40, whereby GaAs The basic structure of the field effect transistor is completed.
[0012]
[Problems to be solved by the invention]
However, in the above-described electrode patterning process, it is difficult to form a fine pattern with good processability because the dry etching method and the ion milling method are used, and in the dry etching process or the ion milling process. Since particles such as ions strike the surface of the semiconductor layer, there is a problem that the semiconductor layer is damaged.
[0013]
In order to solve such a problem, a lift-off method may be used. However, when a W-based electrode material is used, the W-based material has a high melting point and a low vapor pressure, so that vapor deposition by resistance heating or electron beam heating is performed. An electrode cannot be formed by this method, and it is necessary to deposit an electrode film using a sputtering method as described above. When the sputtering method is used, there is a problem that the lift-off method cannot be used because the resist is modified by heat during sputtering and cannot be removed by a normal resist removing solution.
[0014]
In addition, refractory metals such as W and WSiN are highly stressed metals, and a large stress is applied to the interface between the electrode and the semiconductor layer. This stress may affect the reliability of the semiconductor element. There is a problem that the electrode is easily peeled off.
Therefore, in the case of the above-described non-alloy gate electrode, the LaB ₆ layer 35 is interposed in order to relieve stress, but the problem that the workability of the fine pattern due to the adoption of the sputtering method is still not solved. It is.
[0015]
Accordingly, an object of the present invention is to form a non-alloy electrode that can be finely processed and has low stress by selecting an electrode material.
[0016]
[Means for Solving the Problems]
FIG. 1 is an explanatory diagram of the principle configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
Refer to FIG. 1. (1) In the compound semiconductor device of the present invention, as an electrode provided on the compound semiconductor layer 1, the first heat-resistant metal layer 2, the non-heat-resistant metal layer 3, and the W Pd having a thickness of 5 nm or less is interposed between the compound semiconductor layer 1 and the first refractory metal layer 2 using an electrode having a laminated structure in which the second refractory metal layer 4 having higher vapor pressure is sequentially laminated. A binder conductive layer 5 is provided .
[0017]
In this way, by using a metal having a higher vapor pressure than W as the heat-resistant metal, it becomes possible to form a film by vapor deposition, so that the lift-off method can be used, and thereby a fine pattern with excellent thermal stability. This non-alloy electrode can be formed with high accuracy.
Moreover, since the low-resistance non-heat-resistant metal layer 3 is provided between the first heat-resistant metal layer 2 and the second heat-resistant metal layer 4 in order to relieve stress, good conductivity can be obtained. Stress can be relaxed without loss.
In particular, the binder conductive layer 5 made of Pd that can be formed by vapor deposition with a thickness of 5 nm or less between the compound semiconductor layer 1 and the first refractory metal layer 2, that is, on the exposed surface of the compound semiconductor layer 1. Since a conductive layer is provided to reduce the self-oxide and improve the adhesion of the electrode, peeling of the electrode can be prevented by improving the adhesion of the electrode, and contact with the oxide Since the increase in resistance value can be eliminated, the characteristics and reliability of the compound semiconductor device can be improved.
[0018]
(2) Moreover, the present invention is the above (1), wherein at least one of the first heat-resistant metal layer 2 and the second heat-resistant metal layer 4 is composed of either Mo or Mo alloy, Further, the non-heat resistant metal layer 3 is characterized by being composed of any one of Al, Ag, and Au.
[0019]
Thus, as the first heat-resistant metal layer 2 or the second heat-resistant metal layer 4, it is desirable to use Mo that can be deposited by a vapor deposition method, or a Mo alloy such as Mo · Al. As the refractory metal layer 3, stress can be relaxed without impairing good conductivity by using a soft metal with low resistance made of Al, Ag, and Au.
Further, by using Mo or Mo alloy having a thermal expansion coefficient smaller than that of Al, Ag and Au as the second heat-resistant metal layer 4, generation of hillocks formed on the surface of the electrode by application of heat is suppressed. Can do.
The first refractory metal layer 2 and the second refractory metal layer 4 may be made of different materials.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Here, the manufacturing process of the first embodiment of the present invention will be described with reference to FIG. 2, but the description of the device structure will be omitted for the sake of simplicity.
2A, first, a resist is applied to the entire surface of the InGaAs layer 11, and exposed to light and developed to form a resist pattern 12 having an electrode forming opening 13 having a width of, for example, 0.15 μm. .
[0023]
Refer to FIG.
Next, after depositing a Pd layer 20 having a thickness of 5 nm or less, for example, 1.0 nm using a resistance heating vapor deposition method, a thickness of the first heat-resistant metal layer is obtained using an electron beam vapor deposition method. but 2 to 50 nm, for example, is deposited Mo layer 14 of 10 nm, then, by the resistance heating evaporation method, a thickness of 100-600 nm, for example, it is deposited Al layer 15 of 300 nm, then again, the electron beam evaporation By using this method, a Mo layer 16 having a thickness of 2 to 50 nm, for example, 10 nm is deposited as the second refractory metal layer.
In this vapor deposition step, a multilayer film composed of the Pd layer 21, the Mo layer 17, the Al layer 18, and the Mo layer 19 is also deposited on the flat surface of the resist pattern 12.
[0024]
Next, referring to FIG. 2C, by removing the resist pattern 12 using a resist stripping solution, the multilayer film composed of the Pd layer 21, the Mo layer 17, the Al layer 18, and the Mo layer 19 is also removed simultaneously. A non-alloy electrode composed of the Pd layer 20, the Mo layer 14, the Al layer 15, and the Mo layer 16 is formed.
[0025]
Thus, in the first embodiment of the present invention, first, since the electrode is formed by the lift-off method, it can be formed without damaging the semiconductor layer and with high processing accuracy. .
[0026]
Second, since the Mo layer 14 serves as a barrier layer for the Al layer 15, In and Al constituting the InGaAs layer do not react to form a high-resistance intermediate compound, and thermal stability is improved. Excellent electrode.
[0027]
Incidentally, the contact resistivity of this non-alloy electrode was measured to be 6.59 × 10 ⁻⁸ Ω · cm ² , and this non-alloy electrode was annealed at 350 ° C. for 5 minutes assuming the heat treatment temperature in the wiring formation process. As a result, the contact resistivity after annealing was 3.68 × 10 ⁻⁸ Ω · cm ² , indicating that the contact resistivity tended to be improved.
[0028]
On the other hand, the contact resistivity of a conventional alloy electrode made of 35 nm AuGe layer, 11 nm Ni layer, and 254 nm Au layer formed for comparison is 1.32 × 10 ⁻⁶ Ω · cm ² , Similarly, the contact resistivity after annealing at 350 ° C. for 5 minutes was 3.19 × 10 ⁻⁶ Ω · cm ² , indicating a tendency for the contact resistivity to increase.
In the case of the conventional alloy electrode, it is considered that the reaction between Au and In becomes excessive due to annealing, thereby generating a high-resistance intermediate compound, while the second embodiment of the present invention is performed. In the form, since the Mo layer 14 becomes a barrier layer, Al and In do not react, and it is considered that a thermally stable characteristic can be obtained.
[0029]
Third, by forming the Mo layers 14 and 16 vertically, the stress difference from above and below applied to the intermediate Al layer 15 is reduced, and Mo (linear expansion coefficient α = 3.7-5. Since 3 × 10 ⁻⁶ / K) has a smaller thermal expansion coefficient than Al (α = 23.1 × 10 ⁻⁶ / K), generation of hillocks on the electrode surface can be suppressed.
[0030]
Fourth, Al, which is softer than Mo, has low stress, and even if Mo, which has a large stress, is used as an electrode, the stress applied to the entire electrode can be reduced, so that peeling of the electrode can be suppressed. Thereby, the reliability of the compound semiconductor device can be improved.
[0035]
Further, in order to measure the adhesion of the non-alloy electrode, an Al piece was adhered to the uppermost Mo layer 16 with an adhesive, and the force for pulling up the Al piece and peeling the electrode was measured. / Cm ² .
On the other hand, the adhesion force of the alloy electrode formed for the above comparison is 694 kgf / cm ² , and therefore, it is confirmed that the non-alloy electrode of the present invention can obtain an adhesion degree equal to or higher than that of the conventional alloy electrode. It was done.
[0036]
Such an improvement in adhesion and low contact resistivity is thought to be due to the use of a highly reducing Pd layer as the binder conductive layer. Pd reduces the natural oxide film formed on the surface of the InGaAs layer 11. Since it reacts with the InGaAs layer 11, it is considered that the adhesion is improved and the resistivity is also lowered.
[0037]
In addition, when the surface state of the non-alloy electrode after annealing at 350 ° C. for 5 minutes was observed, no hillock was observed, but the Pd / Mo / Al three-layer structure electrode formed for comparison was annealed. Later hillocks were observed. This is because, in the case of the non-alloy electrode of the present invention, the Mo layer 16 having a smaller thermal expansion coefficient than the Al layer 15 is provided as the uppermost layer, so that this Mo layer suppresses generation of hillocks due to thermal stress. it is conceivable that.
[0038]
The Pd layer 20 as the binder conductive layer in the first embodiment reacts with the underlying InGaAs layer 11 in the annealing process at 350 ° C. for 5 minutes, but the Pd layer 20 has a thickness of 5 nm or less. Therefore, the reaction between the InGaAs layer 11 and the Pd layer 20 does not proceed excessively to deteriorate the electrical characteristics.
[0039]
Thus, in the first embodiment of the present invention, since the binder conductive layer made of Pd is provided between the first heat-resistant metal layer and the underlying semiconductor layer, the adhesion can be improved. In particular, when a compound semiconductor device is manufactured by batch processing, a natural oxide film is formed on the exposed surface of the semiconductor layer, which is important.
[0040]
Having thus described the implementation of the embodiment of the present invention, the present invention is not limited to the configuration and conditions described in the form of implementation, it can be variously modified in the.
For example, Mo is used as the first heat-resistant metal layer and the second heat-resistant metal layer, but there is no limitation to Mo, and Mo alloys such as Mo / Al may be used. Furthermore, a heat-resistant metal having a high vapor pressure and therefore capable of being formed by an evaporation method and having a low reactivity with the base semiconductor layer may be used.
[0041]
Further, in the implementation described above, although the first refractory metal layer and the second refractory metal layer constituted by the same Mo layer, not necessarily the same metal, to each other, different A metal may be used.
[0042]
Further, in the implementation described above, is used an Al layer as a non-refractory metal to reduce the stress, it is not limited to Al layer, low resistance Au or soft like the Al Ag may be used.
[0043]
Further, in the implementation of the above it is not described in the element structure of a compound semiconductor device in order to simplify the description, the invention, HEMT, MESFET, or, HBT (heterojunction bipolar transistor) such as It is used as an ohmic electrode or a Schottky barrier gate electrode of a high-frequency compound semiconductor device, and further applied to a compound optical semiconductor device such as a semiconductor laser having an InGaAs layer or the like as a cap layer.
[0044]
The underlying semiconductor of the electrode is not limited to an InGaAs layer, but is suitable for a III-V group compound semiconductor layer containing In as a constituent element such as an InAlAs layer or an InGaP layer, but does not contain In. The present invention can be applied to a layer or the like, and can be applied to an n-type layer or a p-type layer as the conductivity type of the underlying semiconductor layer.
[0045]
【The invention's effect】
According to the present invention, as the electrode provided on the compound semiconductor layer, the first heat-resistant metal layer having a higher vapor pressure than W that can be formed by vapor deposition, the non-heat-resistant metal layer, and the vapor pressure higher than that of W. Because it uses a multilayer structure electrode with a second refractory metal layer, an electrode with excellent thermal stability can be formed by the lift-off method, thereby enabling fine processing without damaging the semiconductor device. become.
[0046]
Further, by providing a binder conductive layer such as a Pd layer between the base semiconductor layer and the first refractory metal layer, the natural oxide film on the surface of the base semiconductor layer can be reduced, so that the adhesion of the electrode Can be improved, and the contact resistivity can be reduced, whereby peeling of the electrode can be prevented.
[0047]
By synergistically exhibiting such effects, it is possible to realize a workable electrode structure with good electrical characteristics and high reliability, thereby improving the performance and reliability of compound semiconductor devices. The place that contributes to
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a basic configuration of the present invention.
FIG. 2 is an explanatory diagram of a manufacturing process according to the first embodiment of this invention.
FIG. 3 is an explanatory diagram of a manufacturing process of a conventional GaAs field effect transistor.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Compound semiconductor layer 2 1st heat resistant metal layer 3 Non heat resistant metal layer 4 2nd heat resistant metal layer 5 Binder conductive layer 11 InGaAs layer 12 Resist pattern 13 Opening 14 Mo layer 15 Al layer 16 Mo layer 17 Mo Layer 18 Al layer 19 Mo layer 20 Pd layer 21 Pd layer 31 Semi-insulating GaAs substrate 32 Undoped GaAs layer 33 n-type GaAs layer 34 WSi layer 35 LaB ₆ layer 36 W layer 37 Resist pattern 38 Etching gas 39 Source electrode 40 Drain electrode

Claims (2)

As an electrode provided on the compound semiconductor layer, a laminated structure in which a first heat-resistant metal layer having a vapor pressure higher than W, a non-heat-resistant metal layer, and a second heat-resistant metal layer having a vapor pressure higher than W are sequentially laminated. And a binder conductive layer made of Pd having a thickness of 5 nm or less is provided between the compound semiconductor layer and the first refractory metal layer .   At least one of the first heat-resistant metal layer and the second heat-resistant metal layer is made of either Mo or Mo alloy, and the non-heat-resistant metal layer is made of Al, Ag, and Au. The compound semiconductor device according to claim 1, wherein the compound semiconductor device comprises any one of the above.

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