JP4144090B2 - Music generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for generating waveform data of musical sound (speech) to be generated by reading out waveform data for generation stored in a memory or the like.
[0002]
[Background Art and Problems to be Solved by the Invention]
Currently, many musical tone generators should store digital data (waveform data) obtained by sampling the sound of musical instruments in a memory and read out the waveform data from the memory at any timing to generate sound. Music waveform data is generated. This method has an advantage that the amount of data can be suppressed because the pitch of the musical sound can be controlled by the speed of reading the waveform data. .
[0003]
Many of the sounds of musical instruments are continuous sounds, not attenuated sounds such as drum sounds. If all the continuous sounds are sampled, the amount of data is naturally huge. From this, normally, the musical sound generator determines two points (start point and end point) to be repeatedly reproduced in the entire waveform data, and repeatedly reproduces the waveform data between them, thereby generating a continuous sound. It is designed to create.
[0004]
Among musical tone generators equipped with such a loop function, a function for synchronizing a loop of waveform data between channels (hereinafter referred to as a loop synchronization function for convenience) to decorate a musical tone to be generated. In addition, there are some installed. The synchronization of the loop by the function is usually performed by looping the waveform data of the slave channel in accordance with the waveform data loop of the master channel.
[0005]
The conventional musical sound generator has realized its loop synchronization function by executing software. However, in order to realize this function, not only manages the points that are being played back in the entire waveform data in each channel, but also changes the points in the slave channel to match the loop in the master channel. It is also necessary to perform complicated processing such as. For this reason, there was a problem that the load at the time of execution of the software was heavy.
[0006]
Naturally, the processing for all channels must be completed within one sampling period. Because of such time constraints, the above problems are brought about in the form of a decrease in the number of channels that can be processed, that is, a decrease in the number of musical sounds that can be generated simultaneously.
[0007]
An object of the present invention is to make it easier to synchronize loops of waveform data between channels.
[0008]
[Means for Solving the Problems]
  The musical tone generator of the present invention isWaveform storage means for storing the waveform data of the musical sound to be sounded, address generation information for generating an address for reading waveform data from the waveform storage means, and discriminating information for discriminating the master channel are stored for each channel An information storage means, a reading means for reading out the address generation information and the discrimination information sequentially for each channel from the generation information storage means, and an address read by the readout means by the read discrimination information Based on the read address generation information, a determination means for determining whether the generation information corresponds to a master channel or a slave channel that designates a channel determined to be the master channel as a master. Read waveform data from the waveform storage means Address generating means for generating address information, loop start storage means for storing data indicating whether or not the master channel loop is started, and each time the determination means determines that it corresponds to the master channel. A loop detection unit that detects whether or not a loop is started based on the address generated by the address generation unit and updates the stored contents of the loop start storage unit based on the determination result; and the loop detection unit In response to the detection of the loop start by the control unit, the address generation unit is controlled to change the address of the master channel to the loop start address, and each time the determination unit determines that the address corresponds to the slave channel. The stored contents of the loop start storage means are referred to and the stored contents are Data indicating the start of a group, the address control means for controlling the address generation means to change the address of the slave channel to a loop start address, and the address based on the address generated by the address generation means Waveform reading means for reading waveform data from the waveform data storage means;It comprises.
[0009]
  In the above configuration,The discrimination information includes master channel information representing a master channel, and the discrimination means includes a comparison means for comparing a channel corresponding to the read address generation information with a channel represented by the master channel information. It is desirable to have.
The discrimination information includes identification information for identifying whether the channel is a master channel or not.
It is desirable.
Further, the address generation information includes an address value advanced every predetermined period, an address indicating the start position of the waveform data of the musical sound to be generated, an address value indicating the last position of the waveform data, and a start position at which reproduction is repeated. It is desirable to consist of an address representing.
  Further, the musical sound generating apparatus of the present invention is a waveform storage means for storing waveform data of a musical sound to be generated, address generation information for generating an address for reading waveform data from the waveform storage means, and whether or not the master channel. Generating information storage means storing identification information for each channel, reading means for sequentially reading out the address generation information and the identification information for each channel from the generation information storage means, and the read identification Based on the information, determination means for determining whether the address generation information read by the reading means corresponds to a master channel or a slave channel, and based on the read address generation information, Address that generates address information for reading waveform data from the waveform storage means Generated by the address generation means, and a loop start storage means for storing data indicating whether or not the master channel loop is started, and the address generation means each time the determination means determines that the master channel corresponds to the master channel. The loop detection unit detects whether or not the loop is started based on the determined address, and updates the stored contents of the loop start storage unit based on the determination result, and the loop detection is detected by the loop detection unit. In response, the address generation means is controlled to change the address of the master channel to a loop start address, and the memory of the loop start storage means is stored every time the determination means determines that it corresponds to the slave channel. Refer to the contents, and if the stored contents are data indicating the loop start, Address control means for controlling the address generation means to change the address of the slave channel to a loop start address, and waveform reading for reading out waveform data from the waveform data storage means based on the address generated by the address generation means And means.
[0011]
  In the present invention, an address for reading the waveform data for generation is generated.Address generation partAnd manage and control itControl partThe address generation part performs an operation for generating an address. The calculation or the like can be performed only by hardware. This reduces the load on the control part that executes the software.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
<First Embodiment>
FIG. 1 is a configuration diagram of an electronic musical instrument equipped with a musical sound generator according to the first embodiment.
[0013]
As shown in FIG. 1, the electronic musical instrument includes a CPU 101 that controls the entire musical instrument, a RAM 102 that the CPU 101 uses for work, a ROM 103 that stores programs executed by the CPU 101 and various control data, a keyboard, An operator group 104 composed of switches, a musical sound generator 105 that generates waveform data of musical sounds to be generated according to instructions from the CPU 101, a ROM 106 that stores waveform data obtained by sampling sounds of various musical instruments, and musical tone generation A DA converter 107 that converts waveform data input from the device 105 into an analog audio signal and an acoustic circuit 108 that converts the audio signal into sound and outputs the sound are configured.
[0014]
The operation of the above configuration will be described.
[0015]
When the power is turned on, the CPU 101 reads out a program from the ROM 103 and executes it, thereby starting control of the entire instrument. The control is performed in accordance with a user operation on the operator group 104 while using the RAM 102 for work.
[0016]
The user's operation on the operator group 104 is detected by, for example, scanning it and analyzing the scanning result. The CPU 101 operates the electronic musical instrument according to the contents designated by the user via the operator group 104 by giving various settings and instructions to the musical sound generation device 105 based on the analysis result.
[0017]
FIG. 2 is a circuit configuration diagram of the musical tone generator 105.
[0018]
As shown in FIG. 2, the musical tone generator 105 generates a control signal generator 201 that controls the entire apparatus 105 and waveform data for each channel (each channel corresponds to one musical tone). Using the RAM 202 for storing the data for reading, the waveform reading address generating unit 203 for generating an address for reading the waveform data from the ROM 106, and the waveform data read from the ROM 106 by the address generated by the address generating unit 203 A waveform generation unit 204 that generates waveform data of a musical tone to be played, and a RAM I / F (hereinafter abbreviated as I / F) 205 that mediates exchange of data between the RAM 202 and the units 201 to 204. It is configured.
[0019]
In the above configuration, the operation of the tone generator 105 will be described. Here, for the sake of convenience, the description will be given focusing on the operation for one channel.
[0020]
The CPU 101 allocates a musical sound channel to be generated according to the key pressed every time the user presses the key, and generates an identifier for instructing the musical sound generation, a channel number, and waveform data of the musical sound. Data is sent to the tone generator 105 as a control command.
[0021]
The control command is sent to the control signal generator 201 via the I / F 205. The I / F 205 sends only the identifier, channel number, and master channel number, for example, to the control signal generator 201 in the control command. Upon receiving this, the control signal generator 201 outputs an address specified from the channel number to the I / F 205 and stores the remaining data in the control command in the RAM 202.
[0022]
FIG. 4 is a diagram for explaining the contents stored in the RAM 202 in the musical tone generator 105 in this way.
[0023]
In this embodiment, 32 channels of sound are possible. For this reason, as shown in FIG. 4, data related to 0 to 32 channel music reproduction can be stored. In the figure, in the address expressed by a three-digit hexadecimal number, the upper two digits represent a channel, and the other one digit represents an address in an area assigned to the channel. The area has a storage capacity for 16 addresses, addresses 000B to 00FB for 0 channel and addresses 1FOB to IFFB for 31 channel. The number of bits of each address is the number of bits determined according to the data stored therein.
[0024]
The ADC in FIG. 4 indicates the address of the waveform data to be read from the ROM 106. The initial value, in other words, the address sent as a control command is the address of the waveform data located at the head of the waveform data to be reproduced. Similarly, ADE is the last address (end address) where the waveform data is stored, and ADL is the waveform data address (loop start address) that is the start position for repeating reproduction (loop) in the waveform data. Each is shown. The continuous sound is performed by repeatedly reproducing the waveform data between addresses ADL to ADE.
[0025]
FLP is data (flag) indicating whether or not the loop is performed, and is 1 when the loop is performed, and 0 when the loop is not performed. As a matter of course, the initial value is zero. ESTP is data indicating a difference in an amount that the address from which waveform data is to be read exceeds the end address ADE during a loop. As a matter of course, the initial value is zero. MCH is data indicating the number of the master channel, and specifies that the tone of this channel is to be looped in accordance with the tone loop of the master channel. If it is the master channel, its value is its own channel number. FRN is data (step width) indicating an address value advanced every sampling period.
[0026]
The above data is stored in the control command and sent to the musical tone generator 105. The control signal generator 201 stores it in the area specified from the channel as shown in FIG. Those data are erased when a control command for instructing to mute the musical sound to be generated is received from the CPU 101. Thereby, the musical sound is muted. The control command stores, for example, at least an identifier indicating that fact and a channel number.
[0027]
The data stored in the RAM 202 for each channel is read during the processing period of the channel and sent to the waveform read address generator 203. The control signal generation unit 201 sequentially outputs, to the I / F 205, the address (value) where the data of the target channel is stored from the RAM 202. The I / F 205 reads the data stored at those addresses from the RAM 202 and sends the data to the waveform reading address generator 203.
[0028]
The waveform read address generator 203 stores data sent from the RAM 202 via the I / F 205 in the corresponding register, performs various calculations using the data stored in the register, and reads from the ROM 106. An address from which waveform data is to be read is generated. Data updated according to the generation of the address is sent to the I / F 205.
[0029]
The control signal generator 201 outputs an address for storing data in the I / F 205 in accordance with the transmission timing. Thereby, the I / F 205 rewrites (updates) data in the RAM 202.
[0030]
The waveform reading address generation unit 203 sequentially outputs two adjacent addresses (values) to the ROM 106 in one channel. The waveform data stored at those addresses is read from the ROM 106.
[0031]
When the waveform generation unit 204 receives the waveform data read from the ROM 106, it generates waveform data of a musical tone to be generated by performing linear interpolation or the like. The generated waveform data is added to the waveform data of other channels generated so far. Thereby, after the generation of the waveform data for all channels is completed, the waveform data obtained by adding all the waveform data for all channels is output to 1 / F 205. The waveform data is sent to the DA converter 107 shown in FIG.
[0032]
The control signal generator 201 controls the operation of each of the units 203 and 204 by outputting a clock and various control signals. The control signal is changed according to the signal input from them. Thereby, the units 203 and 204 are operated according to the situation.
[0033]
FIG. 3 is a circuit configuration diagram of the waveform read address generator 203. Next, with reference to FIG. 3 and various explanatory diagrams shown in FIGS. 4 to 8, the configuration of the control signal generator 201 and the waveform read address generator 203 will be described in detail.
[0034]
In FIG. 3, 301 to 303 are SL (selector), 304 to 313 are F / F (flip-flop), 314 is an adder / subtracter, 315 is a comparator (COMPARATOR), 316 is an address incrementer (ADDRESS INCREMENTER), RI, and RO is a data bus.
[0035]
The character strings in FIG. 3 indicate the following contents, respectively.
[0036]
A character string located below “F / F” is a register name. Each of the F / Fs 304 to 313 is a register configured by an F / F of the number of bits of contents to be actually stored therein. However, F / F is used here to avoid complications. In order to clarify the correspondence between the data held therein and the data shown in FIG. 4, a character string of the data shown in FIG. 4 is used. The character string indicating the register name is also used as the output signal name for convenience. The character string with “CK” added to the head of the character string is the name of the clock (control signal) input to the F / F (register) corresponding to the character string with the “CK” added.
[0037]
The character string located below each SL 301 to 303 is its select signal name. The numerical value located above the input signal of each SL 301 to 303 indicates the value of the select signal when it is selected. For example, in SL302, when the value of the select signal FIAS is 0, the output signal of the F / F 304 is selected. Similarly, when the value is 1, the output signal of the F / F 305 is selected. It shows that the output signal of F306 is selected. “FSUB” below the adder / subtractor 314 is a control signal that indicates whether to perform addition / subtraction. When the value is 0, addition is performed, and when the value is 1, subtraction is performed by the adder / subtractor 314. When the value is 2, the output signal FIA of the SL 302 is output as it is. Various control signals including clocks, select signals and the like input to the units 301 to 315 are output from the control signal generation unit 201.
[0038]
As shown in FIG. 5, the control signal generation unit 201 performs a process of generating waveform data in units of channels sequentially from the smallest channel number. Thereafter, the control signal for each channel is taken as an example in the case where there are two channels, N and K (K <M <N), where the master channel is the M channel and the M channel is the master channel. The operations of the generation unit 201 and the waveform reading address generation unit 203 (each unit constituting the generation unit 201) will be described in detail.
[0039]
First, the operation of each part constituting the control signal generation unit 201 and the waveform read address generation unit 203 during processing of the M channel which is the master channel will be described with reference to the timing chart shown in FIG.
[0040]
The system clock shown in FIG. 6 is a clock generated by the control signal generator 201 for controlling each unit in the musical tone generator 105 including the waveform read address generator 203. The control signal generator 201 outputs a control signal to be output in synchronization with the clock. The cycle below the system clock is a processing time indicated by dividing the processing time allocated to one channel by one period of the system clock. The operation will be described by paying attention to the cycle for convenience.
[0041]
In the present embodiment, 16 cycles of 0H to FH (H is a symbol indicating hexadecimal notation) are assigned per channel. Therefore, one sampling period is 512 (= 16 × 32) system clocks.
[0042]
When the processing channel shifts to the M channel, data read from the RAM 202 is transferred to the data bus RO in the order of ADC, FRN (including MCH), ADE, FLP (including ESTP) of the master channel, and ADL. Sequentially output from the I / F 205.
[0043]
The control signal generator 201 activates the control signal of the F / F (register) that holds it in accordance with the output timing of those data (high level with a logical value of 1. All the periods are ½ cycle periods. ). Specifically, after setting the value of the select signal to 0 in cycle 0, the clock CKADC is activated in cycle 1 to hold the data ADC in the F / F 304, and both the clocks CKFRN and CKMCH are activated in cycle 2. , F / F309 holds data FRN, F / F310 holds data MCH, clock CKADE is activated in cycle 3 and data ADE is held in F / F307, and clocks CKFLPM and CKESTPM are both activated in cycle 4 The F / F 311 holds the data FLP and the F / F 306 holds the data ESTP (including FLP) (they are master channel data), and the clock CKADL is activated in cycle 5 to activate the data ADL in the F / F 308. Hold . Thereby, the data to be held in each of the F / Fs 304 to 311 is held.
[0044]
In the cycle 4, the control signal generation unit 201 sets the value of the select signal FIAS to 0, the value of the select signal FIBS to 2, and the value of the control signal FSUB to 0. This causes the adder / subtractor 314 to perform an addition operation for adding the data ADC of the F / F 304 to the data FRN of the F / F 309. The adder / subtractor 314 outputs the addition result (= FRN + ADC) as an output FO.
[0045]
In cycle 4, data MCH is held in F / F 310 and output to comparator 315. The control signal generator 201 outputs the master channel number CHCY of the current processing channel to the comparator 315. The comparator 315 sets the value of the output signal FSLV to 1 when they are different. The output signal FSLV is output to the control signal generator 201. Since the M channel is a master channel, the value of the output signal FSLV here is 0.
[0046]
In the next cycle 5, the control signal generation unit 201 sets the value of the select signal ADCIS to 1 and activates the clock CKADC. Thereby, the calculation result (= FRN + ADC) of the adder / subtractor 314 is held in the F / F 304. On the other hand, the value of the select signal FIBS is set to 0, and the value of the control signal FSUB is set to 1. This causes the adder / subtractor 314 to perform an operation of subtracting the F / F 304 data ADC from the F / F 307 data ADE. The adder / subtractor 314 outputs the subtraction result (= ADE-ADC) as an output FO.
[0047]
In cycle 6, the clocks CKFLP and CKESTP are both activated. Thereby, the calculation result (= ADE-ADC) of the adder / subtractor 314 is held in the F / Fs 313 and 305.
[0048]
If the read address ADC of the updated waveform data is larger than the end address ADE, it means that it is necessary to loop, and the calculation result is a negative value. F / F 313 is 1 bit, and the sign of the operation result is input. For this reason, when that situation occurs, the value held by the F / F 313 is 1. The value of F / F 313 is output to the control signal generator 201. Note that the difference (= ADC−ADE) when the waveform data read address ADC becomes larger than the end address ADE will be referred to as an interlace step hereinafter.
[0049]
On the other hand, the control signal generator 201 sets the value of the select signal FIAS to 1, the value of the select signal FIBS to 1, and the value of the control signal FSUB to 1. This causes the adder / subtractor 314 to perform an operation for subtracting the data ESTP of the F / F 304 (the calculation result immediately before the adder / subtractor 314) from the data ADL of the F / F 308. The adder / subtractor 314 outputs the subtraction result (= ADL-ESTP) as an output FO. Since ESTP <0 at the time of the loop, an operation for adding the absolute value of the data ESTP to the data ADL is actually performed.
[0050]
In the subsequent cycle 7, the clock CKADC is made active, and the operation result (= ADL-ESTP) of the adder / subtractor 314 is held in the E / F 304. The updated data ADC held therein is sent to the I / F 205 via the data bus RI and written into the RAM 202. On the other hand, the value of the control signal FSUB is set to 2 while the value of the select signal FIAS remains 1. Thereby, the data held in the F / F 305 is output from the adder / subtractor 314 as it is.
[0051]
In cycle 8, the clock CKADC is activated. Thereby, the data ESTP held by the F / F 305 is sent to the I / F 205 via the F / F 304 and the data bus RI and written to the RAM 202. Otherwise, the clock CKADO is activated. Thereby, the data ADC held in the F / F 304 before the data ESTP is held in the F / F 312 and sent to the address incrementer 316. As a result, the address incrementer 316 outputs the data ADO (ADC) held in the F / F 312 from the cycle 8 as the address EADR, and a value obtained by incrementing the value at the cycle 0 in the next channel (= ADO + 1). Is output. As a result, two waveform data having different address values by one are read from the ROM 106 and sent to the waveform generation unit 204 shown in FIG.
[0052]
The timing chart shown in FIG. 6 shows the operation when looping. The value of F / F 313 is 0 when it is not in a situation of causing the loop. When the value is 0, the control signal generation unit 201 does not activate the clock CKADC in cycle 7. Thereby, the data ADC held in the cycle 5 is held in the F / F 304 until the cycle 8 is shifted to. This is basically the only operational difference between looping and not.
[0053]
Next, the operation of each part of the control signal generation unit 201 and the waveform read address generation unit 203 during processing of the N channel, which is an M channel slave channel, will be described with reference to the timing chart shown in FIG. FIG. 7 is after a loop has occurred in the M channel.
[0054]
Even if the processing target shifts from the master channel to the slave channel, the basic operation is the same. For this reason, only the parts that differ from the above-described operation for the M channel will be described.
[0055]
First, in cycle 2, the clock CKMCH becomes active and the data MCH is held in the F / F 310. Thereby, the value of the output signal FSLV of the comparator 315 becomes 1, and the control signal generator 201 is notified that the N channel is a slave channel.
[0056]
In cycle 4, clocks CKFLPM and CKESTPM are both activated, and data FLP is held in F / F 311 and data ESTP is held in F / F 306, respectively (they are M channel data). By holding the data FLP in the F / F 311, the control signal generator 201 is notified that the loop has been performed on the M channel.
[0057]
  Based on the value held in the F / F 311, the control signal generation unit 201 selects the select signal F output in cycle 6.IDetermine the value of AS. Specifically, if the value is 1, it is set to 2. As a result, in cycle 6, the adder / subtracter 314 sends the data ADL of F / F308 to the data ESTP of F / F306.MPerforms an operation that subtracts. As a result, in the subsequent cycle 7, the calculation result (= ADL-ESTPM) is held in the F / F 304. In other words, in accordance with the loop of the M channel, the value obtained by adding the excess from the end address ADE at that time to the data ADL of the N channel is held in the F / F 304.
[0058]
  At the time of N channel processing, the above-mentioned part is different from that at the time of M channel processing. When the loop is simply performed with the N channel, the control signal generation unit 201 selects the select signal F output in cycle 6.IOnly the AS value is set to 1. When the loop is not performed, the clock CKADC is not activated in cycle 7 as in the case of M channel processing.
[0059]
FIG. 8 is a timing chart showing operations of the control signal generation unit 201 and the waveform read address generation unit 203 during the processing of the K channel, which is an M channel slave channel. The operation when the K channel is processed for the first time after looping with the M channel is shown. The details of the operation are basically the same as those in the N-channel processing, and the description is omitted.
[0060]
FIG. 9 is a diagram for explaining a musical sound waveform generated / sounded by the waveform data read by the waveform reading address generation unit 203 from the ROM 106 as described above.
[0061]
As shown in FIGS. 9A and 9B, the period of the master channel musical sound (reproduction waveform) regardless of whether one period of the musical sound (reproduction waveform) of the slave channel is longer or shorter than that of the master channel. At the same time, a loop in the slave channel is performed.
[0062]
The loop synchronization between the channels is generated by generating the address of the waveform data to be read from the ROM 106 in the waveform reading address generating unit 203 by the control signal generating unit 201 outputting various control signals as described above. To make it happen. The control signal generator 201 itself is not required to perform various calculations. As described above, since the load for generating the waveform data is distributed to the waveform reading address generation unit 203, the load on the generation unit 201 itself can be reduced.
[0063]
In this embodiment, when the loop is performed on the master channel, the jump step at that time is added to the loop start address ADL of the slave channel to perform the loop on the slave channel. I don't have to. For example, when the loop is performed on the master channel, the next read address of the slave channel may be used as the loop start address ADL.
<Second Embodiment>
In the first embodiment, all data for generating waveform data is stored in the RAM 202. On the other hand, in the second embodiment, the amount of data stored in the RAM 202 is smaller.
[0064]
The configuration of the musical tone generator according to the second embodiment is basically the same as that of the first embodiment. For this reason, the reference numerals used in the description of the first embodiment are used as they are, and only the portions different from the first embodiment will be described.
[0065]
In the second embodiment, the configuration of the waveform read address generation unit 203 is changed from the first embodiment in accordance with the reduction in the amount of data stored in the RAM 202. Therefore, only the configuration of the waveform reading address generation unit 203, the contents stored in the RAM 202, and the operations of the control signal generation unit 201 and the waveform reading address generation unit 203 will be described.
[0066]
FIG. 10 is a circuit configuration diagram of the waveform read address generator 203 according to the second embodiment. First, the configuration of the waveform read address generator 203 will be described with reference to FIG.
[0067]
As shown in FIG. 10, in the second embodiment, an SL (selector) 1001 is provided before the F / F 306. The SL 1001 selects either the output signal FO of the adder / subtractor 314 or the output signal of the F / F 306 according to the value of the select signal ESTPMIS and outputs the selected signal to the F / F 306.
[0068]
The F / Fs 310 and 311 and the comparator 315 are omitted. Instead, F / Fs 1003, 1004, and SL1002 are provided. The F / F 1003 is connected to the data bus RO. The SL 1002 selects either the output signal FO of the adder / subtractor 314 or the output signal of the F / F 1004 according to the value of the select signal FLPMIS and outputs the selected signal to the F / F 1004. The output signals of the F / Fs 1003 and 1004 are both output to the control signal generator 201.
[0069]
FIG. 11 is a diagram for explaining the contents stored in the RAM 202.
[0070]
  FIG.As shown in the figure, in the second embodiment, only the data FSLV is stored in the RAM 202 instead of the data FLP, ESTEP, and MCH. The data indicates whether the channel is a master channel or a slave channel, and 0 is set for the master channel and 1 is set for the slave channel. The data FSLV is also data sent from the CPU 101 as a control command.
[0071]
Also in the second embodiment, as shown in FIG. 12, a process of generating waveform data in units of channels is performed in order from the smallest channel number. Hereinafter, the operation of the control signal generation unit 201 and the waveform read address generation unit 203 (each unit constituting the signal) during processing of four consecutive channels N to (N + 3) will be described with reference to the timing charts of FIGS. However, this will be described in detail.
[0072]
The N and (N + 3) channels are master channels, and the (N + 1) and (N + 2) channels are slave channels with the N channel as a master channel. Since the operations at the time of processing each channel are similar to those of the first embodiment, only the main points of the operation will be described.
[0073]
First, the operations of the control signal generation unit 201 and the waveform reading address generation unit 203 (each unit constituting the same) during N channel processing will be described with reference to FIG.
[0074]
When the processing channel shifts to the N channel, the data read from the RAM 202 is sequentially output from the I / F 205 to the data bus RO in the order of ADC, FRN (including FSLV), ADE, and ADL.
[0075]
The control signal generator 201 activates a control signal of an F / F (register) that holds the data in accordance with the output timing of the data. At that time, in the cycle 2, the clock CKFSLV is activated and the F / F 1003 holds the data FSLV. The control signal generation unit 201 determines whether or not the currently targeted channel is a master channel from the value held by the F / F 1003 in this way.
[0076]
In cycle 4, the values of select signals FLPMIS and ESTPMIS are set to zero. In the subsequent cycle 5, the clocks CKFLPM and CKESTP are activated. This causes the F / Fs 306 and 1004 to hold the output signal FO of the adder / subtractor 314. Note that the F / F 1004 holds the value of the sign of the output signal FO.
[0077]
By making the clock CKFLPM active, the value of the F / F 1004 is 1 (a value indicating that a looping situation has been reached). Therefore, the control signal generator 201 activates the clock CKADC in cycle 6. At this time, the value of F / F 313 is also 1.
[0078]
In this way, at the time of master channel processing, the control signal generator 201 updates the contents held by the F / Fs 306 and 1004. The contents are held until the processing of the slave channel is completed. Thereby, the amount of data stored in the RAM 202 is reduced.
[0079]
Another master channel (N + 3) channel is a channel that is not looped. For this reason, as shown in FIG. 16, the clock CKADC is not activated in cycle 6. Basically, this is the only difference in operation from N-channel processing.
[0080]
Next, the operation of each part of the control signal generation unit 201 and the waveform reading address generation unit 203 during processing of the (N + 1) channel, which is an N channel slave channel, will be described with reference to the timing chart shown in FIG. .
[0081]
Even if the processing target shifts from the master channel to the slave channel, the basic operation is the same. For this reason, the description will be made by paying attention only to the difference from the above-described operation for the N channel.
[0082]
In cycle 4, select signals FLPMIS and ESTPMIS are set to 1. In the subsequent cycle 5, the clocks CKFLPM and CKESTP are activated. As a result, the contents of the F / Fs 306 and 1004 are held as they are.
[0083]
FIG. 15 is a timing chart showing operations of the control signal generation unit 201 and the waveform read address generation unit 203 during processing of the (N + 2) channel which is an N channel slave channel. The contents of the operation are basically the same as those at the time of (N + 1) channel processing, and thus description thereof is omitted.
[0084]
In the second embodiment, data (FLP, ESTPM) at the time of master channel processing is held by the F / F (registers) 306 and 1004 in this way. Thereby, the amount of data stored in the RAM 202 is reduced. Further, compared with the first embodiment, there is an effect that the circuit scale of the waveform read address generation unit 203 can be further reduced by making the comparator 315 unnecessary.
[0085]
Even in the second embodiment, when looping is performed on the master channel, the jump step at that time is added to the loop start address ADL of the slave channel, and the loop is performed on the slave channel. You do n’t have to.
[0086]
Further, in the present embodiment (first and second embodiments), it is premised that loop synchronization between channels is performed, but this need not be premised. The waveform read address generator 203 may simply generate an address for reading the waveform data. Of course, you may be able to do that.
[0087]
【The invention's effect】
  As described above, the present invention generates an address for reading generation waveform data.Address generation partAnd manage and control itControl partThe address generation part performs an operation for generating an address. For this reason, it is possible to reduce the load on the control portion that executes the software.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an electronic musical instrument equipped with a musical sound generator according to a first embodiment.
FIG. 2 is a circuit configuration diagram of a musical sound generator.
FIG. 3 is a circuit configuration diagram of a waveform read address generator.
FIG. 4 is a diagram for explaining the contents stored in a RAM in the musical sound generating device.
FIG. 5 is a timing chart showing operations of a control signal generation unit and a waveform read address generation unit.
FIG. 6 is a timing chart showing operations of a control signal generation unit and a waveform read address generation unit during M channel processing.
FIG. 7 is a timing chart showing operations of a control signal generation unit and a waveform read address generation unit during N-channel processing.
FIG. 8 is a timing chart showing operations of a control signal generation unit and a waveform read address generation unit during K channel processing.
FIG. 9 is a diagram for explaining a musical sound waveform generated and generated by waveform data read by a waveform reading address generation unit.
FIG. 10 is a circuit configuration diagram of a waveform read address generation unit (second embodiment);
FIG. 11 is a diagram for explaining the contents stored in a RAM in the musical sound generator (second embodiment).
FIG. 12 is a timing chart showing operations of a control signal generation unit and a waveform read address generation unit (second embodiment).
FIG. 13 is a timing chart showing operations of a control signal generation unit and a waveform read address generation unit during N-channel processing (second embodiment).
FIG. 14 is a timing chart showing operations of a control signal generation unit and a waveform read address generation unit during (N + 1) channel processing (second embodiment);
FIG. 15 is a timing chart showing operations of a control signal generation unit and a waveform read address generation unit during (N + 2) channel processing (second embodiment);
FIG. 16 is a timing chart showing operations of a control signal generation unit and a waveform read address generation unit during (N + 3) channel processing (second embodiment);
[Explanation of symbols]
101 CPU
102, 202 RAM
103, 106 ROM
105 Musical sound generator
107 DA converter
201 Control signal generator
203 Waveform reading address generator
204 Waveform generator
301-303, 1001, 1002 Selector (SL)
304 to 313, 1003, 1004 Flip-flop (F / F)
314 Adder / Subtractor
315 Comparator
316 Address incrementer

Claims (4)

Waveform storage means for storing waveform data of musical sounds to be sounded;
Generation information storage means for storing address generation information for generating an address for reading waveform data from the waveform storage means and determination information for determining a master channel for each channel;
Reading means for reading out the address generation information and the discriminating information from the generation information storage means sequentially in time division for each channel;
Whether the address generation information read by the reading means corresponds to the master channel or the slave channel that designates the channel determined to be the master channel as the master based on the read discrimination information. Discriminating means for discriminating;
Address generation means for generating address information for reading waveform data from the waveform storage means based on the read address generation information;
Loop start storage means for storing data indicating whether or not the master channel loop starts;
Each time the discriminating unit discriminates that it corresponds to the master channel, it detects whether or not the loop is started based on the address generated by the address generating unit, and the loop start storage is performed based on the discrimination result. Loop detection means for updating the stored contents of the means;
In response to detection of a loop start by the loop detection means, the address generation means is controlled to change the address of the master channel to a loop start address, and the determination means corresponds to a slave channel. Each time it is determined, the stored contents of the loop start storage means are referred to.If the stored contents are data indicating the start of a loop, the address generation means is changed so as to change the address of the slave channel to a loop start address. Address control means to control;
Waveform reading means for reading waveform data from the waveform data storage means based on the address generated by the address generation means;
A musical sound generating device comprising: The discrimination information comprises master channel information representing a master channel,
2. The musical tone generating apparatus according to claim 1 , wherein the discriminating unit includes a comparing unit that compares a channel corresponding to the read address generation information with a channel represented by the master channel information . The address generation information includes an address value advanced every predetermined period, an address representing the start position of the waveform data of the musical sound to be generated, an address value representing the last position of the waveform data, and an address representing the start position at which reproduction is repeated. The musical tone generator according to claim 1, comprising: Waveform storage means for storing waveform data of musical sounds to be sounded;
Generation information storage means for storing address generation information for generating an address for reading waveform data from the waveform storage means and identification information for identifying whether the channel is a master channel, or
Reading means for reading out the address generation information and identification information from the generation information storage means sequentially in a time-sharing manner for each channel;
Based on the read identification information, a determination unit that determines whether the address generation information read by the reading unit corresponds to a master channel or a slave channel;
Address generation means for generating address information for reading waveform data from the waveform storage means based on the read address generation information;
Loop start storage means for storing data indicating whether or not the master channel loop starts;
Each time it is determined that the corresponding master channel by said discriminating means, said address based on the address generated by the scan generation means, and detects whether or not the loop start, the loop initiated based on the determination result Loop detection means for updating the storage contents of the storage means;
In response to detection of a loop start by the loop detection means, the address generation means is controlled to change the address of the master channel to a loop start address, and the determination means corresponds to a slave channel. Each time it is determined, the stored contents of the loop start storage means are referred to.If the stored contents are data indicating the start of a loop, the address generation means is changed so as to change the address of the slave channel to a loop start address. Address control means to control;
Waveform reading means for reading waveform data from the waveform data storage means based on the address generated by the address generation means;
A musical sound generating device comprising:

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