JP4141927B2 - Flexible matrix substrate and flexible display device - Google Patents

Description

  The present invention relates to a flexible active matrix substrate, a manufacturing method thereof, and a display device.

  In recent years, liquid crystal display devices (LCDs) have been widely used for notebook computers, thin televisions, and the like because of their thinness and low power consumption. Active matrix LCDs (AM-LCDs) in which active elements such as thin film transistors (TFTs) are formed in a matrix are rapidly spreading due to demands for higher image quality and increased information content.

  An apparatus using an active matrix substrate is applied not only to an LCD but also to a display such as an organic EL display (OLED) and a sensor such as an X-ray detector.

  The active matrix substrate that is widely used at present has a problem that it is easily broken and heavy because it uses a glass substrate.

  There is great expectation for flexible displays, especially in the mobile field, and various applications such as roll-up displays are possible. If an active matrix can be formed on a plastic substrate, not only flexibility, but also great advantages such as improved impact resistance, lighter weight, and thinner thickness are obtained.

  However, in order to form a TFT using amorphous silicon or polysilicon, which is widely used at present, a high-temperature process is required, and it is difficult to directly form a TFT on a plastic substrate having low heat resistance. Although the TFT can be formed at a lower process temperature, the electrical characteristics are inferior to those of a TFT formed on a glass substrate. Further, since the plastic substrate has poor dimensional stability, it is very difficult to form TFTs with the same definition as that on the glass substrate.

Therefore, a process of forming a TFT on a glass substrate as usual and transferring it to a plastic substrate can be considered. However, in the case of this method, in addition to the cost of forming the TFT, a cost related to transfer is newly generated. Therefore, a method of forming elements at high density and selectively transferring them later has been considered. (For example, Patent Document 1)
In order to perform the transfer selectively, a method of forming a layer called an adhesive layer on the transfer destination substrate is effective. In this method, the TFT is transferred only onto the island-shaped adhesive layer.

  Here, the lead-out wiring of the TFT is designed to have the shortest distance in order to connect the signal line and the scanning line arranged vertically and horizontally. That is, the lead-out wiring has two directions, a direction parallel to the signal line and a direction parallel to the scanning line.

This lead wiring inevitably has to get over the step at the edge of the adhesive layer.
JP 2001-7340 A

On the substrate by the transfer method, there are a portion where the adhesive layer is formed and a portion that is relatively difficult to bend, and a portion where the adhesive layer is not present and a portion that is relatively easy to bend. The end portion of the adhesive layer serves as a boundary between a portion that is difficult to bend and a portion that is easily bent. Further, the adhesive layer is relatively thick, and there is a step at the end of the adhesive layer.

  At the edge of the adhesive layer, there is a problem that a failure such as disconnection due to curvature concentration when the substrate is bent is likely to occur due to a difference in bending ease or a step. This defect is characterized in that the direction in which the substrate is bent and the direction in which the wiring is disconnected are the same.

  Therefore, when the substrate is bent, defects tend to occur in the lead-out wiring in a certain direction with respect to the bending.

  An object of the present invention is to prevent the occurrence of defects due to such disconnection and improve the bending resistance of a substrate.

The flexible matrix substrate of the present invention includes a substrate, a signal line and a scanning line formed on the matrix on the substrate, a pixel electrode surrounded by the signal line and the scanning line, and the signal line and the scanning line. An adhesive layer surrounded, a source electrode and a drain electrode formed via a channel layer, and a gate electrode disposed opposite to the channel layer via an insulating layer, and using a transfer method on the adhesive layer and anchored TFT, is connected to the scanning line lead lines for connecting the scanning line and the gate electrode, and the signal line lead lines for connecting the signal line and the source electrode, and the drain electrode and the pixel electrode and a pixel electrode lead wiring, in the adhesive layer end, said scanning line lead lines, the signal line lead wiring and the pixel electrode lead wires are parallel to each other And butterflies.

Of the edge of the adhesive layer, only the sides under the scanning line lead lines, signal line lead lines, and pixel electrode lead lines may be tapered.

  And a peripheral circuit adhesive layer provided on the substrate, and a peripheral circuit provided on the peripheral circuit adhesive layer and connected to the signal line and the scanning line via a peripheral circuit connection wiring. The circuit connection wiring may be parallel to the lead-out wiring at the edge of the peripheral circuit adhesive layer.

In addition, a flexible display device of the present invention includes the above-described flexible matrix substrate .

  Furthermore, a counter substrate having a counter electrode, and a liquid crystal sandwiched between the flexible matrix substrate and the counter substrate may be provided.

  Further, a limiting member may be provided on the substrate.

  The adhesive layer may be a resin.

  According to the present invention, by defining the direction of the wiring over the step at the edge of the adhesive layer in one direction, it is possible to improve resistance to bending perpendicular to the direction in which the wiring is drawn out.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  1 to 3 show a matrix substrate of this embodiment.

Although thin glass can be used for the substrate 101, a plastic film substrate or a resin substrate can also be used in order to give more flexibility. For example, polyethylene terephthalate (PET), polycarbonate (PC), polyethersulfone (PES), polyetherketone (PEEK), polyethylene naphthalate (PEN), polyimide (PI) and the like can be used.

On the substrate 101, signal lines 104 and scanning lines 105 are provided in parallel and vertically and horizontally. For the signal line 104 and the scanning line 105, a metal film such as Al, Mo, MoW, or MoTa can be used. For these wirings, a single-layer metal film or a laminated film can be used. An insulating film such as silicon nitride (SiN _x ), silicon oxide (SiO _x ), silicon oxynitride (SiO _x N _y ), or the like is formed between and on these wirings.

  Although not shown, the signal line 104 is connected to the signal line driver circuit, and the scanning line 105 is connected to the scanning line driver circuit.

  Each pixel electrode 103 is provided in a lattice formed by the signal lines 104 and the scanning lines 105, and each pixel electrode 103 corresponds to a pixel of the display device.

  In the vicinity of the intersection of one signal line 104 and one scanning line 105, each TFT 102 is disposed.

  The source electrode of the TFT 102 is connected to the signal line 104 via the source lead wiring 1021, the drain electrode is connected to the pixel electrode 103 via the drain lead wiring 1022, and the gate electrode is connected to the scanning line 105 via the gate lead wiring 1023. Has been. Here, each lead-out wiring is described as a member different from the pixel electrode 103 and the like. However, it is also possible to use each lead-out wiring as a part of each wiring and pixel electrode. It is also possible to form them simultaneously.

  An enlarged schematic view of one TFT 102 is shown in FIG. FIG. 3 shows a cross-sectional view along AA in FIG.

  As shown in FIG. 3, on the matrix substrate, signal lines 104 and scanning lines 105 are formed on the substrate 101 with an insulating layer interposed therebetween. Further, in the matrix substrate formed by the transfer method, the TFT 102 is bonded onto the adhesive layer 201. The thickness of the TFT 102 is, for example, about 1 μm.

  The adhesive layer 201 needs to be formed in an island shape in order to provide transfer selectivity. Here, the adhesive layer 201 shows an example of a rectangle. The thickness is about 0.3 to 3 μm. As a material of the adhesive layer 201, for example, a photosensitive acrylic resin such as HRC manufactured by JSR, an epoxy resin, a novolac resin, or the like can be used.

  The source lead-out wiring 1021, the drain lead-out wiring 1022, and the gate lead-out wiring 1023 are always formed beyond the end of the adhesive layer 201 in order to obtain electrical connection with the TFT 102 transferred from another substrate. For this reason, the lead-out wiring from the source terminal or the like of the TFT 102 covers the side surface of the TFT 102 and the side surface of the adhesive layer 201.

  These source lead-out wiring 1021, drain lead-out wiring 1022, and gate lead-out wiring 1023 are all formed so as to crawl on the side parallel to the signal line 104 of the adhesive layer 201, and as a result, scan at the end of the adhesive layer 201. It extends in a direction parallel to the line 105.

  Next, a method for manufacturing a matrix substrate will be described.

  As shown in FIG. 4, the TFT 102 is formed on the element formation substrate 401.

  As the element formation substrate 401, a glass substrate can be used.

  An etching stopper layer 402 is formed on the element formation substrate 401. The etching stopper layer 402 is formed with a single layer or a laminated structure of tantalum oxide, aluminum oxide, silicon nitride, or the like having hydrofluoric acid resistance, for example, with a thickness of about 300 nm.

On top of that, an undercoat 403 is formed of, for example, SiN _x , SiO _x , or SiO _x N _y .

  Thereafter, similarly to a normal TFT manufacturing method, a metal film made of a single layer or stacked layers of metals such as Al, Mo, MoW, and MoTa is formed to a thickness of about 300 nm using, for example, a sputtering method. This is patterned to form a gate electrode.

On top of this, a gate insulating film such as SiN _x , SiO _x , SiO _x N _{y is} formed to a thickness of about 300 nm using a plasma CVD method or the like.

Next, after forming an amorphous silicon layer with a thickness of about 50 nm, SiN _x is formed with a thickness of about 100 to 400 nm, and a channel protective layer is formed in self-alignment with the gate electrode by backside exposure.

  Next, a phosphorus-doped silicon film is formed by CVD, and the amorphous silicon layer in the source / drain region is used as an n-type semiconductor layer.

  On the source / drain region, a single layer or laminated film of a metal such as Mo or Al is formed to a thickness of about 300 nm and patterned to form a source electrode and a drain electrode.

  Further, a passivation film made of a silicon nitride film is formed by plasma CVD to a thickness of about 300 nm, and contact holes are formed in the source electrode, drain electrode, and gate electrode portions.

  Further, a protective layer 404 is formed of a photoresist, polyimide, or the like in order to protect the TFT during transfer. This protective layer may be removed after the transfer with a stripping solution or the like, or a contact hole may be opened to ensure connection.

  In this manner, the TFT 102 is formed on the element formation substrate 401. Here, the TFT 102 is more densely formed on the element formation substrate 401, so that the manufacturing efficiency is improved.

  In addition, the manufacturing method of TFT is not limited to the above method. A different structure such as a top gate type TFT may be used, or a TFT using polycrystalline silicon may be used.

  Next, as shown in FIG. 5, the TFT 102 on the element formation substrate 401 is pressure-bonded to the intermediate transfer substrate 501.

  As the intermediate transfer substrate 501, for example, a glass substrate is used.

A temporary adhesion layer 502 is formed on the intermediate transfer substrate 501. The temporary attachment layer 502 is an adhesive layer whose adhesive strength is reduced by heating or UV irradiation. For example, Riva Alpha (registered trademark) manufactured by Nitto Denko Co., Ltd., which foams when heated and the adhesive strength decreases, and Intellimer (registered trademark) of Nita Co., Ltd., whose adhesive strength changes greatly with temperature, can be used. It is.

  Thereafter, the element formation substrate 401 is removed from the back side of the element formation substrate 401 with an etchant containing hydrofluoric acid. At this time, the etching stopper layer 402 formed under the TFT 102 can prevent the etchant from being penetrated into the TFT 102.

  Note that as a method for removing the element formation substrate 401, a method by mechanical polishing can be used in addition to a method using a hydrofluoric acid etchant. Further, instead of the etching stopper layer 402, a layer that causes laser ablation such as amorphous silicon may be formed, and a method of causing peeling by laser irradiation from the back surface may be used.

Further, the etching stopper layer 402 is removed with a chemical solution. (Fig. 6)
On the other hand, signal lines and scanning lines are formed on the substrate 101. The signal lines 104 and the scanning lines 105 are formed by forming a metal film of Al, Mo, MoW, MoTa, or the like by about 300 nm by sputtering or the like, and then patterning. For these wirings, a single-layer metal film or a laminated film can be used. Further, an insulating film such as SiN _x , SiO _x , or SiO _x N _y is formed between and on these wirings. Then, the adhesive layer 201 is formed by photolithography, printing, or the like. Here, the adhesive layer 201 is formed at a position where the TFT 102 is to be provided, has an island shape large enough to adhere the TFT 102, and is about 30 to 100 μm. Typically, it is rectangular, but other polygons may be used in combination with the shape of the pixel electrode or the like. Further, the size of the adhesive layer 201 needs to have a sufficient margin in consideration of the transfer accuracy in consideration of an error due to the transfer accuracy of the TFT 102. In addition, in order to connect the wiring, it is desirable that the end portion of the adhesive layer 201 has a certain degree of taper. If the taper angle is set to about 60 degrees, for example, step breakage is suppressed, and the area of the taper portion does not need to be too large.

  The intermediate transfer substrate 501 faces the substrate 101, and the TFT 102 to be transferred and the adhesive layer 201 are aligned. As shown in FIG. 7, the TFT 102 to be transferred and the adhesive layer 201 are fixed by applying pressure and heating.

In this state, the intermediate transfer substrate 501 is heated or UV irradiation is performed from the back side of the intermediate transfer substrate 501 to reduce the adhesive strength of the temporary adhesion layer 502, and the intermediate transfer substrate 501 and the TFT 102 are peeled off. . (Fig. 8)
In this manner, the TFT 102 on the element formation substrate 401 can be selectively transferred onto the substrate 101.

  After transferring and fixing the TFT 102 on the substrate 101, contact holes are formed in the signal lines and the scanning lines, and the TFTs are connected.

  The order of signal line formation, scanning line formation, adhesion layer formation and transfer process can be arbitrarily changed. The connection may be individually formed with a metal film such as Al, may be formed simultaneously with the signal line or the scanning line, or may be formed simultaneously with the pixel electrode using a transparent conductive material such as ITO. The width of each lead-out wiring is about 10 μm.

  Here, as shown in FIG. 1, the source lead-out wiring 1021, the drain lead-out wiring 1022, and the gate lead-out wiring 1023 are arranged in parallel at the end portion of the adhesive layer 201, and are all substantially parallel to the scanning line 105. .

With this arrangement, distortion is concentrated when the substrate 101 is bent in the direction in which the signal line 104 bends while the scanning line 105 is straight (when bent in the vertical direction in FIG. 1). At the end of the adhesive layer 201 that is easy to perform, the lead-out wiring remains linear, and disconnection of the lead-out wiring does not occur. That is, when wiring as shown in FIG. 1 is performed, resistance to bending in the direction of the signal line 104 is improved.

  By the way, in the case of the wiring structure as shown in FIG. 1, there is no wiring on the side parallel to the scanning line 105 of the adhesive layer 201. Therefore, it is not necessary to provide a taper for the side of the adhesive layer 201 parallel to the scanning line 105, and the size of the adhesive layer 201 can be reduced. Furthermore, since there is no wiring on this side, there is no need to allow for a wiring margin. As a result, an effect such as an increase in the aperture ratio of the display due to the reduction of the adhesive layer area can be expected.

  Up to this point, an example in which the lead wires are parallel to each other at the end of the adhesive layer 201 and arranged in parallel to the scanning line 105 has been described with reference to FIGS. As described above, the signal line 104 can be arranged in parallel.

  9, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. That is, the source lead wiring 1021, the drain lead wiring 1022, and the gate lead wiring 1023 are parallel to each other and almost parallel to the signal line 104 at the end of the adhesive layer 201.

  At this time, when the substrate 101 is bent in the direction in which the scanning line 104 bends while the signal line 104 is straight (when it is bent in the lateral direction in FIG. 9), distortion tends to concentrate. At the end of the adhesive layer 201, the lead-out wiring remains straight, and disconnection of the lead-out wiring does not occur. That is, when wiring as shown in FIG. 9 is performed, resistance to bending in the scanning line 104 direction is improved.

  Note that the example in which the source lead-out wiring 1021 and the gate lead-out wiring 1023 are juxtaposed and the drain lead-out wiring 1022 is arranged on the opposite side has been described, but when all these three lead-out wirings are juxtaposed as shown in FIG. In addition, various patterns can be employed such as when the source lead-out wiring 1021 and the gate lead-out wiring 1023 are juxtaposed.

  In addition, since it is only necessary that the lead-out wiring is arranged in the same direction at the end portion of the adhesive layer 201, it is not necessarily arranged in parallel with the signal line 104 or the scanning line 105. For example, unlike the direction of the signal line 104, the lead wiring direction does not mean that the pattern design of the 45 degree direction cannot be performed.

  At this time, resistance to bending in the direction perpendicular to the direction of the lead-out wiring at the end of the adhesive layer 201 is improved. This is because the signal line 104 and the scanning line 105 are formed relatively flat, whereas a large step portion such as an end portion of the adhesive layer 201 is weak against bending.

  As described above, since the source lead-out wiring 1021, the drain lead-out wiring 1022, and the gate lead-out wiring 1023 are arranged substantially parallel to each other at the end of the adhesive layer 201, resistance to bending in the vertical direction is improved.

  As another shape of the adhesive layer 201, as shown in FIG. Again, as shown in FIG. 12, the lead-out lines may be arranged in the same direction.

Further, the width of the wiring does not have to be constant, and it is also possible to change the width of the wiring at a portion that covers the end portion of the adhesive layer as shown in FIG.

  Further, the position of the TFT 102 can be changed.

  For example, as shown in FIG. 14, the positions of the TFTs 102 may be alternately changed between adjacent pixels so as to be disposed on both sides so as to sandwich one scanning line 105.

  Here too, at the end of the adhesive layer 201, the source lead-out wiring 1021, the drain lead-out wiring 1022, and the gate lead-out wiring 1023 are substantially parallel to each other. For this reason, it is possible to prevent the occurrence of defects with respect to bending in a direction perpendicular to the direction of these lead-out wirings.

  Note that the directions of the lead-out lines at the end of the adhesive layer 201 do not have to be completely the same. In other words, even if there are slight exceptions due to the convenience of the pattern, it goes without saying that the effect can be obtained if the lead-out wiring directions are almost the same.

  The matrix substrate of this embodiment will be described with reference to FIG.

  Here, on the matrix substrate 101, there are a pixel region 701 in which TFTs are formed in a matrix and a peripheral region 702 for forming a drive circuit and the like.

  In the pixel region 701, the signal line 104 and the scanning line 105 are provided in parallel and vertically and horizontally. A pixel electrode is provided in a lattice formed by the signal line 104 and the scanning line 105.

  In each lattice, there is a TFT 102 bonded to the substrate 101 by an adhesive layer 201. The source electrode of the TFT 102 is connected to the signal line 104 via the source lead wiring 1021, the drain electrode is connected to the pixel electrode 103 via the drain lead wiring 1022, and the gate electrode is connected to the scanning line 105 via the gate lead wiring 1023. Has been. These source lead wiring 1021, drain lead wiring 1022, and gate lead wiring 1023 extend in an almost parallel direction to the scanning line 105 at the end of the adhesive layer 201.

  On the other hand, a peripheral circuit 704 such as a signal line driver circuit and a scanning line driver circuit is formed in the peripheral region 702 and connected to the signal line 104 and the scanning line 105 in the pixel region 701.

  The peripheral circuit is also bonded to the substrate 101 by the peripheral adhesive layer 703, and the peripheral circuit connection wiring 704 for connection covers the end of the peripheral adhesive layer 703. The peripheral circuit connection wiring 704 is substantially parallel to the scanning line 105 in the pixel region 701 at the end of the adhesive layer 703.

  In other words, the direction of the adhesive layer side surfaces of the source lead wiring 1021, drain lead wiring 1022, gate lead wiring 1023, and peripheral circuit connection wiring 704 in the pixel region 701 coincides and is substantially parallel to the scanning line 105. . For this reason, not only in the pixel but also in the peripheral portion, resistance to bending parallel to the signal line is increased.

  The manufacturing method of this embodiment is almost the same as the previous embodiment.

A display can be formed using the flexible matrix substrate 101 described in the above embodiment.

  Here, the case where a liquid crystal display is comprised is demonstrated.

  As shown in FIG. 18, a polyimide film 13 is formed on a matrix substrate 101, and the surface thereof is subjected to liquid crystal alignment treatment. Here, TFTs and the like are omitted.

  Next, a flexible counter substrate 12 is used, and a counter electrode such as ITO, a black matrix layer, and a color filter are formed on the surface thereof. Furthermore, a polyimide film 14 subjected to an alignment process is formed thereon.

  The substrate 101 and the counter substrate 12 are bonded to each other with a spacer 16 having a size of about 2 to 6 μm, and the periphery of the display area is fixed with a sealant 17.

  Next, liquid crystal 15 is injected between the substrate 101 and the counter substrate 12.

  Then, a scanning line, a signal line, and a counter electrode are connected to a driving circuit, and polarizing plates are attached to both sides to complete a liquid crystal display device.

  Since the lead-out wiring direction of the matrix substrate 101 is only a single direction at the end of the adhesive layer, resistance to bending in a direction perpendicular to the lead-out wiring direction is improved. This is because there is no wiring in the stepped portion of the adhesive layer that becomes a major defect when bent and is parallel to the direction of the bending.

  That is, the display can be bent in a direction perpendicular to the direction of the lead-out wiring at the end of the adhesive layer. For example, if the direction of the lead-out wiring is the vertical direction of the screen, the display can be bent in the horizontal direction.

  Here, the liquid crystal display device has been described as an example, but a display device using a matrix substrate is not limited to this, and for example, an electrophoretic type in which colored particles are dispersed in a cell and can be similarly produced. The same applies to a display or the like.

  The configuration of this example is schematically shown in FIG.

  This embodiment is also a case where the pixel region 701 and the peripheral region 702 are provided on the substrate 101 as in the second embodiment. However, in this embodiment, a limiting member 705 is provided in the peripheral region 702. The limiting member 705 limits the direction in which the substrate 101 bends.

  The arrangement of the lead lines in the pixel region 701 is the same as that in FIG. That is, at the end of the adhesive layer 201 below the TFT 102, the source lead-out wiring 1021, the drain lead-out wiring 1022, and the gate lead-out wiring 1023 are substantially parallel to each other, and these are also in parallel with the signal line 104.

  The limiting member 705 provided in the peripheral region 702 is made of a material that is less flexible than the substrate 101, so that the substrate 101 does not bend in the signal line 104 direction and is relatively free in the scanning line 105 direction. It becomes possible to make a display that bends in a straight line. That is, the display using the substrate 101 bends well in the direction of higher resistance, and hardly bends in the direction of low resistance.

  The limiting member 705 can incorporate a peripheral drive circuit, a power source, and the like.

  Further, the display can be rolled up and stored around the limiting member 705.

  An organic EL display can be configured using the flexible matrix substrate described in the previous embodiment.

  FIG. 20 is a schematic plan view of the organic EL display, and FIG. 21 is a partial cross-sectional view in the vicinity of the light emitting layer and the TFT in FIG. 15 and 16 are two examples of the plan view according to FIG.

  A signal line 104 and a power supply line 106 are formed in parallel, and a scanning line 105 is formed perpendicular thereto. The power supply line 106 is connected to a power supply circuit outside the pixel region. Pixels surrounded by the signal lines 104, the power supply lines 106, and the two adjacent scanning lines 105 are formed in a matrix.

  A current is supplied from the pixel electrode 103 connected to the pixel driving circuit 301 to the light emitting layer 302 of the organic EL formed on the pixel electrode to emit light.

  The pixel drive circuit 301 includes two transistors, a drive TFT 306 and a current control TFT 307. The drain electrode of the driving TFT 306 is connected to the gate electrode of the current control TFT 307. The source electrode of the driving TFT 306 is connected to the signal line 104 via the source lead wiring 1021, and the gate electrode of the driving TFT 306 is connected to the scanning line 105 via the gate lead wiring 1023. Further, the source electrode of the current control TFT 307 is connected to the power supply line 106 via the power supply lead line 1025 and to the pixel electrode 103 via the drain lead line 1024.

  Each lead-out wiring from the pixel drive circuit 301 is parallel to the signal line 104 (FIG. 15) or parallel to the scanning line 105 (FIG. 16) at the end of the adhesive layer 102.

  By configuring such an organic EL display, it is possible to form a display with improved resistance to bending parallel to the scanning line 105.

  As shown in FIG. 20, the light emitting portion of the organic EL display is composed of a pixel electrode 103 formed on a substrate 101, a light emitting layer 302 thereon, and an electrode 304 thereon. Usually, the electrodes 304 are connected in common so that a constant potential can be supplied.

  In addition, the pixel driving circuit 301 is fixed on the adhesive layer 201.

  An outline of the manufacturing method of this display will be described.

  First, in the same manner as in Example 1, a flexible active matrix substrate is formed. At this time, the power supply line 106 can be formed using the same material as the signal line 104 at the same time. In addition, two TFTs may be formed at the same time and transferred onto one adhesive layer 201 at the same time.

  A side wall is formed so as to surround the pixel electrode 103. An organic EL light emitting layer 302 is formed on the pixel electrode 103 surrounded by the side wall. At this time, a low molecular material may be deposited, or a high molecular material may be formed by printing such as an ink jet method.

  And the electrode 304 is formed on it using transparent electrodes, such as ITO.

  Furthermore, an organic EL display can be formed by forming a transparent protective layer 305 such as an acrylic resin thereon.

  In the display described in this embodiment, since the direction of the lead-out wiring from the TFT is parallel at the end of the adhesive layer, the resistance to bending in the direction perpendicular to the display is improved.

Wiring pattern diagram explaining the embodiment Enlarged view of TFT to explain the embodiment Cross-sectional view of TFT to explain the embodiment Manufacturing process diagram explaining an example Manufacturing process diagram explaining an example Manufacturing process diagram explaining an example Manufacturing process diagram explaining an example Manufacturing process diagram explaining an example Wiring pattern diagram explaining the embodiment TFT partial enlarged view illustrating the embodiment Example of adhesive layer illustrating the embodiment TFT partial enlarged view illustrating the embodiment TFT partial enlarged view illustrating the embodiment Wiring pattern diagram explaining the embodiment TFT partial enlarged view illustrating the embodiment TFT partial enlarged view illustrating the embodiment Layout on the substrate explaining the embodiment Schematic cross-sectional view of a liquid crystal display device illustrating an embodiment Layout on the substrate explaining the embodiment Plane schematic diagram illustrating the embodiment Partial sectional view in FIG.

Explanation of symbols

101 Substrate 102 TFT
103 pixel electrode 104 signal line 105 scanning line 106 power supply line 201 adhesive layer 301 pixel drive circuit 302 light emitting layer 1021 source lead wiring 1022 drain lead wiring 1023 gate lead wiring 1024 power lead wiring

Claims (7)

A substrate,
Signal lines and scanning lines formed on a matrix on the substrate;
A pixel electrode surrounded by the signal line and the scanning line;
An adhesive layer surrounded by the signal lines and the scanning lines;
And and a channel layer of the gate electrode are oppositely arranged with an insulating layer and formed a source electrode and a drain electrode on the channel layer through, is fixed by using a transfer method on the adhesive layer TFT,
A scanning line lead-out wiring connecting the gate electrode and the scanning line;
A signal line lead-out wiring connecting the source electrode and the signal line;
A pixel electrode lead wiring connected to the drain electrode and the pixel electrode;
The flexible matrix substrate , wherein the scanning line lead line, the signal line lead line, and the pixel electrode lead line are parallel to each other at the edge of the adhesive layer . 2. The flexible matrix substrate according to claim 1, wherein only a side below the scanning line lead- out wiring, the signal line lead- out wiring, and the pixel electrode lead- out wiring among the end portions of the adhesive layer is tapered. Further, a peripheral circuit adhesive layer provided on the substrate,
A peripheral circuit provided on the peripheral circuit adhesive layer and connected to the signal line and the scanning line via a peripheral circuit connection wiring ;
2. The flexible matrix substrate according to claim 1, wherein the peripheral circuit connection wiring is parallel to the scanning line lead-out wiring at an end portion of the peripheral circuit adhesive layer.   A flexible display device comprising the flexible matrix substrate according to claim 1. The flexible display device according to claim 4, further comprising: a counter substrate having a counter electrode; and a liquid crystal sandwiched between the flexible matrix substrate and the counter substrate.   The flexible matrix substrate according to claim 1, further comprising a limiting member on the substrate.   2. The flexible matrix substrate according to claim 1, wherein the adhesive layer is made of a resin.

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