JP4125743B2 - Ferroelectric memory device - Google Patents

Description

  The present invention relates to a ferroelectric memory device.

  In recent years, a ferroelectric memory device has been devised that realizes non-volatility of stored data by using a ferroelectric material for a capacitor of a memory cell. A ferroelectric capacitor has a hysteresis characteristic, and even when the electric field is zero, residual polarizations having different polarities depending on the history remain. A non-volatile memory device is realized by expressing stored data by remanent polarization of a ferroelectric capacitor.

  One US patent specification discloses two types of ferroelectric memory devices (see, for example, Patent Document 1).

  In the first type, a memory cell is composed of one transistor and one capacitor (1T1C) per bit. For example, every 256 ferroelectric capacitors (normal cells) for main body memory cells. One ferroelectric capacitor for reference memory cells is provided.

  In the second type, a ferroelectric capacitor for a reference memory cell is not provided, and a memory cell is composed of two transistors and two capacitors (2T2C) per bit, and a pair of complementary data Is stored in a pair of ferroelectric capacitors for main body memory cells.

  In order to increase the memory capacity, the 1T1C type is advantageous. At this time, for the low voltage operation and long life operation, the ferroelectric capacitor for the reference cell is designed with respect to the ferroelectric capacitor for the main body memory cell. It becomes important.

As ferroelectric materials constituting the capacitor, KNO ₃ , PbLa ₂ O ₃ —ZrO ₂ —TiO ₂ , PbTiO ₃ —PbZrO ₃ , and the like are known. According to PCT International Publication No. WO 93/12542, a ferroelectric material having extremely small fatigue compared to PbTiO ₃ —PbZrO ₃ suitable for a ferroelectric memory device is also known.

  The configuration of a conventional 1T1C type ferroelectric memory device will be briefly described below.

  FIG. 7 is a memory cell configuration diagram, FIG. 8 is a sense amplifier circuit diagram, and FIG. 9 is an operation timing diagram.

  In FIG. 7, C00 to C37 are ferroelectric capacitors for main body memory cells, and CD00 to CD31 are ferroelectric capacitors for reference memory cells. CPD is a cell plate driver, and REW0 to REW1 are reference memory cell rewrite signal lines. SA0 to SA3 are sense amplifiers, and CP is a cell plate signal line. WL0 to WL7 are word lines, RWL0 to RWL1 are reference word lines, and BL0 to BL3 and / BL0 to / BL3 are bit lines. In FIGS. 8 and 9, BP is a bit line precharge signal, and / SAP and SAN are sense amplifier control signals. VSS is a ground voltage, and VDD is a power supply voltage.

  As a memory cell configuration, as shown in the figure, for example, bit lines BL0 and / BL0 are connected to a sense amplifier SA0. The main memory cell ferroelectric capacitor C00 is connected to the bit line BL0 via an N-channel MOS transistor Tr1 having the word line WL0 as a gate. The bit line / BL0 is connected to a ferroelectric capacitor CD00 for reference memory cell via an N-channel MOS transistor Tr2 having the reference word line RWL0 as a gate. The ferroelectric capacitors C00 and CD00 are connected to a cell plate signal line CP that is driven by a cell plate driver CPD.

  The bit lines / BL0 and / BL1 are connected via an N-channel MOS transistor Tr3 whose gate is the reference word line RWL0. The bit line BL0 and the reference memory cell ferroelectric capacitor CD00 are connected via an N-channel MOS transistor Tr5 whose gate is the reference memory cell rewrite signal line REW0.

  As shown in FIG. 8, the sense amplifier SA0 is controlled by the sense amplifier control signals / SAP and SAN, and has a circuit configuration in which the precharge of the bit lines BL0 and / BL0 is controlled by the bit line precharge signal BP. is there.

  This conventional 1T1C ferroelectric memory device uses two ferroelectric capacitors of approximately the same size as the main body memory cell ferroelectric capacitor, and each sets one “H” (high) data. In this method, one piece of “L” (low) data is read and the two data are averaged (see, for example, Patent Document 2).

  The operation of the conventional 1T1C ferroelectric memory device will be described with reference to FIG. 9, focusing on the case where the word line WLO is selected.

  First, when the bit line precharge signal BP is H, the bit lines BL0 and / BL0 are precharged to the logic voltage “L”. Similarly, the bit lines BL1 and / BL1 are precharged to the logic voltage “L”.

  Next, when the bit line precharge signal BP is set to the logic voltage “L”, the bit lines BL0 and / BL0 and the bit lines BL1 and / BL1 are in a floating state.

  Next, the word line WL0 and the reference word line RWL0 are set to the logic voltage “H”, and then the cell plate signal line CP is set to the logic voltage “H”. Here, the potential level of the logic voltage “H” of the word line WL0 is a voltage boosted to the power supply voltage VDD or higher. Since the reference word line RWL0 is set to the logic voltage “H”, the N-channel MOS transistors Tr2 to Tr4 are turned on. In the present specification, as described above, for example, when the word line WL0 is expressed as the logic voltage “H”, it means that the potential of the word line WL0 is set as the logic voltage “H”. Is.

  At this time, an electric field is applied to both electrodes of the ferroelectric capacitors C00, CD00, C10, and CD10, and the respective potentials are determined by the capacitance ratio of the ferroelectric capacitor and the bit line capacitance. These potentials are read from the bit lines BL0, / BL0, BL1, and / BL1, respectively.

  At this time, the data read from the ferroelectric capacitors CD00 and CD10 for the reference memory cell are electrically connected to the bit lines / BL0 and / BL1 because the N-channel MOS transistors Tr2 to Tr4 are in the ON state. Therefore, both data are averaged data (potential). Here, "H" (high) data is recorded in the ferroelectric capacitors CD00 and CD01 for reference memory cells, and "L" (low) data is recorded in the ferroelectric capacitors CD10 and CD11 for reference memory cells. ing.

  Next, the reference word line RWL0 is set to the logic voltage “L” and the N-channel MOS transistors Tr2 to Tr4 are turned off to electrically disconnect the bit line / BL0 and the bit line / BL1.

  Thereafter, the sense amplifier control signal / SAP is set to the logic voltage “L” and the SAN logic voltage “H”, and the sense amplifier is operated.

  As a result, the potential read to the bit line is amplified to the power supply voltage VDD and the ground voltage VSS.

  Next, the reference memory cell rewrite signal line REW0 is set to the logic voltage “H”, and the reference memory cell ferroelectric capacitors CD00 and CD10 are set to “H” (high) and “L” for the next read operation. (Low) potential can be written.

  Next, the cell plate signal line CP is set to the logic voltage “L” as a rewrite operation. Thereafter, the bit line precharge signal BP is set to the logic voltage “H”, the bit lines BL0 and / BL0 are precharged to the logic voltage “L”, and the word line WL0 and the reference word line RWL0 are set to the logic voltage “L”. The initial state is assumed.

As described above, in the conventional 1T1C type ferroelectric memory device, when the word line WLO is selected, the reference potential used when reading the potentials of the bit line BL0 and the bit line BL1 is the strong potential for the reference memory cell. It is an average value of the dielectric capacitors CD00 and CD10. The average value is read from the bit lines / BL0 and / BL1. The reference potential used when reading the potentials of the bit lines BL2 and BL3 is an average value of the ferroelectric capacitors CD20 and CD30 for reference memory cells. The average value is read from the bit lines / BL 2 and / BL 3 .

  When the word line WL1 is selected, the role of the bit line pair is opposite to that described above, and the ferroelectric capacitor for the reference memory cell is also different.

That is, the reference potential used when reading the potentials of the bit line / BL0 and the bit line / BL1 is an average value of the ferroelectric capacitors CD01 and CD11 for reference memory cells. The average value is read from the bit lines BL0 and BL1. The reference potential used when reading the potentials of the bit lines / BL2 and / BL3 is an average value of the ferroelectric capacitors CD21 and CD31 for reference memory cells. Its average value is read out from the bit lines BL 2 and BL 3.

Therefore, in the configuration shown in FIG. 7, there are four types of reference potentials for the eight word lines WL0 to WL7.
US Pat. No. 4,873,664 JP-A-7-262768

  However, the reference memory cell system of the conventional 1T1C type ferroelectric memory device has the following problems.

  That is, in the conventional case, one ferroelectric capacitor for reference (for example, a ferroelectric capacitor CD00 for reference memory cells) in which data of “H” (high) and “L” (low) is written. And CD10) are electrically connected, the potentials of both are averaged, and this is used as a reference potential for data reading. Therefore, variations in the reference potentials are caused by variations in the ferroelectric capacitors for the reference memory cells. Accordingly, there is a case where an ideal reference potential that should originally be the same value cannot be obtained, which causes a decrease in yield as a ferroelectric memory device.

  In particular, variations in the ferroelectric capacitors for the reference memory cell are greatly influenced by the layout arrangement position, and the arrangement positions of the ferroelectric capacitor for the reference memory cell and the ferroelectric capacitor for the main body memory cell are If they are far from each other, there is a problem that an ideal reference potential may not be obtained.

  Further, in the reference memory cell system of the conventional 1T1C type ferroelectric memory device, an N-channel MOS transistor as a control signal and a control switch element and a ferroelectric capacitor for the reference memory cell are provided in one bit. There is a problem that it is necessary for each line and occupies a large area in layout.

  An object of the present invention is to provide a ferroelectric memory device in which the variation of the reference potential can be further reduced as compared with the conventional case in consideration of the above-described conventional problems.

A first aspect of the present invention is a ferroelectric memory device for storing nonvolatile data in a ferroelectric capacitor for a main body memory cell,
Three or more first reference memory cell ferroelectric capacitors respectively connected to three or more first bit lines via a first transistor whose first reference word line is a gate. Prepared,
The three or more first reference memory cell ferroelectric capacitor, said first reference memory cell having the data of the first strong for reference memory cell ferroelectric capacitor and a high level with the low level data Including at least one ferroelectric capacitor and the same number
Equalizing circuit means for averaging potentials read to the three or more first bit lines;
Reading means for reading data stored in the ferroelectric capacitor for main body memory cells, using the averaged potential as a reference potential;
A ferroelectric memory device characterized by comprising:

According to a second aspect of the present invention, word lines for selecting the ferroelectric capacitors for main body memory cells and the first bit lines are arranged in a matrix, and the ferroelectric capacitors for main body memory cells are used. A memory cell array is configured,
The ferroelectric memory device according to the first aspect of the present invention is characterized in that the equalize circuit means is arranged in the vicinity of the center in the length direction of the first bit line.

According to a third aspect of the present invention, the word lines for selecting the ferroelectric capacitors for main body memory cells and the first bit lines are arranged in a matrix, and the ferroelectric capacitors for main body memory cells are used. A memory cell array is configured,
The ferroelectric memory device according to the first aspect of the present invention is characterized in that the ferroelectric capacitor for the first reference memory cell is disposed in the vicinity of the center in the length direction of the first bit line. is there.

According to a fourth aspect of the present invention, word lines for selecting the ferroelectric capacitors for main body memory cells and the first bit lines are arranged in a matrix, and the ferroelectric capacitors for main body memory cells are used. A memory cell array is configured,
The ferroelectric capacitor for the first reference memory cell according to the first aspect of the present invention, wherein the ferroelectric capacitors for the first reference memory cell are distributed at a plurality of positions in a length direction of the first bit line. Body memory device.

According to a fifth aspect of the present invention, word lines for selecting the ferroelectric capacitors for main body memory cells and the first bit lines are arranged in a matrix, and the ferroelectric capacitors for main body memory cells are used. A memory cell array is configured,
Cell plate driving means for applying a predetermined potential to the ferroelectric capacitor for the main body memory cell;
In the ferroelectric memory device according to the first aspect of the present invention, the cell plate driving means is disposed near the center in the length direction of the first bit line.

According to a sixth aspect of the present invention, word lines for selecting the ferroelectric capacitors for main body memory cells and the first bit lines are arranged in a matrix, and the ferroelectric capacitors for main body memory cells are used. A memory cell array is configured,
Cell plate driving means for applying a predetermined potential to the ferroelectric capacitor for the main body memory cell;
The ferroelectric memory device according to the first aspect of the present invention, wherein the cell plate driving means is disposed substantially near the center of the array of the three or more first bit lines. .

  According to a seventh aspect of the present invention, in any one of the first to sixth aspects of the present invention, the three or more first bit lines are connected to different sense amplifiers. This is a ferroelectric memory device.

The eighth aspect of the present invention provides three or more second bit lines connected to three or more second bit lines via a second transistor whose second reference word line is a gate. A ferroelectric capacitor for a reference memory cell ;
The three or more second reference memory cell ferroelectric capacitor, said second reference memory cell having the data of the second strong for reference memory cell ferroelectric capacitor and a high level with the low level data Including at least one ferroelectric capacitor and the same number
Second equalize circuit means for averaging potentials read to the three or more second bit lines;
Readout means for reading out data stored in the ferroelectric capacitor for the main body memory cell by using the averaged potential as a reference potential,
The three or more second bit lines are respectively connected to the different sense amplifiers, and the first bit line and the second bit line form a bit line pair. The ferroelectric memory device according to the seventh aspect of the present invention.

  The ninth aspect of the present invention is the ferroelectric memory device according to the first aspect of the present invention, wherein the first equalizing circuit means is connected to the first reference word line. .

  As is apparent from the above description, the present invention has an advantage that it is possible to provide a ferroelectric memory device in which the variation in the reference potential can be further reduced as compared with the prior art.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a configuration diagram of a memory cell in a ferroelectric memory device according to a first embodiment of the present invention. The configuration of the present embodiment will be described with reference to FIG.

  The sense amplifier circuit and the operation timing diagram are the same as those in FIGS. 8 and 9 of the conventional example.

  As shown in FIG. 1, C00 to C37 are ferroelectric capacitors for main body memory cells, and CD00 to CD31 are ferroelectric capacitors for reference memory cells. CPD is a cell plate driver, and REW0 to REW1 are reference memory cell rewrite signal lines. The reference memory cell ferroelectric capacitors CD00 and CD20 have “H” (high) data, and the reference memory cell ferroelectric capacitors CD10 and CD30 have “L” (low) data. Is recorded. The reference memory cell ferroelectric capacitors CD01 and CD21 have "H" (high) data, and the reference memory cell ferroelectric capacitors CD11 and CD31 have "L" (low) data. Is recorded.

  EQ0 to EQ1 are reference potential signal lines, SA0 to SA3 are sense amplifiers, and CP is a cell plate signal line. WL0 to WL7 are word lines, RWL0 to RWL1 are reference word lines, and BL0 to BL3 and / BL0 to / BL3 are bit lines. BP is a bit line precharge signal, and / SAP and SAN are sense amplifier control signals. VSS is a ground voltage, and VDD is a power supply voltage. The reference potential signal lines EQ0 to EQ1 are signal lines for generating a reference potential when the reference word lines RWL0 to RWL1 are selected.

  As shown in the figure, the word lines for selecting the ferroelectric capacitors for the main body memory cells and the bit lines used for reading the potential are arranged in a matrix. A memory cell array, which will be described later, is constituted by a ferroelectric capacitor for main body memory cells.

  In the memory cell array configuration, bit lines BL0 to BL3 and / BL0 to / BL3 are connected to sense amplifiers SA0 to SA3 as shown in FIG. The main memory cell ferroelectric capacitors C00, C10, C20, and C30 are connected to the bit lines BL0 to BL3 via N-channel MOS transistors having the word line WL0 as a gate. The bit lines / BL0, / BL1, / BL2, / BL3 are connected to the ferroelectric capacitors for reference memory cells via N-channel MOS transistors Tr2, Tr4, Tr7, Tr9 having the reference word line RWL0 as a gate. CD00, CD10, CD20, and CD30 are connected to each other.

  The equalize circuit is a circuit composed of N-channel MOS transistors Tr0, Tr3, Tr6, Tr8 and the like. That is, the equalizing circuit reads the various data stored in the ferroelectric capacitors for the reference memory cells CD00, CD10, CD20, CD30 as various potentials from the bit lines / BL0, / BL1, / BL2, / BL3. It is a circuit that averages these potentials. The potential averaged by the equalize circuit is a reference potential used for amplifying data read from the ferroelectric capacitor for main body memory cells by the sense amplifier.

  The ferroelectric capacitors C00 to C37 and CD00 to CD31 are connected to a cell plate signal line CP that is driven by a cell plate driver CPD.

  The bit line BL0 and the reference memory cell ferroelectric capacitor CD00 are connected via an N-channel MOS transistor Tr5 whose gate is the reference memory cell rewrite signal line REW0. The other bit lines / BL0, BL2, / BL2 are also connected to the reference memory cell ferroelectric capacitors CD10, CD20, CD30 through the respective N-channel MOS transistors in the same manner as the bit line BL0. .

  The sense amplifier SA0 is controlled by the sense amplifier control signals / SAP and SAN, and has a circuit configuration in which the precharge of the bit lines BL0 to BL3 and / BL0 to / BL3 is controlled by the bit line precharge signal BP. The reading means of the present invention corresponds to the sense amplifier SA0 and the like.

  In the first embodiment, four ferroelectric capacitors having approximately the same size as the main body memory cell ferroelectric capacitor are used, and data “H” is obtained from two of them, and the remaining two capacitors. In this method, “L” data is read from each of the data, and these data are averaged.

  The operation of this embodiment will be described below.

  The operation timing of this embodiment is the same as that of the conventional example shown in FIG.

  Here, main differences from the conventional example will be described. That is, in the conventional case, as described above, one H data and one L data are used, and the reference potential is obtained by averaging them. On the other hand, the present embodiment is different from the conventional case in that a plurality of H data and a plurality of L data are used and averaged to obtain a reference potential.

  Thus, in the ferroelectric memory device of this embodiment, when the word line WLO is selected, the reference potential used when reading the potentials of the bit lines BL0, BL1, BL2, and BL3 is for the reference memory cell. The average value of the ferroelectric capacitors CD00, CD10, CD20, and CD30. The average values are read from the bit lines / BL0, / BL1, / BL2, / BL3, respectively.

  When the word line WL1 is selected, the role of the bit line pair is opposite to that described above, and the ferroelectric capacitor for the reference memory cell is also different.

  That is, the reference potential used when reading the potentials of the bit lines / BL0, / BL1, / BL2, / BL3 is an average value of the ferroelectric capacitors CD01, CD11CD21 and CD31 for reference memory cells. The average values are read from the bit lines BL0, BL1, BL2, and BL3, respectively.

  Therefore, in the configuration shown in FIG. 1, there are two types of reference potentials for the eight word lines WL0 to WL7. The first ferroelectric memory cell of the present invention corresponds to, for example, ferroelectric capacitors CD00 and CD20 for reference memory cells, and the second ferroelectric memory cell is a ferroelectric capacitor for reference memory cells. It corresponds to CD10 and CD30.

  The first embodiment is characterized in that a plurality of “H” (high) data and a plurality of “L” (low) data are averaged, so that even if the ferroelectric capacitors for reference memory cells vary. A reference potential close to the ideal can be obtained with little influence.

  Here, an embodiment in which four ferroelectric capacitors (CD00 to CD30) for reference memory cells are averaged is shown. However, the present invention is not limited to this. For example, ferroelectric capacitors for reference memory cells to be averaged are shown. It is possible to increase the number of.

  In this way, it is clear that if the number of ferroelectric capacitors for reference memory cells to be averaged is increased, the influence of variations in the ferroelectric capacitors for reference memory cells is reduced.

  For example, comparing the case where 16 averages are taken with the case where two averages are taken, one ferroelectric capacitor which should output “H” (high) data outputs “L” (low) data. Sometimes, the deviation from the ideal reference potential can be suppressed to 1/8.

  As described above, since the deviation from the ideal reference potential is suppressed, a ferroelectric memory device capable of operating more normally can be obtained if a certain operating margin is secured in the sense amplifier.

(Embodiment 2)
FIG. 2 is a memory cell configuration diagram of the ferroelectric memory device according to the second embodiment of the present invention. The configuration and operation of the present embodiment will be described with reference to FIG.

  The configuration of this embodiment is basically the same as that of the first embodiment, including electrical connection, except for the following points.

  That is, the feature of the present embodiment is that the reference potential generation circuit including the ferroelectric capacitors CD00 to CD31 for reference memory cells and the equalizing circuit, and the cell plate driver CPD are arranged as shown in FIG. It is arranged near the center in the length direction.

  Here, the equalizing circuit of the present embodiment is composed of a first equalizing circuit A and a second equalizing circuit B as shown in FIG.

  That is, the first equalize circuit A is a circuit composed of N-channel MOS transistors Tr0, Tr3, Tr6, Tr8 and the like. That is, the equalizing circuit reads the various data stored in the ferroelectric capacitors for the reference memory cells CD00, CD10, CD20, CD30 as various potentials from the bit lines / BL0, / BL1, / BL2, / BL3. It is a circuit that averages these potentials. Further, the averaged potential is generated on the signal line EQ0.

  Similarly to the first equalize circuit A, a second equalize circuit B is provided. That is, the second equalize circuit B reads the various data stored in the ferroelectric capacitors for reference memory cells CD01, CD11, CD21, and CD31 as various potentials from the bit lines BL0, BL1, BL2, and BL3. It is a circuit that averages these potentials. Further, the averaged potential is generated on the signal line EQ1.

  By arranging the reference potential generating circuit near the center in the length direction of the bit line as shown in the figure, the following effects can be obtained.

  That is, even when there is a variation in characteristics depending on the location of the ferroelectric capacitor, the ferroelectric capacitor for the reference memory cell is located near the center of the ferroelectric capacitor group for the main body memory cell, so that the influence is reduced. Can do.

  In addition, as shown in the figure, by arranging the cell plate driver CPD on the right side of the bit line / BL3 and in the vicinity of the center in the length direction of each bit line, the following effects can be obtained. .

  That is, the influence of the delay difference in the drive timing by the cell plate driver CPD can be reduced, and high-speed operation becomes possible. In other words, for example, the delay difference in the timing of the cell plate signal between when the main body memory cell ferroelectric capacitor C00 is selected and when the main body memory cell ferroelectric capacitor C06 is selected can be reduced. Specifically, the timing delay difference in the case of FIG. 2 is about ½ compared to the case of the configuration shown in FIG.

(Embodiment 3)
FIG. 3 is a configuration diagram of a memory cell in a ferroelectric memory device according to the third embodiment of the present invention. The configuration and operation of the present embodiment will be described with reference to FIG.

  The configuration of this embodiment is basically similar to that of the first embodiment except for the following points.

  That is, the first feature of the present embodiment is that the ferroelectric capacitors for reference memory cells are arranged at a plurality of positions in the length direction of the bit line.

  Specifically, the reference memory cell ferroelectric capacitors CD00, CD01, CD10, and CD11 are arranged at positions close to the sense amplifiers SA0 and SA1, and the reference memory cell ferroelectric capacitors CD20, CD21, CD30, and CD31 are sensed. It is arranged at a position far from the amplifiers SA2 and SA3.

  The second feature is that, as shown in FIG. 3, the equalize circuit D is arranged near the center of the bit line in the length direction.

  Distributing and arranging the ferroelectric capacitors for reference memory cells in this manner can reduce the influence of variations in the ferroelectric capacitor characteristics on the arrangement, and can also reduce “H” (high) data and “ When the L ″ (low) data is averaged, the influence of the difference due to the time difference in the length direction of the bit line of the averaged potential can be reduced, and the high-speed operation is also effective.

  That is, in FIG. 3, since the cell plate signal line connected to the reference memory cell ferroelectric capacitors CD00 and CD10 is close to the cell plate driving circuit CDP, the potential comes out quickly. Further, since the cell plate signal line connected to the reference memory cell ferroelectric capacitors CD20 and CD30 is far from the cell plate driving circuit CDP, the potential comes out slowly. By averaging the reference memory cell ferroelectric capacitors CD00, CD10, CD20, and CD30, the speed at which the reference potential appears is averaged. Therefore, the influence of the difference in the reference potential due to the time difference in the length direction of the bit line can be reduced.

  Here, one reference potential generating bit line equalizing circuit is arranged near the center in the length direction of the bit line, but it is of course possible to arrange it on the side closer to and far from the sense amplifier. Furthermore, the ferroelectric capacitor for the reference memory cell can also be arranged near the center in the length direction of the bit line.

  Next, another embodiment shown in FIG. 4 will be briefly described.

  That is, in this example, as shown in the figure, the cell plate driver CPD is placed at a substantially central position in the arrangement of the plurality of bit lines and in the arrangement as compared with the configuration described in FIG. It is different in that it is arranged along. Other configurations are the same as those shown in FIG. 3, and the description thereof is omitted.

As a result, the lengths of the cell plate signal lines CP to the ferroelectric capacitors for reference memory cells are equalized. For this reason, the delay time during driving of the cell plate driver CPD is less dependent on the location and the timing difference is small.

(Embodiment 4)
FIG. 5 is a configuration diagram of a memory cell in a ferroelectric memory device according to the fourth embodiment of the present invention. The configuration and operation of the present embodiment will be described with reference to FIG.

  The feature of this fourth embodiment is that, by selectively connecting one reference memory cell ferroelectric capacitor to a plurality of bit lines, a reference memory cell ferroelectric capacitor for generating a reference potential, etc. This means that the layout area can be reduced.

  As shown in FIG. 5, in the memory cell configuration, bit lines BL0 to BL3 and / BL0 to / BL3 are connected to sense amplifiers SA0 to SA3. Further, ferroelectric capacitors C00, C10, C20, and C30 for main memory cells are connected to the bit lines BL0 to BL3 via N-channel MOS transistors having the word line WL0 as a gate. Reference memory cell ferroelectric capacitors CD00, CD10, CD20, and CD30 are connected to the bit lines / BL0 to / BL3 via N-channel MOS transistors having the reference word line RWL0 as a gate. Reference memory cell ferroelectric capacitors CD00, CD10, CD20, and CD30 are also connected to the bit lines BL0 to BL3 via an N-channel MOS transistor having the reference word line RWL1 as a gate. That is, the reference memory cell ferroelectric capacitors CD00, CD10, CD20, and CD30 can be connected to the bit lines BL0 to BL3 and the bit lines / BL0 to / BL3.

  The ferroelectric capacitors C00 to C37 and CD00 to CD31 are connected to a cell plate signal line CP driven by a cell plate driver CPD. The bit lines / BL0 to / BL3 are connected via an N-channel MOS transistor having the reference word line RWL0 as a gate. Further, the bit lines BL0 to BL3 and the reference memory cell ferroelectric capacitors CD00, CD10, CD20, CD30 are connected via an N-channel MOS transistor whose gate is the reference memory cell rewrite signal line REW0.

  The sense amplifier SA0 has a circuit configuration that is controlled by the sense amplifier control signals / SAP and SAN, and the precharge of the bit lines BL0 to BL3 and / BL0 to / BL3 is controlled by the bit line precharge signal BP.

  Also in the fourth embodiment, as in the first embodiment, four ferroelectric capacitors having substantially the same size as the ferroelectric capacitor for the main body memory cell are used, and two of them are changed to “H”. A method of reading (high) data and “L” (low) data from the remaining two and averaging these data is used.

  Thus, in the ferroelectric memory device of this embodiment, when the word line WLO is selected, the reference potential used when reading the potentials of the bit lines BL0, BL1, BL2, and BL3 is for the reference memory cell. The average value of the ferroelectric capacitors CD00, CD10, CD20, and CD30. The average values are read from the bit lines / BL0, / BL1, / BL2, / BL3, respectively.

  When the word line WL1 is selected, the role of the bit line pair is opposite to that in the above case, but the same ferroelectric capacitor for the reference memory cell is used.

  Therefore, in the configuration shown in FIG. 5, there is only one type of reference potential for the eight word lines WL0 to WL7. The first ferroelectric memory cell of the present invention corresponds to, for example, ferroelectric capacitors CD00 and CD20 for reference memory cells, and the second ferroelectric memory cell is a ferroelectric capacitor for reference memory cells. It corresponds to CD10 and CD30.

  Here, one ferroelectric capacitor for a reference memory cell is shared by two bit line pairs, but can be shared by more bit lines. The layout in the case of sharing two bit line pairs as in the fourth embodiment can be realized relatively easily with few wiring layers. In the layout area of the fourth embodiment, the number of ferroelectric capacitors for reference memory cells is halved compared to the case of the first embodiment.

  Of course, the reference potential generating circuit and the bit line equalizing circuit for generating the reference potential can be arranged near the center in the length direction of the bit line.

  Next, another embodiment shown in FIG. 6 will be briefly described.

  As shown in the figure, the present embodiment is another example of the embodiment shown in FIG.

  That is, in FIG. 5, for example, the reference memory cell ferroelectric capacitor CD00 is shared by one bit line pair (for example, BL0 and / BL0 of the bit line pair connected to a certain sense amplifier SA0). On the other hand, in FIG. 6, it is shared by different bit line pairs. For example, as shown in FIG. 6, the reference memory cell ferroelectric capacitor CD00 is shared by the bit line / BL0 and the bit line BL1.

  As described above, according to the present embodiment, the ferroelectric capacitors for reference memory cells are shared even for different word lines. Therefore, the number of ferroelectric capacitors for reference memory cells is set to the above embodiment. As with, it can be reduced.

  As described above, according to the above-described embodiment, even when the ferroelectric capacitors for reference memory cells vary, the influence thereof is small, and an ideal reference potential is obtained, which leads to an improvement in yield.

  Further, the arrangement of the ferroelectric capacitor for the reference memory cell and the equalize circuit can provide a reference potential that is closer to the ideal, and there is an effect that a ferroelectric memory device that operates at high speed can be obtained.

  Further, there is an effect that the layout area of the ferroelectric capacitor for the reference memory cell for generating the reference potential can be reduced.

  As is apparent from the above description, the first invention provides, for example, a plurality of ferroelectric capacitors for reference memory cells that store high level data and a plurality of reference memories that store low level data. Since each potential read from the cell ferroelectric capacitor is averaged, even if there is a variation in the ferroelectric capacitor for each reference memory cell, the influence is small and the variation is smaller than in the conventional case. The reference potential is obtained. In addition, the configuration in which the equalizing circuit is connected between a plurality of bit lines has the effect that the layout area of the ferroelectric capacitor for the reference memory cell for generating the reference potential can be realized without increasing compared to the conventional case. It is done.

  In the first invention described above, for example, an equalize circuit is connected between a plurality of bit lines, and further arranged near the center in the length direction of the bit lines, thereby affecting the influence of the equalization state of the bit lines. The effect is that the reference potential close to the ideal can be obtained at each location of the bit line.

  In the first invention described above, for example, a ferroelectric capacitor for a reference memory cell is connected to a plurality of bit lines and arranged near the center in the length direction of the bit line, so that the ferroelectric for the reference memory cell is arranged. The influence of the location of the body capacitor and the ferroelectric capacitor for the main body memory cell is reduced, and even if there is a variation in the ferroelectric capacitor for each reference memory cell, it is possible to obtain an ideal reference potential with little influence. Has the effect of being able to.

  In the first invention described above, for example, the reference ferroelectric memory cell is connected to a plurality of bit lines and arranged at a plurality of positions in the length direction of the bit line, thereby further increasing the strength for the reference memory cell. The influence of the location of the dielectric capacitor and the ferroelectric capacitor for the main body memory cell is reduced, and even if there is a variation in the ferroelectric capacitor for each reference memory cell, the reference potential is obtained with little influence. Has the effect of being able to.

  In the first invention described above, for example, the influence of the delay difference in the drive timing by the cell plate driver CPD can be reduced, and high-speed operation is possible.

  In addition, any of the above-described inventions is effective in realizing a ferroelectric memory device capable of high-speed operation in that a reference potential closer to ideal can be obtained.

  In another invention, for example, a reference ferroelectric memory cell is connected to a plurality of bit lines via a switch element, so that a reference ferroelectric memory cell for generating a reference potential can be obtained. There is an effect that the layout area can be reduced as compared with the conventional case. Further, when used in combination with the configuration of the first aspect of the invention, the reference ferroelectric memory cell capacitor is less affected by variations, a more ideal reference potential can be obtained, and the layout area can be reduced.

  In the above-described other invention, for example, by connecting one reference ferroelectric memory cell to each of the two bit line pairs connected to the sense amplifier via each switch element, the reference There is an effect that the layout area of the reference ferroelectric memory cell for generating the potential can be reduced as compared with the conventional case. Further, in this case, the reference ferroelectric memory cell is only used in common for the two bit line pairs as compared with the above example. Is advantageous. In addition, the layout area is small because it is only necessary to provide switch elements for two adjacent bit line pairs.

  As described above, the ferroelectric memory device of the present invention stores, for example, a plurality of first ferroelectric memory cells that store substantially high level data and substantially low level data. A plurality of second ferroelectric memory cells, equalizing circuit means for averaging the potentials read from each of the first and second ferroelectric memory cells, and the averaged potential as a reference potential And reading means for reading data stored in the ferroelectric capacitor for the main body memory cell, thereby making it possible to further reduce the variation in the reference potential as compared with the conventional case. .

  The ferroelectric memory device according to the present invention has an effect that the variation of the reference potential can be further reduced as compared with the conventional one, and is useful as a ferroelectric memory device or the like.

FIG. 1 is a configuration diagram of a memory cell according to the first embodiment of the present invention. FIG. 2 is a configuration diagram of a memory cell according to the second embodiment of the present invention. FIG. 3 is a configuration diagram of a memory cell according to the third embodiment of the present invention. FIG. 4 is a memory cell configuration diagram of another example in the third embodiment of the present invention. FIG. 5 is a configuration diagram of a memory cell according to the fourth embodiment of the present invention. FIG. 6 is a configuration diagram of another example of the memory cell in the fourth embodiment of the present invention. FIG. 7 is a configuration diagram of a conventional memory cell. FIG. 8 is a conventional sense amplifier circuit diagram. FIG. 9 is an operation timing chart of the conventional example.

Explanation of symbols

C00 to C37 Main body memory cell ferroelectric capacitors CD00 to CD31 Reference memory cell ferroelectric capacitors CPD Cell plate drivers SA0 to SA3 Sense amplifier CP Cell plate signal lines WL0 to WL7 Word lines RWL0 to RWL1 Reference word lines REW0 to REW1 Reference memory cell rewrite signal lines EQ0 to EQ1 Reference potential signal lines BL0 to BL3, / BL0 to / BL3 Bit line BP Bit line precharge signal / SAP, SAN Sense amplifier control signal VSS Ground voltage VDD Power supply voltage

Claims (9)

A ferroelectric memory device for storing nonvolatile data in a ferroelectric capacitor for a main body memory cell,
Three or more first reference memory cell ferroelectric capacitors respectively connected to three or more first bit lines via a first transistor whose first reference word line is a gate. Prepared,
The three or more first reference memory cell ferroelectric capacitor, said first reference memory cell having the data of the first strong for reference memory cell ferroelectric capacitor and a high level with the low level data Including at least one ferroelectric capacitor and the same number
Equalizing circuit means for averaging potentials read to the three or more first bit lines;
Reading means for reading data stored in the ferroelectric capacitor for main body memory cells, using the averaged potential as a reference potential;
A ferroelectric memory device comprising: The word lines for selecting the ferroelectric capacitors for main body memory cells and the first bit lines are arranged in a matrix, and a memory cell array is constituted by the ferroelectric capacitors for main body memory cells,
2. The ferroelectric memory device according to claim 1, wherein the equalizing circuit means is disposed near a center in a length direction of the first bit line. The word lines for selecting the ferroelectric capacitors for main body memory cells and the first bit lines are arranged in a matrix, and a memory cell array is constituted by the ferroelectric capacitors for main body memory cells,
2. The ferroelectric memory device according to claim 1, wherein the first reference memory cell ferroelectric capacitor is disposed in the vicinity of the center of the first bit line in the length direction. The word lines for selecting the ferroelectric capacitors for main body memory cells and the first bit lines are arranged in a matrix, and a memory cell array is constituted by the ferroelectric capacitors for main body memory cells,
2. The ferroelectric memory according to claim 1, wherein the ferroelectric capacitors for the first reference memory cell are distributed at a plurality of positions in a length direction of the first bit line. apparatus. The word lines for selecting the ferroelectric capacitors for main body memory cells and the first bit lines are arranged in a matrix, and a memory cell array is constituted by the ferroelectric capacitors for main body memory cells,
Cell plate driving means for applying a predetermined potential to the ferroelectric capacitor for the main body memory cell;
2. The ferroelectric memory device according to claim 1, wherein the cell plate driving means is disposed near the center in the length direction of the first bit line. The word lines for selecting the ferroelectric capacitors for main body memory cells and the first bit lines are arranged in a matrix, and a memory cell array is constituted by the ferroelectric capacitors for main body memory cells,
Cell plate driving means for applying a predetermined potential to the ferroelectric capacitor for the main body memory cell;
2. The ferroelectric memory device according to claim 1, wherein the cell plate driving means is arranged substantially near the center in the array of the three or more first bit lines.   7. The ferroelectric memory device according to claim 1, wherein the three or more first bit lines are connected to different sense amplifiers. Three or more second reference memory cell ferroelectric capacitors respectively connected to three or more second bit lines via a second transistor whose second reference word line is a gate ; ,
The three or more second reference memory cell ferroelectric capacitor, said second reference memory cell having the data of the second strong for reference memory cell ferroelectric capacitor and a high level with the low level data Including at least one ferroelectric capacitor and the same number
Second equalize circuit means for averaging potentials read to the three or more second bit lines;
Readout means for reading out data stored in the ferroelectric capacitor for the main body memory cell by using the averaged potential as a reference potential,
The three or more second bit lines are respectively connected to the different sense amplifiers, and the first bit line and the second bit line form a bit line pair. The ferroelectric memory device according to claim 7.   2. The ferroelectric memory device according to claim 1, wherein the first equalizing circuit means is connected to the first reference word line.

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