JP4121201B2

JP4121201B2 - Triple well manufacturing method of semiconductor memory device

Info

Publication number: JP4121201B2
Application number: JP32556498A
Authority: JP
Inventors: 相必沈; 元成李
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1998-03-26
Filing date: 1998-11-16
Publication date: 2008-07-23
Anticipated expiration: 2018-11-16
Also published as: TW396506B; JPH11297853A

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体メモリ装置の製造方法に係り、特に半導体メモリ装置のトリプルウェルの製造方法に関する。
【０００２】
【従来の技術】
通常、ＣＭＯＳＤＲＡＭ装置はラッチアップ免疫性、セル隔離並びに動作速度を改善するために、基板にバックバイアス電圧(back bias voltage：以下ＶＢＢ）を印加する。しかし、サブミクロン装置のような高集積半導体メモリ装置において、前記バックバイアス電圧はＮチャンネルトランジスタで短チャンネル効果を増やすという短所がある。このような問題点を解決するために、メモリセルアレイ領域にはバックバイアス電圧ＶＢＢを印加して周辺回路領域中Ｎチャンネルトランジスタが形成される領域には接地電圧ＶＳＳを印加してメモリ装置の特性を向上させることができるトリプルウェル(triple well)構造が提案された。
【０００３】
このようなトリプルウェル構造を採用する半導体メモリ装置が図１に示されている。図１を参照すれば、Ｐ型基板１００上に各々ソース並びにドレーン領域になるＮ型不純物領域１１２、１２２並びにゲート酸化膜１１４、１２４を介在して形成されたゲート１１６、１２６で構成されるＮチャンネルトランジスタが形成されるＰ型第１ウェル１１０並びにＰ型第２ウェル１２０が形成されている。また周辺回路領域には、ソース並びにドレーン領域になるＰ型不純物領域１３２、ゲート酸化膜１３４並びにゲート１３６で構成されるＰチャンネルトランジスタが形成されるＮ型第１ウェル１３０が形成されている。
【０００４】
また、Ｐ型第１ウェル１１０とＰ型第２ウェル１２０は、Ｐ型第２ウェル１２０を包んでいるＮ型第２ウェル１４０により分離されている。Ｎ型第２ウェル１４０は、基板の表面から第１深さになる領域まで垂直に延設される側壁領域１４２と、側壁領域１４２の下端部と連結され、基板から第２深さになる領域に水平に形成されたベース領域１４４とで構成されている。
【０００５】
したがって、Ｐ型第２ウェル１２０内に形成されたＰ型不純物領域１２８にはバックバイアス電圧ＶＢＢが印加され、Ｐ型第１ウェル１１０内に形成されたＰ型不純物領域１１８には接地電圧ＶＳＳが印加される。そして、Ｎ型第１ウェル１３０内に形成されたＮ型不純物領域１３８には電源電圧ＶＣＣが印加される。
【０００６】
ところが図１に示されたように、Ｐ型第１ウェル１１０、Ｐ型第２ウェル１２０、Ｎ型第１ウェル１３０、Ｎ型第２ウェル１４０のベース領域１４４並びに側壁領域１４２で構成されたトリプルウェル構造を製造するためには最小４回以上の写真蝕刻工程が要求されて工程が非常に複雑になるという短所がある。
【０００７】
そして、トリプルウェル構造では、ベース領域１４４と側壁領域１４２でなされたＮ型第２ウェル１４０がＰ型第２ウェル１２０を完全に包んでＰ型第１ウェル１１０と電気的に完全に分離させることが重要である。ところが、ベース領域１４４を形成するための写真蝕刻工程時ミスアラインが発生して点線で表示されたようなＮ型第２ウェルのベース１４４′が形成される場合、ベース１４４′と側壁領域１４２が十分にオーバーラップ出来なくＰ型第１ウェル１１０とＰ型第２ウェル１２０が短絡されるという問題点が発生する。
【０００８】
【発明が解決しようとする課題】
本発明が果たそうとする技術的課題は単純化された工程で電気的特性が向上されたトリプルウェルを製造できるトリプルウェルの製造方法を提供することにある。
【０００９】
【課題を解決するための手段】
前記技術的課題を達成するための本発明の製造方法によって形成されるトリプルウェルは、第１導電型の半導体基板内に形成された第１導電型の第１ウェル、第１導電型の第２ウェル、第２導電型の第１ウェル並びに前記第１導電型の第１ウェルと前記第１導電型の第２ウェルを分離させるために前記第１導電型の第２ウェルを包む第２導電型の第２ウェルで構成される。そして、前記第２導電型の第２ウェルは、基板の表面から基板内に第１深さになる領域まで延設された側壁領域と、前記側壁領域の下端部と連結されて基板から第２深さになる領域に水平に形成されたベース領域とから構成される。
【００１０】
前記トリプルウェルを製造するための本発明の一態様によれば、前記第２導電型の第２ウェルのベース領域と前記第１導電型の第２ウェルは、一つのマスクパターンをイオン注入マスクとして使用して形成する。そして、前記第２導電型の第２ウェルのベース領域を形成する時、前記マスクパターンをイオン注入マスクとして使用し第２導電型の不純物が前記半導体基板に垂直な方向と入射角θをなしながら傾斜するように前記基板の表面に入射されるように前記第２導電型の不純物を注入して前記マスクパターンにより露出された領域より広い領域に前記第２導電型の第２ウェルのベース領域を形成する。
【００１１】
前記入射角θは５゜乃至３０゜であることが望ましい。また、前記第２導電型の第２ウェルのベース領域を限定するマスクパターンは、前記第２導電型の第２ウェルの側壁領域の内側壁により限定される半導体基板領域を露出させるように形成されることが望ましい。
【００１２】
前記トリプルウェルを製造するための本発明の他の態様によれば、前記側壁領域を形成するためのイオン注入エネルギーと前記ベース領域を形成するためのイオン注入エネルギーを同一または類似にして前記側壁領域と前記ベース領域を形成することによって、前記側壁領域と前記ベース領域がオーバーラップされて前記第１導電型の第１ウェルと前記第１導電型の第２ウェルを完全に分離させるようにし、前記ベース領域と前記第１導電型の第２ウェルは同一マスクパターンをイオン注入マスクとして使用して形成する。
【００１３】
前記第２導電型の第２ウェルの側壁領域とベース領域を形成する段階は、先に、前記第１導電型の半導体基板を提供した後、前記第１導電型の半導体基板上に前記第２導電型の第２ウェルの側壁領域を限定する第１マスクパターンを形成する。次に、前記第１マスクパターンをイオン注入マスクとして使用し第２導電型の不純物を第１エネルギーで注入する。続いて、前記第１マスクパターンを取り除いた後、前記半導体基板上に前記ベース領域を限定する第２マスクパターンを形成する。最後に前記第２マスクパターンをイオン注入マスクとして使用し前記第２導電型の不純物を前記第１エネルギーと同一または類似な第２エネルギーで注入して前記第１深さと同一または類似な第２深さに該当する領域に前記ベース領域を形成する。
【００１４】
望ましくは、前記第１マスクパターンを取り除く段階前に前記第１マスクパターンをイオン注入マスクとして使用し第２導電型の不純物を前記第１エネルギーより大きいエネルギーで注入する段階をさらに実施する。
【００１５】
前記トリプルウェルを製造するための本発明のまた他の態様によれば、先に、前記第１導電型の半導体基板を提供した後、前記第１導電型の半導体基板上に前記第２導電型の第２ウェルのベース領域を限定するマスクパターンを形成する。次に、前記マスクパターンをイオン注入マスクとして使用し第２導電型の不純物を注入して前記第２導電型の第２ウェルのベース領域を形成する。続いて、前記マスクパターンの側壁にスペーサを形成した後、前記マスクパターン並びにスペーサをイオン注入マスクとして使用し第１導電型の不純物を注入して前記第１導電型の第２ウェルを形成する。
【００１６】
前記マスクパターンは、前記第１導電型の第２ウェルの側壁に形成される前記第２導電型の第２ウェルの側壁領域を一部または全部露出させ、前記スペーサは、前記露出された第２ウェルの側壁領域をおおうことが望ましい。
【００１７】
前記トリプルウェルを製造するための本発明のまた他の態様によれば、先に、前記第１導電型の半導体基板を提供した後、前記第１導電型の半導体基板上に前記第１導電型の第２ウェルを限定する第１マスクパターンを形成する。次に、前記第１マスクパターンをイオン注入マスクとして使用し第１導電型の不純物を注入して前記第１導電型の第２ウェルを形成する。続いて、前記第１マスクパターンを縮少させて前記第１マスクパターンにより露出された領域より広い領域を露出させる第２マスクパターンで形成する。最後に、前記第２マスクパターンをイオン注入マスクとして使用し第２導電型の不純物を注入して前記第１導電型の第２ウェルの下に前記第１導電型の第２ウェルより大きい幅を有する前記第２導電型の第２ウェルを形成する。
【００１８】
前記第２マスクパターンは、前記第１導電型の第２ウェルの側壁に形成される前記第２導電型の第２ウェルの側壁領域を一部または全部を露出させるように形成されることが望ましい。
本発明によれば、簡単な工程で完全な構造のトリプルウェルを形成することができる。
【００１９】
【発明の実施の形態】
以下添付した図面を参照して本発明の望ましい実施の形態を説明することによって本発明を詳細に説明する。しかし、本発明は以下で開示される実施の形態の一例に限らず相異なる多様な形態で具現されることであり、単に本実施の形態の一例は本発明の開示が完全なるようにし、通常の知識を有する者に発明の範疇を完全に知らせるために提供されることである。添付された図面で多様な膜と領域の厚さは明瞭性のために強調された。そして、図面に表示された導電型は例示のためのことであって基板の導電型がＰ型の場合を基準として示したことである。しかし、基板の導電型がＮ型の場合にも同じく適用でき、この場合ウェルの導電型も示された導電型と反対導電型を有するようになる。図面で同一参照符号は同一部材を示す。
【００２０】
＜実施例１＞
図２を参照すれば、第１導電型、例えばＰ型の半導体基板２００上にパッド酸化膜２０５を通常の方法で形成した後、第１導電型の第１ウェル、例えばＰ型第１ウェル２１０を限定する第１マスクパターン２１０Ｍを形成する。次に、第１マスクパターン２１０Ｍをイオン注入マスクとして使用し、Ｐ型不純物イオン２０９を注入することによってＰ型第１ウェル２１０を形成する。続いて、第１マスクパターン２１０Ｍを通常の方法で取り除く。
【００２１】
図３を参照すれば、Ｐ型第１ウェル２１０が形成された半導体基板２００の全面に第２導電型の第１ウェル、すなわち、Ｎ型第１ウェル並びに第２導電型の第２ウェル、すなわち、Ｎ型第２ウェルの側壁領域を限定する第２マスクパターン３４２Ｍを形成する。次に、第２マスクパターン３４２Ｍをイオン注入マスクとして使用しＮ型不純物イオン３４１を注入して、周辺回路領域にはＮ型第１ウェル３３０を、メモリセルアレイ領域にはＮ型第２ウェルの側壁領域３４２を、形成する。続いて、第２マスクパターン３４２Ｍを通常の方法で取り除く。
【００２２】
図４を参照すれば、Ｎ型第２ウェルのベース領域を限定する第３マスクパターン４４４Ｍを基板２００の全面に形成する。第３マスクパターン４４４ＭはＮ型第２ウェルの側壁領域３４２の内側壁により限定される半導体基板領域を露出させるように形成することが望ましい。
【００２３】
次に、第３マスクパターン４４４Ｍをイオン注入マスクとして使用し、Ｎ型不純物イオン４４３を傾斜するように注入してＮ型第２ウェルのベース領域４４４を形成して側壁領域３４２とベース領域４４４で構成されたＮ型第２ウェル４４０を完成する。
【００２４】
Ｎ型不純物イオン４４３を傾斜するように注入する方式としては、半導体基板２００をイオン注入装置（図示せず）内にローディングする時不純物イオンの入射方向と基板２００に垂直な方向が入射角θをなして傾斜するようにローディングする方式を使用する。したがって、不純物イオンが基板２００に垂直な方向と入射角θをなしながら傾斜するように基板２００表面に入射される。
【００２５】
この時、入射角θは５゜乃至３０゜になるようにすることが望ましい。入射角はベース領域４４４と側壁領域３４２がオーバーラップされる幅Ｗ１と不純物イオンの入射範囲値（Projected Range：基板の表面から不純物濃度最高地点までの距離、以下Ｒｐ）により決定される。
【００２６】
すなわち、入射角（傾斜角）θは下記式１により計算できる。
ｓｉｎθ＝Ｗ１Ｒｐ … 式１
前記式中θは傾斜角であり、Ｗ１はベース領域４４４と側壁領域３４２がオーバーラップされる幅であり、Ｒｐは不純物イオンの入射範囲値である。
【００２７】
本発明によって製造されるトリプルウェルの適正Ｒｐは、１乃至１．８μｍであり、適正オーバーラップ幅Ｗ１が０．２乃至０．８μｍである。したがって、これを前記式１に代入して計算すればθが５゜乃至３０゜がなるようして不純物を注入することが望ましいということがわかる。
【００２８】
前述したように、本実施例ではＮ型の不純物４４３を傾斜するようにイオン注入するためにＮ型第２ウェルのベース領域４４４が第３マスクパターン４４４Ｍにより露出される領域より両側面にさらに拡張されて形成されることができる。したがって、Ｎ型第２ウェルのベース領域４４４がＮ型第２ウェルの側壁領域３４２とオーバーラップされる幅Ｗ１を増大させ、Ｐ型第１ウェル２１０と後続工程で形成されるＰ型第２ウェル（図５の５２０参考）を電気的に完全に分離させてこの二つのウェルが短絡されることを防止し、二つのウェル２１０、５２０に相異なる電圧を印加することが可能なようにする。
【００２９】
図５を参照すれば、Ｎ型第２ウェルのベース領域４４４を限定する第３マスクパターン４４４Ｍをそのままイオン注入マスクとして使用し、Ｐ型の不純物イオン５１９を注入してＰ型第２ウェル５２０を形成する。
【００３０】
前述したように本実施例によってトリプルウェル構造を形成すれば、Ｎ型第２ウェルのベース領域４４４と側壁領域３４２がオーバーラップされる幅Ｗ１を最大化できる。したがって、Ｐ型第１ウェル２１０とＰ型第２ウェル５２０が短絡されることを防止して電気的に完全に分離させることができる。また、Ｎ型第２ウェルのベース領域４４４とＰ型第２ウェル５２０を一つのマスクパターン４４４Ｍを使用して形成することができる。
【００３１】
すなわち、工程が複雑で生産コストに多くの影響を及ぼすマスクパターン形成工程、例えばフォトレジストパターン形成工程を減少させることができるので、工程が単純化されて生産コストを節減できる長所がある。
【００３２】
本実施例ではＰ型第１ウェル２１０、Ｎ型第１ウェル２３０並びにＮ型第２ウェルの側壁領域３４２を予め形成した後にＮ型第２ウェルのベース領域４４４とＰ型第２ウェル５２０を形成したが、その製造順序を変えて形成することができることはもちろんである。すなわち、Ｎ型第２ウェルのベース領域４４４とＰ型第２ウェル５２０を形成した後、Ｐ型第１ウェル２１０、Ｎ型第１ウェル２３０並びにＮ型第１ウェルの側壁領域３４２を形成することもできる。そして、Ｐ型第２ウェル５２０を先に形成してＮ型第２ウェルのベース領域４４４を形成することもできる。
【００３３】
＜実施例２＞
図６を参照すれば、Ｐ型第１ウェル６１０が形成されている半導体基板６００のパッド酸化膜６０５上にＮ型第１ウェル並びにＮ型第２ウェルの側壁領域を限定する第１マスクパターン６４２Ｍを形成する。第１マスクパターン６４２Ｍをイオン注入マスクとして使用し、Ｎ型不純物イオン６４１を０．２乃至１．０ＭｅＶで注入して深さがＤ１のＮ型第１ウェル６３０′並びにＮ型第２ウェルの側壁領域６４２′を形成する。
【００３４】
次に、図７に示されたように、第１マスクパターン６４２Ｍをそのままイオン注入マスクとして使用しイオン注入エネルギーを１．０乃至１．８ＭｅＶに変えてＮ型不純物イオン７４１を注入して深さがＤ２のＮ型第１ウェル７３０′並びにＮ型第２ウェルの側壁領域７４２′を形成する。したがって、深さがＤ１のＮ型第１ウェル６３０′と深さがＤ２のＮ型第１ウェル７３０′で構成されたＮ型第１ウェル７３０と深さがＤ１のＮ型第２ウェルの側壁領域６４２′並びに深さがＤ２のＮ型第２ウェルの側壁領域７４２′で構成されたＮ型第２ウェルの側壁領域７４２を完成する。続いて第１マスクパターン６４２Ｍを通常の方法で取り除く。
【００３５】
図８を参照すれば、Ｎ型第２ウェルのベース領域を限定する第２マスクパターン８４４Ｍをパッド酸化膜６０５上に形成する。次に、第２マスクパターン８４４Ｍをイオン注入マスクとして使用し、Ｎ型の不純物８４３を１．０乃至１．８ＭｅＶのイオン注入エネルギーで注入してＮ型第２ウェルのベース領域８４４を形成する。
【００３６】
したがって、Ｎ型第２ウェルの側壁領域７４２の最大Ｒｐとベース領域８４４の最大Ｒｐ値が同一になるので、図８に示されているように側壁領域７４２とベース領域８４４が十分にオーバーラップされて完全なＮ型第２ウェル８４０を完成できる。
【００３７】
図９を参照すれば、第２マスクパターン８４４Ｍをそのままイオン注入マスクとして使用し、Ｐ型不純物イオン９１９を１００乃至５００ＭｅＶで注入してＰ型第２ウェル９２０を形成する。
【００３８】
第２実施例では、Ｎ型第２ウェルの側壁領域７４２を２回のイオン注入工程を経て形成する。特に、Ｎ型第２ウェルのベース領域８４４を形成するための不純物のイオン注入エネルギーとＮ型第２ウェルの側壁領域７４２を最大深さＤ２に形成するためのイオン注入エネルギーを同一または類似にすることによりベース領域８４４と側壁領域７４２が垂直方向に十分にオーバーラップされて完全なＮ型第２ウェル８４０を形成することができるようにする。
【００３９】
また、Ｎ型第２ウェルのベース領域８４４とＰ型第２ウェル９２０を一つのマスクパターン８４４Ｍで限定するために工程が単純化されるという長所がある。
本実施例でＮ型第２ウェルの側壁領域７４２を形成するために相互異なるイオン注入エネルギーで２回のイオン注入工程を実施する理由は次の通りである。
【００４０】
Ｎ型第２ウェルのベース領域８４４が形成される深さであるＤ２が大きい場合、すなわち、ベース領域８４４を形成するためのイオン注入エネルギーが大きい場合、ベース領域８４４を形成するためのイオン注入エネルギーと同一または類似なエネルギーで１回のみイオン注入して側壁領域７４２を形成すれば、側壁領域が基板の表面からＤ２深さまで連続的に連結されなく基板の表面から分離されて深さがＤ２になる領域付近にのみ形成される場合を防止するためである。
【００４１】
したがって、側壁領域７４２とベース領域８４４を垂直方向に十分にオーバーラップさせて第１導電型の第１ウェル６１０と第２ウェル９２０を完全に分離させることができ、１回のイオン注入工程で側壁領域７４２を基板の表面からベース領域８４４が形成される深さ（例：Ｄ２）まで延設させることさえできるならば、ベース領域８４４を形成するためのイオン注入エネルギーと同一または類似なイオン注入エネルギーで１回のイオン注入工程を実施して側壁領域７４２を形成することがさらに望ましい。
また、必要に応じてはイオン注入工程の回数を２回以上に増やすことができることはもちろんである。
【００４２】
＜実施例３＞
図１０を参照すれば、第２実施例の図６乃至図７に示されているような同一な工程を経て、Ｐ型第１ウェル６１０、Ｎ型第１ウェル７３０並びにＮ型第２ウェルの側壁領域７４２を形成する。次に、Ｎ型第２ウェルのベース領域を限定するマスクパターン１０４４Ｍをパッド酸化膜６０５上に形成する。続いて、マスクパターン１０４４Ｍをイオン注入マスクとして使用し、Ｎ型不純物イオン１０４３が基板７００に対してθの角度をなしながら入射されるように注入する。その結果、側壁領域７４２と垂直方向でオーバーラップされるのみならず水平方向にもオーバーラップされるベース領域１０４４を形成してＮ型第２ウェル１０４０を完成する。
【００４３】
図１１を参照すれば、Ｎ型第２ウェルのベース領域１０４４を限定するマスクパターン１０４４Ｍをそのまま使用してＰ型不純物イオン１１１９を注入してＰ型第２ウェル１１２０を形成する。
【００４４】
本実施例によれば、Ｎ型第２ウェルの側壁領域７４２は相互異なるイオン注入エネルギーで２回以上イオン注入して形成し、ベース領域１０４４は不純物イオンを傾斜するように注入して形成するために、側壁領域７４２とベース領域１０４４が垂直方向並びに水平方向に広い領域に渡ってオーバーラップされるのでＰ型第１ウェル６１０とＰ型第２ウェル１１２０を電気的に完全に隔離させることができる。
【００４５】
また、第１実施例並びに第２実施例と同じく、一つのマスクパターン１０４４ＭでＮ型第２ウェルのベース領域１０４４とＰ型第２ウェル１１２０を同時に形成するために製造工程が簡単になり生産コストを節減できることはもちろんである。
【００４６】
＜実施例４＞
図１２を参照すれば、パッド酸化膜１２０５、Ｐ型第１ウェル１２１０、Ｎ型第１ウェル１２３０並びにＮ型第２ウェルの側壁領域１２４２が形成された半導体基板１２００上にＮ型第２ウェルのベース領域を限定するマスクパターン１２４４Ｍ、例えばフォトレジストパターンを形成する。次に、マスクパターン１２４４Ｍをイオン注入マスクとして使用し、Ｎ型不純物イオン１２４３を注入してＮ型第２ウェルのベース領域１２４４を形成する。
【００４７】
この時、マスクパターン１２４４Ｍは半導体基板１２００内に所定深さで形成された側壁領域１２４２の一部または全部を露出させるように形成されてベース領域１２４４が側壁領域１２４２と十分にオーバーラップされるようにする。その結果側壁領域１２４２とベース領域１２４４で構成されたＮ型第２ウェル１２４０を完成する。
【００４８】
次に、前記マスクパターン１２４４Ｍをフォトレジストパターンで形成した場合にはフォトレジストパターン１２４４Ｍと半導体基板１２００間の接着力を良くするためにベーク（ｂａｋｅ）工程を実施する。フォトレジストパターン１２４４Ｍのベーク工程は概略１８０乃至２３０℃程度で進めることが望ましく、約２００℃で進めることが望ましい。あまり高い温度でベーク工程を進めると、フォトレジストパターン１２４４Ｍが変形される場合もあるからである。
続いて、マスクパターン１２４４Ｍが形成されている半導体基板１２００の全面にスペーサ形成用絶縁膜（図示せず）を形成する。
【００４９】
絶縁膜としては酸化膜を使用することが望ましい。そして、マスクパターン１２４４Ｍをフォトレジストパターンに形成する場合、酸化膜を高温で形成すればフォトレジストパターンが縮まるパッドリング（puddling）が発生する。したがって、酸化膜は低温で形成することが望ましい。したがって、低温で酸化膜を形成することができるプラズマ化学気相蒸着法を使用して形成することが望ましく、蒸着温度は１８０乃至２５０℃に設定することが望ましい。
【００５０】
続けて、絶縁膜が形成された半導体基板の全面に対して異方性蝕刻を進めることによって、図１３に示されているように、マスクパターン１２４４Ｍの側壁に一定幅Ｗ２を有するスペーサ１３２０Ｓを形成する。
【００５１】
この時、酸化膜スペーサ１３２０Ｓの幅Ｗ２はマスクパターン１２４４Ｍの厚さ並びにマスクパターン１２４４Ｍが露出させている半導体基板１２００の露出幅ｄに依存する。例えばマスクパターン１２４４Ｍの厚さが４５００Åであり、マスクパターン１２４４Ｍにより露出された半導体基板の距離が数百μｍである時マスクパターン１２４４Ｍ上に形成される酸化膜の厚さは１０００乃至４０００Å程度で形成することが望ましい。１０００乃至４０００Å厚さで形成された酸化膜を異方性蝕刻すれば、マスクパターン１２４４Ｍの側壁に幅Ｗ２が１０００乃至４０００Åの酸化膜スペーサ１３２０Ｓを形成できるようになる。
【００５２】
この時形成される酸化膜スペーサ１３２０Ｓの幅Ｗ２がマスクパターン１２４４Ｍにより露出されたＮ型第２ウェルの側壁領域１２４２をすべて遮って側壁領域１２４２内の半導体基板１２００領域のみ露出させることができる大きさで形成されるべきことはもちろんである。
【００５３】
引続きマスクパターン１２４４Ｍとスペーサ１３２０Ｓをイオン注入マスクとして使用しＰ型不純物イオン１３１９を注入してＰ型第２ウェル１３２０を形成する。
【００５４】
本実施例によれば、酸化膜スペーサ１３２０Ｓの幅Ｗ２によってＮ型ウェルの側壁領域１２４２とベース領域１２４４がオーバーラップされる幅Ｗ１を自動的に決定できる。
【００５５】
再び言えば、酸化膜スペーサ１３２０Ｓを形成できる幅Ｗ２ほどのＮ型第２ウェルの側壁領域１２４２を露出させるマスクパターン１２４４Ｍを形成した後、Ｎ型不純物を注入してＮ型第２ウェルの側壁領域１２４２と一定幅Ｗ１ぐらいオーバーラップされるＮ型第２ウェルのベース領域１２４４を形成することができる。
【００５６】
また、酸化膜スペーサ１３２０Ｓを自己整列方式で形成することによってＰ型第２ウェル１３２０をＮ型第２ウェル１２４０内にのみ形成することができる。したがって、Ｐ型第１ウェル１２１０とＰ型第２ウェル１３２０間の短絡を効果的に防止できる。
【００５７】
また、前述した第１実施例乃至第３実施例と同じく一つのマスクパターン１２４４ＭのみでＮ型第２ウェルのベース領域１２４４とＰ型第２ウェル１３２０を同時に形成することができるために製造工程が簡単になり生産コストを節減できる。
【００５８】
＜第５実施例＞
図１４を参照すれば、パッド酸化膜１４０５が全面に形成され、Ｐ型第１ウェル１４１０並びにＮ型第１ウェル１４３０並びにＮ型第２ウェルの側壁領域１４４２が形成されている半導体基板１４００上にＰ型第２ウェル１４２０が形成される領域を露出させる第１マスクパターン１４２０Ｍを形成する。望ましくは、第１マスクパターン１４２０ＭはＮ型第２ウェルの側壁領域１４４２をすべて遮るように形成する。
【００５９】
続いて、前記第１マスクパターン１４２０Ｍをイオン注入マスクとして使用し、Ｐ型不純物イオン１４１９を注入してＮ型第２ウェルの側壁領域１４２４により限定された半導体基板１４００内にＰ型第２ウェル１４２０を形成する。
【００６０】
図１５を参照すれば、Ｐ型第２ウェル１４２０を形成した後、前記第１マスクパターン１４２０Ｍを縮少させる工程を進める。第１マスクパターン１４２０Ｍをフォトレジストパターンで形成した場合、フォトレジストパターン１４２０Ｍに対して等方性蝕刻を実施してフォトレジストパターンの大きさを縮少させる。等方性蝕刻は通常のプラズマ蝕刻方式を使用して進めたり通常的なデスカム（descum）装備を用いて進める。
【００６１】
すなわち、点線で示された元来の第１マスクパターン１４２０Ｍを縮少させて実線でなされた第２マスクパターン１５４４Ｍになるようにする。第２マスクパターン１５４４ＭはＮ型第２ウェルのベース領域を限定する。第２マスクパターン１５４４ＭはＮ型第２ウェルの側壁領域１４４２の一部または全部を露出させるように形成される。
【００６２】
第１マスクパターン１４２０Ｍが第１フォトレジストパターンであり、これを縮少させて第２マスクパターン１５４４Ｍ、すなわち第２フォトレジストパターンを形成する場合には第２フォトレジストパターンの厚さが概略２５００Å以上になるように工程条件を調節する。第２フォトレジストパターンがイオン注入マスクとしての役割を十分に遂行できるようにするためである。
【００６３】
続いて、第２マスクパターン１５４４Ｍをイオン注入マスクとして使用し、Ｎ型不純物イオン１５４３を注入してＮ型第２ウェルのベース領域１５４４を形成する。図１５に示されているように第１マスクパターン１４２０Ｍが縮少された幅Ｗ２が結局Ｎ型第２ウェルのベース領域１５４４とＮ型第２ウェルの側壁領域１５４２がオーバーラップされる幅Ｗ１を決定する。
【００６４】
すなわち、本実施例は一つのマスクパターン１４２０Ｍを形成した後、これを用いてＰ型第２ウェル１４２０を形成した後、その大きさを縮少させてＰ型第２ウェル１４２０より広い幅を有するＮ型第２ウェルのベース領域１５４４を形成する。したがって、Ｎ型第２ウェルのベース領域１５４４とＮ型第２ウェルの側壁領域１５４２を十分にオーバーラップさせて形成してＮ型第２ウェル１５４０を完成する。したがって、Ｐ型第１ウェル１４１０とＰ型第２ウェル１４２０間に短絡が発生する問題点を単純化された工程で効果的に防止できる。
【００６５】
【発明の効果】
本発明によれば、第１導電型の第２ウェルを取り囲んで第１導電型の第１ウェルと分離させて第１導電型の第１ウェルと第２ウェルに相異なる電圧が印加できるようにする第２導電型の第２ウェルのベース領域と第１導電型の第２ウェルを同一マスクを使用して形成する。また、第２導電型の第２ウェルのベース領域と側壁領域が完全に連結されるよう形成する。それゆえに、特性が向上されたトリプルウェル構造を単純化された工程で効果的に形成することができる。
【図面の簡単な説明】
【図１】本発明で製造しようとするトリプルウェル構造を有する半導体メモリ装置の断面図である。
【図２】本発明の第１実施例によってトリプルウェルを製造する方法を説明するための製造工程中間段階構造物の断面図を示す。
【図３】本発明の第１実施例によってトリプルウェルを製造する方法を説明するための製造工程中間段階構造物の断面図を示す。
【図４】本発明の第１実施例によってトリプルウェルを製造する方法を説明するための製造工程中間段階構造物の断面図を示す。
【図５】本発明の第１実施例によってトリプルウェルを製造する方法を説明するための製造工程中間段階構造物の断面図を示す。
【図６】本発明の第２実施例によってトリプルウェルを製造する方法を説明するための製造工程中間段階構造物の断面図を示す。
【図７】本発明の第２実施例によってトリプルウェルを製造する方法を説明するための製造工程中間段階構造物の断面図を示す。
【図８】本発明の第２実施例によってトリプルウェルを製造する方法を説明するための製造工程中間段階構造物の断面図を示す。
【図９】本発明の第２実施例によってトリプルウェルを製造する方法を説明するための製造工程中間段階構造物の断面図を示す。
【図１０】本発明の第３実施例によってトリプルウェルを製造する方法を説明するための製造工程中間段階構造物の断面図を示す。
【図１１】本発明の第３実施例によってトリプルウェルを製造する方法を説明するための製造工程中間段階構造物の断面図を示す。
【図１２】本発明の第４実施例によってトリプルウェルを製造する方法を説明するための製造工程中間段階構造物の断面図を示す。
【図１３】本発明の第４実施例によってトリプルウェルを製造する方法を説明するための製造工程中間段階構造物の断面図を示す。
【図１４】本発明の第５実施例によってトリプルウェルを製造する方法を説明するための製造工程中間段階構造物の断面図を示す。
【図１５】本発明の第５実施例によってトリプルウェルを製造する方法を説明するための製造工程中間段階構造物の断面図を示す。
【符号の説明】
１００Ｐ型基板
１１０Ｐ型第１ウェル
１１２、１２２、１３８Ｎ型不純物領域
１１４、１２４ゲート酸化膜
１１６、１２６、１３６ゲート
１１８、１２８Ｐ型不純物領域
１２０Ｐ型第２ウェル
１３０Ｎ型第１ウェル
１３２Ｐ型不純物領域
１３４ゲート酸化膜
１４０Ｎ型第２ウェル
１４２側壁領域
１４４ベース領域
１４４′ ベース[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for manufacturing a triple well of a semiconductor memory device.
[0002]
[Prior art]
In general, a CMOS DRAM device applies a back bias voltage (hereinafter referred to as VBB) to a substrate in order to improve latch-up immunity, cell isolation, and operation speed. However, in a highly integrated semiconductor memory device such as a submicron device, the back bias voltage is an N channel transistor and has a disadvantage of increasing a short channel effect. In order to solve such a problem, the memory cell array region is applied with a back bias voltage VBB, and the region of the peripheral circuit region where the N-channel transistor is formed is applied with the ground voltage VSS to improve the characteristics of the memory device. A triple well structure has been proposed that can be improved.
[0003]
A semiconductor memory device employing such a triple well structure is shown in FIG. Referring to FIG. 1, an N formed of N-type impurity regions 112 and 122 serving as source and drain regions and gate oxide films 114 and 124 formed on a P-type substrate 100 with gate oxide films 114 and 124 interposed therebetween. A P-type first well 110 and a P-type second well 120 in which channel transistors are formed are formed. In the peripheral circuit region, an N-type first well 130 is formed in which a P-channel transistor composed of a P-type impurity region 132 serving as a source and drain region, a gate oxide film 134, and a gate 136 is formed.
[0004]
The P-type first well 110 and the P-type second well 120 are separated by an N-type second well 140 that encloses the P-type second well 120. The N-type second well 140 is connected to the side wall region 142 extending vertically from the surface of the substrate to the region having the first depth and the lower end of the side wall region 142, and is the region having the second depth from the substrate. And a base region 144 formed horizontally.
[0005]
Accordingly, the back bias voltage VBB is applied to the P-type impurity region 128 formed in the P-type second well 120, and the ground voltage VSS is applied to the P-type impurity region 118 formed in the P-type first well 110. Applied. The power supply voltage VCC is applied to the N-type impurity region 138 formed in the N-type first well 130.
[0006]
However, as shown in FIG. 1, the triple formed of the P-type first well 110, the P-type second well 120, the N-type first well 130, the base region 144 of the N-type second well 140, and the sidewall region 142. In order to manufacture the well structure, there is a disadvantage that the photolithography process is required at least four times and the process becomes very complicated.
[0007]
In the triple well structure, the N-type second well 140 formed by the base region 144 and the sidewall region 142 completely encloses the P-type second well 120 and is electrically completely separated from the P-type first well 110. is important. However, when misalignment occurs during the photolithography process for forming the base region 144 and the base 144 'of the N-type second well as indicated by the dotted line is formed, the base 144' and the side wall region 142 are sufficient. However, the P-type first well 110 and the P-type second well 120 are short-circuited without being overlapped.
[0008]
[Problems to be solved by the invention]
A technical problem to be solved by the present invention is to provide a triple well manufacturing method capable of manufacturing a triple well with improved electrical characteristics by a simplified process.
[0009]
[Means for Solving the Problems]
The triple well formed by the manufacturing method of the present invention for achieving the above technical problem includes a first conductivity type first well and a first conductivity type second well formed in a first conductivity type semiconductor substrate. A second well of the first conductivity type and a second well of the first conductivity type in order to separate the first well of the first conductivity type and the second well of the first conductivity type in order to separate the first well of the first conductivity type and the second well of the first conductivity type; The second well. The second conductivity type second well is connected to a side wall region extending from the surface of the substrate to a region having a first depth in the substrate and a lower end portion of the side wall region to be second from the substrate. And a base region formed horizontally in a region to be deep.
[0010]
According to one aspect of the present invention for manufacturing the triple well, the base region of the second well of the second conductivity type and the second well of the first conductivity type are formed using one mask pattern as an ion implantation mask. Use to form. Then, when forming the base region of the second conductivity type second well, the mask pattern is used as an ion implantation mask while the second conductivity type impurity forms an incident angle θ with the direction perpendicular to the semiconductor substrate. Impurities of the second conductivity type are implanted so as to be incident on the surface of the substrate so as to be inclined, and a base region of the second conductivity type second well is formed in a region wider than the region exposed by the mask pattern. Form.
[0011]
The incident angle θ is preferably 5 ° to 30 °. The mask pattern for defining the base region of the second conductivity type second well is formed to expose a semiconductor substrate region defined by the inner side wall of the side wall region of the second conductivity type second well. It is desirable.
[0012]
According to another aspect of the present invention for manufacturing the triple well, the sidewall region is formed by making the ion implantation energy for forming the sidewall region the same as or similar to the ion implantation energy for forming the base region. Forming the base region, the sidewall region and the base region are overlapped to completely separate the first conductivity type first well and the first conductivity type second well, The base region and the second well of the first conductivity type are formed using the same mask pattern as an ion implantation mask.
[0013]
The step of forming the sidewall region and the base region of the second conductivity type second well includes providing the first conductivity type semiconductor substrate and then forming the second conductivity type on the first conductivity type semiconductor substrate. A first mask pattern is formed to limit the sidewall region of the conductive type second well. Next, using the first mask pattern as an ion implantation mask, a second conductivity type impurity is implanted with a first energy. Subsequently, after removing the first mask pattern, a second mask pattern for defining the base region is formed on the semiconductor substrate. Finally, using the second mask pattern as an ion implantation mask, the second conductivity type impurity is implanted with a second energy that is the same as or similar to the first energy, and a second depth that is the same as or similar to the first depth. The base region is formed in the corresponding region.
[0014]
Preferably, before the step of removing the first mask pattern, a step of implanting a second conductivity type impurity with an energy larger than the first energy is performed using the first mask pattern as an ion implantation mask.
[0015]
According to another aspect of the present invention for manufacturing the triple well, after providing the first conductive type semiconductor substrate, the second conductive type is formed on the first conductive type semiconductor substrate. A mask pattern for limiting the base region of the second well is formed. Next, using the mask pattern as an ion implantation mask, a second conductivity type impurity is implanted to form a base region of the second conductivity type second well. Subsequently, a spacer is formed on the sidewall of the mask pattern, and then the first conductivity type impurity is implanted using the mask pattern and the spacer as an ion implantation mask to form the first conductivity type second well.
[0016]
The mask pattern exposes part or all of the sidewall region of the second conductivity type second well formed on the sidewall of the first conductivity type second well, and the spacer is exposed to the exposed second well. It is desirable to cover the sidewall region of the well.
[0017]
According to another aspect of the present invention for manufacturing the triple well, after providing the first conductive type semiconductor substrate, the first conductive type is formed on the first conductive type semiconductor substrate. A first mask pattern for defining the second well is formed. Next, using the first mask pattern as an ion implantation mask, a first conductivity type impurity is implanted to form the first conductivity type second well. Subsequently, the first mask pattern is reduced to form a second mask pattern that exposes a wider area than the area exposed by the first mask pattern. Finally, a second conductivity type impurity is implanted using the second mask pattern as an ion implantation mask so that a width larger than the first conductivity type second well is formed under the first conductivity type second well. A second well of the second conductivity type is formed.
[0018]
The second mask pattern may be formed to expose a part or all of a sidewall region of the second conductivity type second well formed on a sidewall of the first conductivity type second well. .
According to the present invention, a triple well having a complete structure can be formed by a simple process.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the exemplary embodiment disclosed below, but may be embodied in various different forms. The exemplary embodiment is merely intended to complete the disclosure of the present invention, and It is provided to fully inform those who have knowledge of the scope of the invention. In the accompanying drawings, various film and region thicknesses have been emphasized for clarity. The conductivity types displayed in the drawings are for illustration purposes, and are based on the case where the conductivity type of the substrate is P-type. However, the present invention can also be applied to the case where the conductivity type of the substrate is N-type. In this case, the conductivity type of the well also has a conductivity type opposite to that shown. In the drawings, the same reference numerals denote the same members.
[0020]
<Example 1>
Referring to FIG. 2, after a pad oxide film 205 is formed on a first conductive type, for example, a P-type semiconductor substrate 200 by a normal method, the first conductive type first well, for example, a P-type first well 210 is formed. A first mask pattern 210M is formed to limit the above. Next, the P-type first well 210 is formed by implanting P-type impurity ions 209 using the first mask pattern 210M as an ion implantation mask. Subsequently, the first mask pattern 210M is removed by a normal method.
[0021]
Referring to FIG. 3, the second conductive type first well, that is, the N-type first well and the second conductive type second well, that is, the entire surface of the semiconductor substrate 200 on which the P-type first well 210 is formed. Then, a second mask pattern 342M for defining the sidewall region of the N-type second well is formed. Next, N-type impurity ions 341 are implanted using the second mask pattern 342M as an ion implantation mask, and the N-type first well 330 is formed in the peripheral circuit region, and the N-type second well sidewall is formed in the memory cell array region. Region 342 is formed. Subsequently, the second mask pattern 342M is removed by a normal method.
[0022]
Referring to FIG. 4, a third mask pattern 444 </ b> M that defines the base region of the N-type second well is formed on the entire surface of the substrate 200. The third mask pattern 444M is preferably formed so as to expose a semiconductor substrate region limited by the inner sidewall of the sidewall region 342 of the N-type second well.
[0023]
Next, using the third mask pattern 444M as an ion implantation mask, the N-type impurity ions 443 are implanted so as to be inclined to form the base region 444 of the N-type second well, and the sidewall region 342 and the base region 444 are formed. The configured N-type second well 440 is completed.
[0024]
As a method of implanting the N-type impurity ions 443 so as to incline, when the semiconductor substrate 200 is loaded into an ion implantation apparatus (not shown), the incident angle θ is perpendicular to the incident direction of impurity ions and the direction perpendicular to the substrate 200. A method of loading so as to incline is used. Accordingly, the impurity ions are incident on the surface of the substrate 200 so as to be inclined while forming an incident angle θ with the direction perpendicular to the substrate 200.
[0025]
At this time, it is desirable that the incident angle θ be 5 ° to 30 °. The incident angle is determined by a width W1 where the base region 444 and the side wall region 342 overlap each other and an incident range value (Projected Range: distance from the substrate surface to the highest impurity concentration point, hereinafter Rp) of impurity ions.
[0026]
That is, the incident angle (tilt angle) θ can be calculated by the following formula 1.
sin θ = W1Rp Equation 1
In the above equation, θ is an inclination angle, W1 is a width in which the base region 444 and the sidewall region 342 overlap, and Rp is an incident range value of impurity ions.
[0027]
The appropriate Rp of the triple well manufactured according to the present invention is 1 to 1.8 μm, and the appropriate overlap width W1 is 0.2 to 0.8 μm. Therefore, if this is substituted into Equation 1 and calculated, it can be seen that it is desirable to implant the impurities so that θ is 5 ° to 30 °.
[0028]
As described above, in this embodiment, the N-type impurity 443 is ion-implanted so that the N-type impurity 443 is inclined, so that the base region 444 of the N-type second well is further expanded on both sides from the region exposed by the third mask pattern 444M. Can be formed. Accordingly, the width W1 of the base region 444 of the N-type second well overlapping the sidewall region 342 of the N-type second well is increased, and the P-type second well formed in a subsequent process with the P-type first well 210. (See 520 in FIG. 5) is completely electrically separated to prevent the two wells from being short-circuited, so that different voltages can be applied to the two wells 210 and 520.
[0029]
Referring to FIG. 5, the third mask pattern 444M defining the base region 444 of the N-type second well is used as it is as an ion implantation mask, and P-type impurity ions 519 are implanted to form the P-type second well 520. Form.
[0030]
As described above, when the triple well structure is formed according to the present embodiment, the width W1 in which the base region 444 and the sidewall region 342 of the N-type second well overlap can be maximized. Therefore, the P-type first well 210 and the P-type second well 520 can be prevented from being short-circuited and can be completely separated electrically. Further, the base region 444 of the N-type second well and the P-type second well 520 can be formed using one mask pattern 444M.
[0031]
That is, the mask pattern forming process, which is complicated and has a great influence on the production cost, for example, the photoresist pattern forming process can be reduced, so that the process can be simplified and the production cost can be reduced.
[0032]
In this embodiment, the P-type first well 210, the N-type first well 230, and the N-type second well sidewall region 342 are formed in advance, and then the N-type second well base region 444 and the P-type second well 520 are formed. However, it is needless to say that the manufacturing order can be changed. That is, after the base region 444 of the N-type second well and the P-type second well 520 are formed, the P-type first well 210, the N-type first well 230, and the sidewall region 342 of the N-type first well are formed. You can also. Then, the base region 444 of the N-type second well can be formed by forming the P-type second well 520 first.
[0033]
<Example 2>
Referring to FIG. 6, a first mask pattern 642M that defines sidewall regions of the N-type first well and the N-type second well on the pad oxide film 605 of the semiconductor substrate 600 where the P-type first well 610 is formed. Form. Using the first mask pattern 642M as an ion implantation mask, N-type impurity ions 641 are implanted at 0.2 to 1.0 MeV, and the sidewalls of the N-type first well 630 'and the N-type second well having a depth of D1 are used. Region 642 'is formed.
[0034]
Next, as shown in FIG. 7, the first mask pattern 642M is used as it is as an ion implantation mask, the ion implantation energy is changed to 1.0 to 1.8 MeV, and N-type impurity ions 741 are implanted to obtain a depth. Forms a D2 N-type first well 730 'and an N-type second well sidewall region 742'. Accordingly, the sidewalls of the N-type first well 730 composed of the N-type first well 630 'having a depth of D1, the N-type first well 730' having a depth of D2, and the N-type second well having a depth of D1. A sidewall region 742 of the N-type second well composed of the region 642 ′ and the sidewall region 742 ′ of the N-type second well having a depth of D2 is completed. Subsequently, the first mask pattern 642M is removed by a normal method.
[0035]
Referring to FIG. 8, a second mask pattern 844M that defines the base region of the N-type second well is formed on the pad oxide film 605. Next, using the second mask pattern 844M as an ion implantation mask, an N-type impurity 843 is implanted with an ion implantation energy of 1.0 to 1.8 MeV to form a base region 844 of the N-type second well.
[0036]
Therefore, since the maximum Rp of the sidewall region 742 of the N-type second well and the maximum Rp value of the base region 844 are the same, the sidewall region 742 and the base region 844 are sufficiently overlapped as shown in FIG. Complete N-type second well 840 can be completed.
[0037]
Referring to FIG. 9, the second mask pattern 844M is directly used as an ion implantation mask, and P-type impurity ions 919 are implanted at 100 to 500 MeV to form a P-type second well 920.
[0038]
In the second embodiment, the sidewall region 742 of the N-type second well is formed through two ion implantation steps. In particular, the impurity ion implantation energy for forming the base region 844 of the N-type second well and the ion implantation energy for forming the sidewall region 742 of the N-type second well at the maximum depth D2 are made the same or similar. Accordingly, the base region 844 and the sidewall region 742 are sufficiently overlapped in the vertical direction so that a complete N-type second well 840 can be formed.
[0039]
In addition, since the N-type second well base region 844 and the P-type second well 920 are limited to one mask pattern 844M, the process is simplified.
The reason why the ion implantation process is performed twice with different ion implantation energies in order to form the sidewall region 742 of the N-type second well in the present embodiment is as follows.
[0040]
When D2, which is the depth at which the base region 844 of the N-type second well is formed, is large, that is, when the ion implantation energy for forming the base region 844 is large, the ion implantation energy for forming the base region 844 If the sidewall region 742 is formed by ion implantation only once with the same or similar energy, the sidewall region is not continuously connected from the surface of the substrate to the depth D2 and is separated from the surface of the substrate so that the depth becomes D2. This is to prevent the case where it is formed only in the vicinity of the region.
[0041]
Accordingly, the first conductivity type first well 610 and the second well 920 can be completely separated by sufficiently overlapping the side wall region 742 and the base region 844 in the vertical direction, and the side wall can be formed by one ion implantation process. As long as the region 742 can be extended from the surface of the substrate to the depth at which the base region 844 is formed (eg, D2), the ion implantation energy is the same as or similar to the ion implantation energy for forming the base region 844. More preferably, the sidewall region 742 is formed by performing one ion implantation step.
Of course, the number of ion implantation steps can be increased to two or more as required.
[0042]
<Example 3>
Referring to FIG. 10, the P-type first well 610, the N-type first well 730, and the N-type second well are processed through the same process as shown in FIGS. 6 to 7 of the second embodiment. Sidewall regions 742 are formed. Next, a mask pattern 1044M for defining the base region of the N-type second well is formed on the pad oxide film 605. Subsequently, using the mask pattern 1044M as an ion implantation mask, N-type impurity ions 1043 are implanted so as to enter the substrate 700 at an angle of θ. As a result, a base region 1044 that overlaps not only in the vertical direction but also in the horizontal direction with the sidewall region 742 is formed to complete the N-type second well 1040.
[0043]
Referring to FIG. 11, a P-type second well 1120 is formed by implanting P-type impurity ions 1119 using the mask pattern 1044M that defines the base region 1044 of the N-type second well as it is.
[0044]
According to this embodiment, the sidewall region 742 of the N-type second well is formed by ion implantation twice or more with different ion implantation energies, and the base region 1044 is formed by implanting impurity ions so as to be inclined. In addition, since the side wall region 742 and the base region 1044 overlap each other over a wide region in the vertical direction and the horizontal direction, the P-type first well 610 and the P-type second well 1120 can be electrically isolated completely. .
[0045]
Further, as in the first and second embodiments, the N-type second well base region 1044 and the P-type second well 1120 are simultaneously formed with one mask pattern 1044M, thereby simplifying the manufacturing process and reducing the production cost. Of course, you can save.
[0046]
<Example 4>
Referring to FIG. 12, an N-type second well is formed on a semiconductor substrate 1200 having a pad oxide film 1205, a P-type first well 1210, an N-type first well 1230, and a sidewall region 1242 of the N-type second well. A mask pattern 1244M for limiting the base region, for example, a photoresist pattern is formed. Next, using the mask pattern 1244M as an ion implantation mask, N-type impurity ions 1243 are implanted to form the base region 1244 of the N-type second well.
[0047]
At this time, the mask pattern 1244M is formed so as to expose part or all of the sidewall region 1242 formed in the semiconductor substrate 1200 at a predetermined depth so that the base region 1244 sufficiently overlaps with the sidewall region 1242. To. As a result, an N-type second well 1240 composed of the side wall region 1242 and the base region 1244 is completed.
[0048]
Next, when the mask pattern 1244M is formed of a photoresist pattern, a bake process is performed to improve the adhesion between the photoresist pattern 1244M and the semiconductor substrate 1200. The baking process for the photoresist pattern 1244M is preferably performed at about 180 to 230 ° C., and preferably at about 200 ° C. This is because if the baking process is performed at a very high temperature, the photoresist pattern 1244M may be deformed.
Subsequently, a spacer formation insulating film (not shown) is formed on the entire surface of the semiconductor substrate 1200 on which the mask pattern 1244M is formed.
[0049]
It is desirable to use an oxide film as the insulating film. When the mask pattern 1244M is formed into a photoresist pattern, padding that shrinks the photoresist pattern occurs when the oxide film is formed at a high temperature. Therefore, it is desirable to form the oxide film at a low temperature. Therefore, it is desirable to use a plasma chemical vapor deposition method that can form an oxide film at a low temperature, and the deposition temperature is preferably set to 180 to 250 ° C.
[0050]
Subsequently, anisotropic etching is performed on the entire surface of the semiconductor substrate on which the insulating film is formed, thereby forming a spacer 1320S having a constant width W2 on the side wall of the mask pattern 1244M as shown in FIG. To do.
[0051]
At this time, the width W2 of the oxide film spacer 1320S depends on the thickness of the mask pattern 1244M and the exposed width d of the semiconductor substrate 1200 from which the mask pattern 1244M is exposed. For example, when the thickness of the mask pattern 1244M is 4500 mm and the distance of the semiconductor substrate exposed by the mask pattern 1244M is several hundred μm, the thickness of the oxide film formed on the mask pattern 1244M is about 1000 to 4000 mm. It is desirable to do. If the oxide film formed to a thickness of 1000 to 4000 mm is anisotropically etched, an oxide film spacer 1320S having a width W2 of 1000 to 4000 mm can be formed on the sidewall of the mask pattern 1244M.
[0052]
The width W2 of the oxide film spacer 1320S formed at this time is large enough to block the entire sidewall region 1242 of the N-type second well exposed by the mask pattern 1244M and expose only the semiconductor substrate 1200 region in the sidewall region 1242. Of course, it should be formed.
[0053]
Subsequently, a P-type second well 1320 is formed by implanting P-type impurity ions 1319 using the mask pattern 1244M and the spacer 1320S as an ion implantation mask.
[0054]
According to the present embodiment, the width W1 in which the sidewall region 1242 of the N-type well and the base region 1244 overlap can be automatically determined by the width W2 of the oxide film spacer 1320S.
[0055]
In other words, after forming a mask pattern 1244M for exposing the sidewall region 1242 of the N-type second well having a width W2 capable of forming the oxide film spacer 1320S, an N-type impurity is implanted to form the sidewall region of the N-type second well. The base region 1244 of the N-type second well that overlaps with the constant width W1 by 1242 can be formed.
[0056]
Further, the P-type second well 1320 can be formed only in the N-type second well 1240 by forming the oxide film spacer 1320S by the self-alignment method. Therefore, a short circuit between the P-type first well 1210 and the P-type second well 1320 can be effectively prevented.
[0057]
In addition, since the base region 1244 of the N-type second well and the P-type second well 1320 can be formed at the same time by using only one mask pattern 1244M as in the first to third embodiments, the manufacturing process is increased. Simplify and reduce production costs.
[0058]
<Fifth embodiment>
Referring to FIG. 14, a pad oxide film 1405 is formed on the entire surface, and is formed on a semiconductor substrate 1400 where a P-type first well 1410, an N-type first well 1430, and an N-type second well sidewall region 1442 are formed. A first mask pattern 1420M is formed to expose a region where the P-type second well 1420 is to be formed. Preferably, the first mask pattern 1420M is formed to block all the sidewall region 1442 of the N-type second well.
[0059]
Subsequently, using the first mask pattern 1420M as an ion implantation mask, P-type impurity ions 1419 are implanted to form a P-type second well 1420 in the semiconductor substrate 1400 defined by the sidewall region 1424 of the N-type second well. Form.
[0060]
Referring to FIG. 15, after the P-type second well 1420 is formed, a process of reducing the first mask pattern 1420M is performed. When the first mask pattern 1420M is formed of a photoresist pattern, isotropic etching is performed on the photoresist pattern 1420M to reduce the size of the photoresist pattern. Isotropic etching is carried out using a normal plasma etching method or using a normal descum equipment.
[0061]
That is, the original first mask pattern 1420M indicated by the dotted line is reduced so that the second mask pattern 1544M indicated by the solid line is obtained. The second mask pattern 1544M defines the base region of the N-type second well. The second mask pattern 1544M is formed to expose part or all of the sidewall region 1442 of the N-type second well.
[0062]
When the first mask pattern 1420M is the first photoresist pattern and is reduced to form the second mask pattern 1544M, that is, the second photoresist pattern, the thickness of the second photoresist pattern is approximately 2500 mm or more. Adjust the process conditions so that This is because the second photoresist pattern can sufficiently perform the role as an ion implantation mask.
[0063]
Subsequently, using the second mask pattern 1544M as an ion implantation mask, N-type impurity ions 1543 are implanted to form an N-type second well base region 1544. As shown in FIG. 15, the reduced width W2 of the first mask pattern 1420M results in a width W1 where the base region 1544 of the N-type second well and the sidewall region 1542 of the N-type second well overlap each other. decide.
[0064]
That is, in this embodiment, after forming one mask pattern 1420M, the P-type second well 1420 is formed using the mask pattern 1420M, and then the size is reduced to have a width wider than that of the P-type second well 1420. An N-type second well base region 1544 is formed. Accordingly, the base region 1544 of the N-type second well and the sidewall region 1542 of the N-type second well are sufficiently overlapped to complete the N-type second well 1540. Therefore, the problem that a short circuit occurs between the P-type first well 1410 and the P-type second well 1420 can be effectively prevented by a simplified process.
[0065]
【The invention's effect】
According to the present invention, different voltages can be applied to the first and second wells of the first conductivity type by surrounding the second well of the first conductivity type and separating from the first well of the first conductivity type. The base region of the second well of the second conductivity type and the second well of the first conductivity type are formed using the same mask. In addition, the base region and the sidewall region of the second conductivity type second well are formed to be completely connected. Therefore, a triple well structure with improved characteristics can be effectively formed by a simplified process.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor memory device having a triple well structure to be manufactured according to the present invention.
FIG. 2 is a cross-sectional view of a manufacturing process intermediate structure for explaining a method of manufacturing a triple well according to a first embodiment of the present invention.
FIG. 3 is a cross-sectional view of a manufacturing process intermediate stage structure for explaining a method of manufacturing a triple well according to the first embodiment of the present invention.
FIG. 4 is a cross-sectional view of an intermediate stage structure for explaining a method of manufacturing a triple well according to a first embodiment of the present invention.
FIG. 5 is a cross-sectional view of a manufacturing process intermediate structure for explaining a method of manufacturing a triple well according to a first embodiment of the present invention.
FIG. 6 shows a cross-sectional view of an intermediate stage structure for explaining a method of manufacturing a triple well according to a second embodiment of the present invention.
FIG. 7 is a cross-sectional view of an intermediate structure of a manufacturing process for explaining a method of manufacturing a triple well according to a second embodiment of the present invention.
FIG. 8 is a cross-sectional view of a manufacturing process intermediate structure for explaining a method of manufacturing a triple well according to a second embodiment of the present invention.
FIG. 9 is a cross-sectional view of a manufacturing process intermediate structure for explaining a method of manufacturing a triple well according to a second embodiment of the present invention.
FIG. 10 is a cross-sectional view of a manufacturing process intermediate stage structure for explaining a method of manufacturing a triple well according to a third embodiment of the present invention.
FIG. 11 shows a cross-sectional view of an intermediate stage structure for explaining a method of manufacturing a triple well according to a third embodiment of the present invention.
FIG. 12 is a cross-sectional view of an intermediate stage structure for explaining a method of manufacturing a triple well according to a fourth embodiment of the present invention.
FIG. 13 is a cross-sectional view of a manufacturing process intermediate stage structure for explaining a method of manufacturing a triple well according to a fourth embodiment of the present invention.
FIG. 14 is a cross-sectional view of a manufacturing process intermediate structure for explaining a method of manufacturing a triple well according to a fifth embodiment of the present invention.
FIG. 15 shows a cross-sectional view of an intermediate stage structure for explaining a method of manufacturing a triple well according to a fifth embodiment of the present invention.
[Explanation of symbols]
100 P-type substrate
110 P-type first well
112, 122, 138 N-type impurity region
114, 124 Gate oxide film
116, 126, 136 gates
118, 128 P-type impurity region
120 P type second well
130 N-type first well
132 P-type impurity region
134 Gate oxide film
140 N-type second well
142 Side wall region
144 Base area
144 'base

Claims

A first conductivity type first well, a first conductivity type second well, a second conductivity type first well, and the first conductivity type first well formed in the first conductivity type semiconductor substrate; In order to separate the second well of the first conductivity type, a second well of the second conductivity type surrounding the second well of the first conductivity type is formed, and the second well of the second conductivity type is a surface of the substrate To a region having a first depth in the substrate, and a base region connected to the lower end of the sidewall region and formed in a region having a second depth from the substrate. In a method for manufacturing a triple well of a semiconductor device,
Providing a semiconductor substrate of the first conductivity type;
Forming a first mask pattern defining a sidewall region of the second conductivity type second well and the second conductivity type first well on the semiconductor substrate;
Using the first mask pattern as an ion implantation mask, a second conductivity type impurity is implanted into the substrate to form a sidewall region of the second conductivity type second well and the second conductivity type first well. And the stage of
Forming a second mask pattern for defining a base region of the second conductivity type second well on the semiconductor substrate;
Using the second mask pattern as an ion implantation mask, a second conductivity type impurity is incident on the surface of the substrate at an angle of incidence θ with respect to a direction perpendicular to the semiconductor substrate. Implanting impurities into the region deeper than the region exposed by the second mask pattern at the second depth to form a base region of the second conductivity type second well;
Using the second mask pattern as an ion implantation mask and implanting a first conductivity type impurity to form a second well of the first conductivity type in a region exposed by the second mask pattern;
A method for manufacturing a triple well of a semiconductor memory device.

2. The method of manufacturing a triple well of a semiconductor memory device according to claim 1, wherein the incident angle [theta] is 5 [deg.] To 30 [deg.].

A first conductivity type first well, a first conductivity type second well, a second conductivity type first well, and the first conductivity type first well formed in the first conductivity type semiconductor substrate; In order to separate the second well of the first conductivity type, a second well of the second conductivity type surrounding the second well of the first conductivity type is formed, and the second well of the second conductivity type is a surface of the substrate To a region having a first depth in the substrate, and a base region connected to the lower end of the sidewall region and formed in a region having a second depth from the substrate. In a method for manufacturing a semiconductor device triple well,
Providing a semiconductor substrate of the first conductivity type;
Forming a first mask pattern defining a sidewall region of the second conductivity type second well and the second conductivity type first well on the semiconductor substrate;
Using the first mask pattern as an ion implantation mask, a second conductivity type impurity is implanted into the substrate to form a sidewall region of the second conductivity type second well and the second conductivity type first well. And the stage of
Forming a second mask pattern for defining a base region of the second conductivity type second well on the first conductivity type semiconductor substrate;
The second with impurity of the second conductivity type using the mask pattern as an ion implantation mask is tilted with no angle of incidence θ and the direction perpendicular to the semiconductor substrate to be incident on the surface of the substrate, the second conductivity type in the impurity the second depth, the steps of the second injected into wider than the exposed area region by a mask pattern to form a base region of the second well of the second conductivity type,
Using the second mask pattern as an ion implantation mask and implanting a first conductivity type impurity to form a second well of the first conductivity type in a region exposed by the second mask pattern ; Including
The second well of the first conductivity type is a memory array region of a semiconductor memory device, a first well of the first well and the second conductive type of the first conductivity type disposed in the peripheral circuit region of the semiconductor element A method for producing a triple well of a semiconductor memory device, wherein the well is a well of a transistor.

4. The method as claimed in claim 3, wherein the incident angle [theta] is 5 [deg.] To 30 [deg.].

The second mask pattern to limit the base region of the second well of the second conductivity type, formed so as to expose the semiconductor substrate region defined by the inner walls of the sidewall regions of the second well of the second conductivity type The method for manufacturing a triple well of a semiconductor memory device according to claim 3, wherein:

A first conductivity type first well, a first conductivity type second well, a second conductivity type first well, and the first conductivity type first well formed in the first conductivity type semiconductor substrate; In order to separate the second well of the first conductivity type, a second well of the second conductivity type surrounding the second well of the first conductivity type is formed, and the second well of the second conductivity type is separated from the surface of the substrate. A semiconductor comprising a side wall region extending to a region having a first depth in the substrate and a base region connected to a lower end portion of the side wall region and formed in a region having a second depth from the substrate. In the manufacturing method of the triple well of the element,
And providing a semiconductor substrate before Symbol first conductivity type,
Forming a first mask pattern to limit both the said and the second conductive type second well side wall regions of the first conductivity type semiconductor substrate a second conductivity type first well of,
Using the first mask pattern as an ion implantation mask, a second conductivity type impurity is implanted with a first energy to extend from the surface of the substrate to a region having a first depth, and the second sidewall region and the second region Simultaneously forming a first well of conductivity type;
Removing the first mask pattern;
Forming a second mask pattern for defining a base region of the second conductivity type second well on the semiconductor substrate;
The second mask pattern is used as an ion implantation mask, and the second conductivity type impurity is implanted with a second energy that is the same as the first energy, to a region corresponding to the second depth that is the same as the first depth. Forming a base region of a second well of the second conductivity type ;
Using the second mask pattern as an ion implantation mask and implanting a first conductivity type impurity to form a second well of the first conductivity type in a region exposed by the second mask pattern; Including
Forming the base region of the second conductivity type second well,
Using the second mask pattern as an ion implantation mask, the second conductivity type impurity is incident on the surface of the substrate at an angle of incidence θ with respect to a direction perpendicular to the semiconductor substrate. In the step of forming a base region of the second well of the second conductivity type by implanting the impurity in a region wider than the region exposed by the second mask pattern at the second depth. A method for manufacturing a triple well of a memory device.

A first conductivity type first well, a first conductivity type second well, a second conductivity type first well, and the first conductivity type first well formed in the first conductivity type semiconductor substrate; In order to separate the second well of the first conductivity type, the second well of the second conductivity type surrounding the second well of the first conductivity type is formed, and the second well of the second conductivity type is the surface of the substrate To a region having a first depth in the substrate, and a base region connected to the lower end of the sidewall region and formed in a region having a second depth from the substrate. In a method for manufacturing a semiconductor device triple well,
Providing a semiconductor substrate of the first conductivity type;
Forming a first mask pattern on the first conductive type semiconductor substrate to limit both a sidewall region of the second conductive type second well and the second conductive type first well;
Using the first mask pattern as an ion implantation mask, a second conductivity type impurity is implanted to extend from the surface of the substrate to a region having a first depth, and the second conductivity type second impurity. Simultaneously forming one well;
Removing the first mask pattern;
Forming a second mask pattern for defining a base region of the second conductivity type second well on the first conductivity type semiconductor substrate;
Using the second mask pattern as an ion implantation mask and implanting a second conductivity type impurity to the second depth to form a base region of the second conductivity type second well;
Forming a spacer on a sidewall of the second mask pattern;
Forming a second well of the first conductivity type by implanting a first conductivity type impurity using the second mask pattern and the spacer as an ion implantation mask;
Method for producing the triple-well semi-conductor memory device which comprises a.

Forming the spacer comprises :
Forming an insulating film on the entire surface of the semiconductor substrate on which the base region of the second well of the second conductivity type is formed;
Method for producing the triple-well semiconductor memory device according to claim 7, characterized in that said made insulating film is anisotropically etched in the step of forming a spacer on sidewalls of the second mask pattern.

Forming the second mask pattern comprises:
Forming a photoresist film on the entire surface of the substrate and then patterning to form a photoresist pattern that defines a base region of the second well of the second conductivity type;
Before the step of forming the insulating film,
Further comprising baking the photoresist pattern;
The step of forming the insulating film includes:
9. The method of manufacturing a triple well of a semiconductor memory device according to claim 8 , wherein the method is a step of forming a low temperature oxide film .

The second mask pattern exposes part or all of a sidewall region of the second conductivity type second well formed on a side surface of the first conductivity type second well,
8. The method of claim 7 , wherein the spacer covers a sidewall region of the second conductivity type second well exposed by the second mask pattern .

A first conductivity type first well, a first conductivity type second well, a second conductivity type first well, and the first conductivity type first well formed in the first conductivity type semiconductor substrate; In order to separate the second well of the first conductivity type, a second well of the second conductivity type surrounding the second well of the first conductivity type is formed, and the second well of the second conductivity type is separated from the surface of the substrate. A semiconductor comprising a side wall region extending to a region having a first depth in the substrate and a base region connected to a lower end portion of the side wall region and formed in a region having a second depth from the substrate. In the manufacturing method of the triple well of the element,
Providing a semiconductor substrate of the first conductivity type;
Forming a first mask pattern on the first conductive type semiconductor substrate to limit both a sidewall region of the second conductive type second well and the second conductive type first well;
Using the first mask pattern as an ion implantation mask, a second conductivity type impurity is implanted with a first energy to extend from the surface of the substrate to a region having a first depth, and the second sidewall region and the second region Simultaneously forming a first well of conductivity type;
Removing the first mask pattern;
Forming a second mask pattern defining the second well of the first conductivity type on the semiconductor substrate of the first conductivity type;
Using the second mask pattern as an ion implantation mask and implanting a first conductivity type impurity to form the first conductivity type second well;
Reducing the second mask pattern to form a third mask pattern that exposes a wider area than the area exposed by the second mask pattern;
Using the third mask pattern as an ion implantation mask, a second conductivity type impurity is implanted to the second depth and below the first conductivity type second well from the first conductivity type second well. Forming a base region of the second well of the second conductivity type having a large width,
The first conductivity type second well is a memory array region of a semiconductor memory element, and the first conductivity type first well and the second conductivity type first well are disposed in a peripheral circuit region of the semiconductor element. method for producing the triple-well semi-conductor memory device which is a well of the transistor.

The forming of the first mask pattern,
A step of forming a first photoresist pattern exposing a region Pas tanning and second well of the first conductivity type is formed after forming a photoresist film on the entire surface of the semiconductor substrate,
Forming the second mask pattern comprises:
The method according to claim 11, wherein the second photoresist pattern is formed by isotropically etching the first photoresist pattern to expose a wider area than the area exposed by the first photoresist pattern. A triple well manufacturing method of the semiconductor memory device described.

The second mask pattern is to be formed so that exposes a part or all of the sidewall regions of the second well of the second conductivity type formed in the side wall of the second well of the first conductivity type The method for manufacturing a triple well of a semiconductor memory device according to claim 11 .