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JP4115556B2 - Manufacturing method of semiconductor package - Google Patents

Manufacturing method of semiconductor package Download PDF

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Publication number
JP4115556B2
JP4115556B2 JP15868897A JP15868897A JP4115556B2 JP 4115556 B2 JP4115556 B2 JP 4115556B2 JP 15868897 A JP15868897 A JP 15868897A JP 15868897 A JP15868897 A JP 15868897A JP 4115556 B2 JP4115556 B2 JP 4115556B2
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JP
Japan
Prior art keywords
chip
semiconductor package
manufacturing
cutting
package according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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JP15868897A
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Japanese (ja)
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JPH118329A (en
Inventor
芳弘 石田
潔 清水
哲夫 佐藤
進一 西方
修一 石綿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Holdings Co Ltd
Citizen Watch Co Ltd
Original Assignee
Citizen Holdings Co Ltd
Citizen Watch Co Ltd
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Priority to JP15868897A priority Critical patent/JP4115556B2/en
Application filed by Citizen Holdings Co Ltd, Citizen Watch Co Ltd filed Critical Citizen Holdings Co Ltd
Priority to EP08167595.1A priority patent/EP2015359B1/en
Priority to EP98917679.7A priority patent/EP0932198B1/en
Priority to PCT/JP1998/001905 priority patent/WO1998052220A1/en
Priority to CNB988005794A priority patent/CN1185702C/en
Priority to US09/194,735 priority patent/US6365438B1/en
Priority to KR1019997000071A priority patent/KR100568571B1/en
Priority to TW087106959A priority patent/TW395033B/en
Priority to MYPI98002064A priority patent/MY123937A/en
Publication of JPH118329A publication Critical patent/JPH118329A/en
Application granted granted Critical
Publication of JP4115556B2 publication Critical patent/JP4115556B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Dicing (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は半導体パッケージの製造方法に係わり、更に詳しくは多数個取りする半導体パッケージの製造方法に関するものである。
【０００２】
【従来の技術】
近年、半導体パッケージの小型化、高密度化に伴いベア・チップを直接フェイスダウンで、基板上に実装するフリップチップボンディングが開発されている。カメラ一体型ＶＴＲや携帯電話機等の登場により、ベア・チップと略同じ寸法の小型パッケージ、所謂ＣＳＰ（チップサイズ／スケール・パッケージ）を載せた携帯機器が相次いで登場してきている。最近ＣＳＰの開発は急速に進み、その市場要求が本格化している。
【０００３】
図７は、多数個取りし、高密度実装化した従来技術が特開平８−１５３８１９号公報に開示されている。以下図面に基づいてその概要を説明する。
【０００４】
図７において、短冊状の回路基板１にスルーホール２を形成後、銅メッキ層を施す工程と、全ての回路パターンと接続する共通電極１４を含む複数個、例えば２個のＢＧＡを構成する回路パターンを形成する回路パターン形成工程と、前記回路基板１の上下両面に感光性樹脂皮膜を施した後、エッチングにより、共通電極１４及びＩＣチップ、ボンディングワイヤ、半田バンプの各接続部を除くようにドライフイルムを形成するドライフイルムラミネート工程と、前記共通電極１４を利用して前記回路基板１の上下両面の露出している電極の銅メッキ層の表面に、Ｎｉ−Ａｕメッキ層を形成する。
【０００５】
次に、共通電極１４と回路パターンとを分離するパターン分離工程は、製品分離ライン１５の四辺に沿って、その四隅に回路基板１と連結する連結部１５ａを残すように、ルータ加工により長穴１６を穴明けする。その後、ワイヤーボンディング及びトランスファーモールドにより樹脂封止し、回路基板１の下面に半田バンプを形成する。
【０００６】
製品分離工程は、前記四隅に残した連結部は狭隘なため、プレス抜き等の切り離し手段で余分な負荷をかけることなく極めて容易に分離することにより、単個のＢＧＡを製造することができる。
【０００７】
しかしながら、前述した短冊状の複数個取りする半導体パッケージの製造方法は、単個の半導体パッケージの製造方法に比較して生産性は若干向上するが、小型パッケージであるＣＳＰにおいては、回路基板製造時の基板取り個数が少なく、生産コストが高くなる。また、前記ＣＳＰのように、前記回路基板の外縁から最外周に位置するボール電極の中心までの距離が差が無くなると、製品分離工程でプレス抜き等の切り離し手段で分離する時の金型押さえ代が無くなる等の問題があった。
【０００８】
そこで、小型携帯機器等に搭載するＣＳＰの従来の半導体パッケージの製造方法について以下その概要を説明する。
【０００９】
先ず図８（ａ）に示す多数個取りする回路基板形成工程は、両面銅張りされた集合回路基板１Ａにスルーホール（図示しない）を形成した後、無電解銅メッキ及び電解銅メッキにより銅メッキ層を形成し、更にメッキレジストをラミネートし、露光現像してパターンマスクを形成した後、エッチング液を用いてパターンエッチングを行うことにより、前記集合回路基板１Ａの上面側には複数個分配列したＩＣ接続用電極３、下面側にパッド電極である外部接続用電極４を形成する。次にソルダーレジスト処理を行い、所定の部分にレジスト膜を形成することにより、前記集合回路基板１Ａの下面側には外部接続用電極４を露呈するように、マトリックス状に多数の同一形状の半田付け可能な表面であるレジスト膜の開口部を形成し、多数個取りする集合回路基板１Ａが完成される。２はＸ、Ｙ方向に直交するカットラインである。
【００１０】
図８（ｂ）に示すＩＣチップ実装工程は、先ず、ＩＣウエハーをバンプ工程に流して前記ＩＣウエハーのパッド電極面に半田バンプ５を形成する。前記半田バンプ５の形成方法には、一般に、スタッドバンプ方式、ボールバンプ方式、及びメッキバンプ方式等があるが、その中で、パッド電極位置にレジストにて窓を形成し半田浴槽中に浸漬してメッキにて半田バンプを形成するメッキバンプ方式は、パッド電極間の狭い配列でバンプを形成することが可能で、ＩＣチップの小型化には有効な半田バンプの形成手段である。
【００１１】
前記半田バンプ５を形成後、前記ＩＣウエハーを粘着テープ等で貼着した状態で、所定のチップサイズにダイシングソー等の装置でウエハーの厚みをフルカット方式でＸ、Ｙ方向に切断した後、ＩＣチップ６を単体に分割する。
【００１２】
前記半田バンプ付きＩＣチップ６、又は前述した集合回路基板１Ａの前記配線バターンの所定位置にフラックスを塗布して、単体に分割した前記ＩＣチップ６を１個づつ複数個分配列した集合回路基板１Ａの個々の回路基板１上の所定位置に搭載した後、半田リフロー工程を経て、フリップチップ実装を行う。
【００１３】
図８（ｃ）に示す封止工程は、熱硬化性の封止樹脂７で前記隣接する複数個のＩＣチップ５に跨がった状態で、サイドポッティングにより一体的に樹脂封止することにより、ＩＣチップ６はフェイスダウンで集合回路基板１Ａの個々の回路基板１上に固定される。
【００１４】
図９（ａ）に示す基準部材張り付け工程は、ＩＣチップ６を実装した集合回路基板１Ａの平坦な底面を、基準部材８上に接着剤又は粘着テープ等の固定手段で張り付ける。張り付け面が互いに平坦なため、確実に固定される。
【００１５】
図９（ｂ）は、タイシング工程で、前述のＸ、Ｙ方向のカットライン２に沿って、ダイシングソー等の切削手段で単個に切削、分割した後、溶解液等により基準部材８より剥離する。
【００１６】
図９（ｃ）は、ボール電極を形成するボール形成工程は切削、分離された個々の回路基板１の下面側に形成された外部接続用電極４の位置に、半田ボールを配置してリフローすることによりボール電極９を形成する。以上の工程により単個のフリップチップＢＧＡ２０が完成される。
【００１７】
【発明が解決しようとする課題】
しかしながら、前述した半導体パッケージの製造方法には次のような問題点がある。即ち、半田ボール付けは、単個に切削、分割された回路基板毎に半田ボークを配置して行うもので、小型パッケージであるＣＳＰにおいては、回路基板の外縁から最外周に位置するボール電極の中心までの距離が無くなると、半田ボール付け時の治具スペースが取れなくなる。また、個々に半田ボール付けを行うので生産性が低く、コストアップ等の問題があった。
【００１８】
本発明は、上記従来の課題に鑑みなされたものであり、その目的は、小型携帯機器等に搭載する信頼性及び生産性に優れた、安価な半導体パッケージの製造方法を提供するものである。
【００１９】
【課題を解決するための手段】
上記目的を達成するために、本発明におけるＩＣチップを実装した半導体パッケージの製造方法は、基板の一方の面に前記ＩＣチップ実装用のボンディングパターンを、他方の面に外部接続用電極を形成するための電極パターンを集合回路基板面に複数個分配列して形成する回路基板形成工程と、前記ボンディングパターンと前記ＩＣチップを電気的接続するＩＣチップ実装工程と、該ＩＣチップを樹脂封止する封止工程とによりパッケージ集合体を形成し、該パッケージ集合体のＩＣチップ側を基準部材に固定する保持工程と、保持された前記パッケージ集合体の前記集合回路基板を切削して単個の完成半導体パッケージを形成する切削工程とからなることを特徴とするものである。
【００２０】
また、前記パッケージ集合体保持工程は、前記ＩＣチップの端面側を平坦化する平坦化工程と、平坦化された前記ＩＣチップ側を前記基準部材に固着する固定工程とからなることを特徴とするものである。
【００２１】
また、前記平坦化工程は、前記ＩＣチップの端面を切削して平坦化することを特徴とするものである。
【００２２】
また、前記平坦化工程は、封止面を切削して平坦化することを特徴とするものである。
【００２３】
また、前記平坦化工程は、ワイヤーボンディング実装したＩＣチップの切削面高さが、ワイヤーボンディング形状の最高点より高いことを特徴とするものである。
【００２４】
また、前記平坦化工程は、フリップチップ実装した前記ＩＣチップの切削面高さが、前記ＩＣチップの回路形成面より高いことを特徴とするものである。
【００２５】
また、前記平坦化工程は、前記ＩＣチップの端面に平板を固着したことを特徴とするものである。
【００２６】
また、前記平板は金属であることを特徴とするものである。
【００２７】
また、前記平坦化工程は、集合回路基板の外周部に枠を付け、封止樹脂を充填して平坦化したことを特徴とするものである。
【００２８】
また、前記ＩＣチップ側を基準部材に固定する保持工程は、接着剤で固着することを特徴とするものである。
【００２９】
また、前記保持工程は、ＩＣチップ側の平坦面を真空吸着したことを特徴とするものである。
【００３０】
また、前記切削工程は、ダイシングソーによる切削で行うことを特徴とするものである。
【００３１】
また、前記切削工程は、封止樹脂も同時に切削されることを特徴とするものである。
【００３２】
【発明の実施の形態】
以下図面に基づいて本発明における半導体パッケージの製造方法について説明する。図１及び図２は本発明の実施の形態で、多数個取りする半導体パッケージの製造工程を示す説明図である。従来技術と同一部材は同一符号で示す。
【００３３】
先ず、図１（ａ）の回路基板形成工程、図１（ｂ）のＩＣ実装工程、図１（ｃ）の樹脂封止工程は、前述の従来技術と同様であるので、説明は省略する。
【００３４】
図示しないボール電極を形成する半田ボール付け工程は、前記集合回路基板１Ａの個々の回路基板１の下面側に形成された外部接続用電極４の位置に、フリップチップの半田の融点より低い融点の半田ボールを配置してリフローすることにより、図１（ｃ）に示すような、突起電極であるボール電極９が形成される。ボール付け半田の組成は、フリップチップは、Ｐｂ：９０％、Ｓｎ：１０％、融点２５０℃で、ボール電極９は、Ｐｂ：４０％、Ｓｎ：６０％、融点１８０℃でそれぞれ融点の異なる半田が使用される。
【００３５】
図２（ａ）に示す基準部材張り付け工程は、後述するＩＣチップ側平坦化工程後に、ＩＣチップ側に形成した平坦面を基準部材８に接着剤、例えば、日東電工（株）製の熱剥離テープ「エレップホルダー感圧型ダイシングテープ、ＳＰＶ−２２４」等の固定手段により張りつけるか、後述すＩＣチップ側を樹脂で埋没させて平坦面を形成し、該平坦面を基準部材８に接着剤等の固定手段により張りつけるか、又は、封止面に平板を付けてフラット面出し後に基準部材８上に固定する。更に、ＩＣチップ側の平坦面を真空吸着して基準部材８上に固定する等の様々な固定手段で行う。上記のように、接着剤等で固定するため、治具等による押さえ代が不要となり、その分基板の取り個数が多くなり多数個取り生産に有利である。ＩＣ面に多少接着剤が残ってもＩＣの性能には影響しない。
【００３６】
図２（ｂ）はタイシング工程で、前述のＸ、Ｙ方向のカットライン２に沿って、ダイシングソー、例えば、ディスコ製のダイシング機「ＤＦＤ−６４０」、使用ブレード「ＮＢＣ−ＺＢ１０９０Ｓ３、０．１ｍｍ幅」等を使用した切削手段で単個に切削、分割した後、溶解液、例えば、日化精工（株）製のワックス「スカイワックス４１５」等を使用して基準部材８より剥離する。以上の工程により単個のフリップチップＢＧＡ１０が完成される。
【００３７】
図３（ａ）、（ｂ）は共に前述したＩＣチップの端面側の平坦化工程を示す。図３（ａ）は、フリップチップ実装したＩＣチップ６の端面をグラインディング等の切削手段で、切削面１１ａの高さがＩＣチップ６の回路形成面より高くなるように、ＩＣチップ６の端面及び封止樹脂７の上面を所定量切削することにより平坦面１１を形成するものである。
【００３８】
図３（ｂ）は、ワイヤーボンディング実装したＩＣチップ６の端面側をグラインディング等の切削手段で、切削面１１ａの高さがワイヤーボンディング形状の最高点より高くなるように、所定量封止樹脂７の上面を切削することにより平坦面１１を形成するものである。
【００３９】
図４（ａ）、（ｂ）は共に前述したＩＣチップ６の端面側の平坦化工程を示す。図４（ａ）は、トランスファーモールドで封止樹脂７によりフラットな端面部を面出して、平坦面１１を形成するものである。図４（ｂ）は、集合回路基板１Ａの外周部を囲むように、金属又はプラスチック部材等よりなる枠部材１２を載せて、ＩＣチップ６側が埋没するように封止樹脂７を充填して、平坦面１１を形成するものである。図４（ａ）、（ｂ）は共に封止樹脂７で平坦面１１を形成するので、端面部を切削する必要はない。
【００４０】
図５は、フリップチップ実装したＩＣチップ６の端面に平板を固着した平坦化工程を示す。図において、ＩＣチップ６の端面に固着する平板１３は、熱伝導性のよい薄い金属、例えば、アルミ板、銅板、Ｃｕ−Ｗ系よりなる金属板等の放熱板で、前記平板１３はフラットの面出しと同時に、熱の放散を兼ねているものである。
【００４１】
前記基準部材８への固定工程は、紫外線反応型樹脂で固着してもよい。ＵＶテープ、例えば、日東電工（株）製のＵＶテープ「ＵＥ−２０９１Ｊ」等を使用する。前記ＵＶテープは両面接着剤のように使用して接着する。剥がす前にＵＶを照射すると接着力が極端に低下するので剥がすのが容易である。
【００４２】
また、基準部材８への固定工程は、熱反応型樹脂で固着してもよい。
【００４３】
また、基準部材８への固定工程は、溶剤反応型樹脂で固着してもよい。
【００４４】
また、基準部材８への固定工程は、前述したようにＩＣチップ６側の平坦面を真空吸着孔を有するチャックテーブル等で真空吸着してもよい。真空吸着しながら、前述のタイシング装置にセットして、直交するＸ、Ｙ方向にカットライン２に沿ってメタルブレードで切断、分離する。
【００４５】
切断工程は、図４（ａ）、（ｂ）に示すように、封止樹脂７も同時に切削することにより、半導体パッケージの外形形状が均一化され、綺麗に出来上がり商品価値を上げることが可能である。
【００４６】
図６は、電解メッキ法によって、回路基板上に複数個分のＣＳＰ用等の回路パターンを形成した集合回路基板１Ａを示す平面図である。この集合回路基板１Ａは、Ｘ方向に延在する２本の共通電極１４を有し、更に、共通電極１４に接続してＹ方向に延在する複数本の共通電極１４ａを有している。Ｙ方向に延在する複数本の共通電極１４ａは、それぞれ両側にＣＳＰ用の製品の回路パターン１４ｃに連なる枝状の配線パターン１４ｂが形成されている。
【００４７】
この集合回路基板１Ａに対しては、前述の実施の形態で説明した工程と同様な手順でＩＣチップの実装、封止、半田ボール付け等を行い、そして基準部材にＩＣチップ側のフラット面を固定する。その後切削工程を行う場合に、電解メッキ法による回路基板では、共通電極から個々の配線パターンを切り離すように切断する必要があるので、図に示すＸ方向の切削手順としては、通常のＡ、Ｂ、Ｃ・・Ｊ、Ｋと行うところだが、Ｙ方向の共通電極１４ｂ部分の切断間隔（Ｂ−Ｃ、Ｅ−Ｆ・・Ｉ−Ｊの間隔）は、他の部分の間隔に比較して狭く、連続して切断すると、図２（ｂ）、図５のように、隣接するＩＣチップ６間が封止樹脂７で埋まっていないような場合は、基準部材８に対する固着力が弱いので、切削中に回路基板が変形したり、切削ラインがずれたりする等の問題があった。
【００４８】
そこで、本実施形態によれば、Ｘ方向の切削手順をＡ、Ｂ、Ｄ、Ｅ、Ｇ、Ｈ、Ｉ、Ｋ、Ｃ、Ｆ、Ｊと行うことにより、切削間隔の狭い共通電極部分を連続切削しないので、回路基板に変形、切削ラインのずれ等の問題が生ぜずに切削できるものである。
【００４９】
以上、回路基板の他方の面に形成した外部接続用電極に、突起電極として半田バンプを形成した半導体パッケージの製造方法について説明したが、マザーボード側に半田バンプを形成することにより、回路基板側に半田バンプを形成せずに外部接続用電極のパット面を直接マザーボード側の半田バンプに接続しても良いことは言うまでもない。
【００５０】
【発明の効果】
以上説明したように、本発明の半導体パッケージの製造方法によれば、前記集合回路基板の上面側に複数個分配列して回路基板にＩＣチップを実装し、ＩＣチップを樹脂封止して、下面側の外部接続用電極に半田ボールを形成後、ＩＣチップ側を基準部材に固定した後、切削して単個の半導体パッケージを製造することにより、従来のように切断した個々の回路基板に半田ボール付けを行うことがない。小型携帯機器等に搭載する多数個取りに適し、生産性、信頼性に優れた安価な半導体パッケージの製造方法を提供することが可能である。
【図面の簡単な説明】
【図１】本発明の実施の形態に係わる半導体パッケージの製造工程で、回路基板形成工程、ＩＣ実装工程、樹脂封止工程を示す説明図である。
【図２】図１の製造工程後の基準部材張り付け工程、ダイシング工程を示す説明図である。
【図３】ＩＣチップ側端面及び樹脂面を切削により平坦面を形成する平坦化工程を示す断面図である。図である。
【図４】封止樹脂によりＩＣチップ側に平坦面を形成する平坦化工程を示す断面図である。
【図５】放熱板兼用の平板をＩＣチップ側に固着して平坦面を形成する平坦化工程を示す断面図である。
【図６】電解メッキ法によって回路基板上に複数個の回路パターンを形成した集合回路基板を示す平面図である。
【図７】従来の短冊状のＢＧＡの平面図である。
【図８】従来のＢＧＡの製造工程で、回路基板形成工程、ＩＣ実装工程、樹脂封止工程を示す説明図である。
【図９】従来のＢＧＡの製造工程で、図８の製造工程後の基準部材張り付け工程、ダイシング工程、ボール付け工程を示す説明図である。
【符号の説明】
１ 回路基板
１Ａ 集合回路基板
２ カットライン
３ ＩＣ接続用電極
４ 外部接続用電極
５ 半田ボール
６ ＩＣチップ
７ 封止樹脂
８ 基準部材
９ ボール電極（突起電極）
１０ フリップチップＢＧＡ
１１ 平坦面
１１ａ 切削面
１２ 枠部材
１３ 平板
１４ 共通電極[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor package, and more particularly to a method for manufacturing a semiconductor package in which a plurality of semiconductor packages are obtained.
[0002]
[Prior art]
2. Description of the Related Art In recent years, flip chip bonding has been developed in which a bare chip is directly mounted face-down on a substrate as semiconductor packages become smaller and higher in density. With the advent of camera-integrated VTRs, mobile phones, and the like, mobile devices on which small packages of approximately the same dimensions as bare chips, so-called CSP (chip size / scale packages), have appeared one after another. Recently, the development of CSP is progressing rapidly, and the market demand is in full swing.
[0003]
FIG. 7 shows a conventional technique in which a large number of parts are taken and high-density mounting is disclosed in Japanese Patent Laid-Open No. 8-1553819. The outline will be described below with reference to the drawings.
[0004]
In FIG. 7, after forming the through hole 2 in the strip-shaped circuit board 1, a step of applying a copper plating layer, and a circuit constituting a plurality of, for example, two BGAs including a common electrode 14 connected to all circuit patterns A circuit pattern forming process for forming a pattern, and after applying a photosensitive resin film on both the upper and lower surfaces of the circuit board 1, the common electrode 14 and the connecting portions of the IC chip, bonding wires, and solder bumps are removed by etching. A Ni-Au plating layer is formed on the surface of the exposed copper plating layer of the upper and lower surfaces of the circuit board 1 by using the common electrode 14 and a dry film laminating process for forming a dry film.
[0005]
Next, in the pattern separation process for separating the common electrode 14 and the circuit pattern, a long hole is formed by router processing so that the connection portions 15a connected to the circuit board 1 are left at the four corners along the four sides of the product separation line 15. 16 is drilled. Thereafter, resin sealing is performed by wire bonding and transfer molding, and solder bumps are formed on the lower surface of the circuit board 1.
[0006]
In the product separation process, since the connecting portions left at the four corners are narrow, a single BGA can be manufactured by separating very easily without applying an extra load by a separating means such as press punching.
[0007]
However, although the above-described method for manufacturing a plurality of strip-shaped semiconductor packages is slightly improved in productivity as compared to a method for manufacturing a single semiconductor package, in a CSP which is a small package, a circuit board is manufactured. This reduces the number of substrates that can be produced and increases the production cost. Further, as in the case of the CSP, when there is no difference in the distance from the outer edge of the circuit board to the center of the ball electrode located on the outermost periphery, the mold holder when separating by a separating means such as press punching in the product separation process. There was a problem such as a lack of money.
[0008]
Therefore, an outline of a method for manufacturing a conventional semiconductor package of a CSP mounted on a small portable device or the like will be described below.
[0009]
First, in the circuit board forming step for taking a large number of pieces shown in FIG. 8 (a), through holes (not shown) are formed in the collective circuit board 1A that is copper-coated on both sides, and then copper plating is performed by electroless copper plating and electrolytic copper plating. After forming a layer, laminating a plating resist, exposing and developing to form a pattern mask, pattern etching is performed using an etching solution, and a plurality of layers are arranged on the upper surface side of the collective circuit board 1A. The IC connection electrode 3 and the external connection electrode 4 which is a pad electrode are formed on the lower surface side. Next, a solder resist treatment is performed to form a resist film on a predetermined portion, so that the external connection electrodes 4 are exposed on the lower surface side of the collective circuit board 1A. An opening portion of a resist film, which is an attachable surface, is formed, and a collective circuit board 1A in which a large number are taken is completed. Reference numeral 2 denotes a cut line orthogonal to the X and Y directions.
[0010]
In the IC chip mounting process shown in FIG. 8B, first, the IC wafer is poured into a bump process to form solder bumps 5 on the pad electrode surface of the IC wafer. The solder bumps 5 are generally formed by a stud bump method, a ball bump method, a plated bump method, etc., in which a window is formed with a resist at the pad electrode position and immersed in a solder bath. The plating bump method of forming solder bumps by plating can form bumps with a narrow arrangement between pad electrodes, and is an effective means for forming solder bumps for miniaturization of IC chips.
[0011]
After forming the solder bumps 5, with the IC wafer attached with an adhesive tape or the like, the wafer thickness is cut in the X and Y directions by a full-cut method with a device such as a dicing saw to a predetermined chip size, The IC chip 6 is divided into single pieces.
[0012]
The integrated circuit board 1A in which the IC chips 6 with solder bumps or the integrated circuit board 1A described above are coated with a flux at a predetermined position on the wiring pattern and divided into a plurality of IC chips 6 divided into single pieces. After mounting at a predetermined position on each of the circuit boards 1, flip chip mounting is performed through a solder reflow process.
[0013]
In the sealing step shown in FIG. 8C, the resin is integrally sealed by side potting while straddling the plurality of adjacent IC chips 5 with the thermosetting sealing resin 7. The IC chip 6 is fixed face-down on each circuit board 1 of the collective circuit board 1A.
[0014]
In the reference member attaching step shown in FIG. 9A, the flat bottom surface of the collective circuit board 1A on which the IC chip 6 is mounted is attached onto the reference member 8 by a fixing means such as an adhesive or an adhesive tape. Since the pasting surfaces are flat with each other, they are securely fixed.
[0015]
FIG. 9 (b) shows a tiling process in which a cutting means such as a dicing saw or the like is cut and divided along the above-mentioned cut line 2 in the X and Y directions, and then peeled off from the reference member 8 by a solution or the like. To do.
[0016]
FIG. 9C shows a ball forming process for forming a ball electrode. A solder ball is arranged at the position of the external connection electrode 4 formed on the lower surface side of each circuit board 1 which has been cut and separated, and reflowed. Thereby, the ball electrode 9 is formed. A single flip chip BGA 20 is completed through the above steps.
[0017]
[Problems to be solved by the invention]
However, the semiconductor package manufacturing method described above has the following problems. That is, the solder ball attachment is performed by arranging a solder boke for each circuit board that is cut and divided into pieces. In a CSP that is a small package, the ball electrode located on the outermost periphery from the outer edge of the circuit board is used. If the distance to the center is lost, the jig space for solder ball attachment cannot be taken. In addition, since solder balls are individually attached, productivity is low and there is a problem of cost increase.
[0018]
The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide an inexpensive method for manufacturing a semiconductor package which is excellent in reliability and productivity mounted on a small portable device or the like.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, in the method of manufacturing a semiconductor package mounted with an IC chip according to the present invention, the bonding pattern for mounting the IC chip is formed on one surface of the substrate, and the electrode for external connection is formed on the other surface. Forming a plurality of electrode patterns on the surface of the collective circuit board, forming an IC chip electrically connecting the bonding pattern and the IC chip, and sealing the IC chip with resin forming a package assembly by the sealing step, a holding step of fixing the IC chip side of the package assembly to the reference member, cutting to single pieces of completing the set circuit board of the package assemblies are held And a cutting process for forming a semiconductor package.
[0020]
Also, the package assembly holding step, characterized in that consists of a flattening step of flattening the end surface of the IC chip, a fixing step of fixing the flattened said IC chip side to the reference member Is.
[0021]
Further, the planarization process is characterized in that the flattening and cutting the end surface of the IC chip.
[0022]
In the planarization step, the sealing surface is cut and planarized.
[0023]
The planarization step is characterized in that the height of the cut surface of the IC chip mounted by wire bonding is higher than the highest point of the wire bonding shape.
[0024]
Further, the planarization step, the cutting surface height of the IC chip is flip-chip mounting, and is characterized in that the above circuit formation surface of the IC chip.
[0025]
The flattening step is characterized in that a flat plate is fixed to the end face of the IC chip .
[0026]
The flat plate is a metal.
[0027]
Further, the planarization step is characterized in that a frame is attached to the outer peripheral portion of the collective circuit board, and the planarization process is performed by filling with a sealing resin.
[0028]
Further, the holding step of fixing the IC chip side to the reference member is fixed by an adhesive.
[0029]
The holding step is characterized in that the flat surface on the IC chip side is vacuum-sucked.
[0030]
The cutting step is performed by cutting with a dicing saw.
[0031]
In the cutting step, the sealing resin is also cut at the same time.
[0032]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a method for manufacturing a semiconductor package according to the present invention will be described with reference to the drawings. FIG. 1 and FIG. 2 are explanatory views showing a manufacturing process of a semiconductor package to be obtained in large numbers according to the embodiment of the present invention. The same members as those in the prior art are denoted by the same reference numerals.
[0033]
First, the circuit board forming process of FIG. 1A, the IC mounting process of FIG. 1B, and the resin sealing process of FIG.
[0034]
The solder ball forming step for forming a ball electrode (not shown) has a melting point lower than the melting point of the solder of the flip chip at the position of the external connection electrode 4 formed on the lower surface side of each circuit board 1 of the collective circuit board 1A. By disposing and reflowing the solder balls, ball electrodes 9 that are protruding electrodes as shown in FIG. 1C are formed. The composition of the ball solder is flip solder: Pb: 90%, Sn: 10%, melting point: 250 ° C., ball electrode 9: Pb: 40%, Sn: 60%, melting point: 180 ° C. Is used.
[0035]
In the reference member pasting step shown in FIG. 2 (a), after the later-described IC chip side flattening step, the flat surface formed on the IC chip side is bonded to the reference member 8 with an adhesive, for example, heat release made by Nitto Denko Corporation. Affixed with fixing means such as a tape “ELEP HOLDER pressure-sensitive dicing tape, SPV-224”, or the IC chip side described later is buried with resin to form a flat surface, and the flat surface is bonded to the reference member 8 with an adhesive, etc. Or by attaching a flat plate to the sealing surface and fixing the flat surface to the reference member 8. Further, the fixing is performed by various fixing means such as vacuum-suctioning the flat surface on the IC chip side and fixing it on the reference member 8. As described above, since it is fixed with an adhesive or the like, there is no need for a pressing margin by a jig or the like, and accordingly, the number of substrates to be taken increases, which is advantageous for multi-piece production. Even if some adhesive remains on the IC surface, the IC performance is not affected.
[0036]
FIG. 2 (b) is a tiling process, and along the above-mentioned cut line 2 in the X and Y directions, a dicing saw, for example, a disco dicing machine “DFD-640”, a blade used “NBC-ZB1090S3, 0.1 mm”. After cutting and dividing into single pieces by a cutting means using “width” or the like, it is peeled off from the reference member 8 using a solution, for example, wax “Sky Wax 415” manufactured by Nikka Seiko Co., Ltd. A single flip chip BGA 10 is completed through the above steps.
[0037]
FIGS. 3A and 3B both show the flattening process on the end face side of the IC chip described above. 3 (a) is an end face of the IC chip 6 is flip-chip mounted in a cutting means such as grinding, so that the height of the cutting surface 11a is higher than the circuit forming surface of IC chip 6, the end face of the IC chip 6 The flat surface 11 is formed by cutting a predetermined amount of the upper surface of the sealing resin 7.
[0038]
FIG. 3B shows a predetermined amount of sealing resin so that the cutting surface 11a is higher than the highest point of the wire bonding shape by cutting means such as grinding on the end surface side of the IC chip 6 mounted by wire bonding. The flat surface 11 is formed by cutting the upper surface of 7.
[0039]
FIGS. 4A and 4B show the planarization process on the end face side of the IC chip 6 described above. 4 (a) is out surface flat end surface portions with a sealing resin 7 by transfer molding, and forms a flat surface 11. In FIG. 4B, a frame member 12 made of a metal or a plastic member is placed so as to surround the outer peripheral portion of the collective circuit board 1A, and the sealing resin 7 is filled so that the IC chip 6 side is buried, The flat surface 11 is formed. FIG. 4 (a), the so to form a flat surface 11 at (b) are both sealing resin 7, it is not necessary to cut the end face portion.
[0040]
FIG. 5 shows a flattening process in which a flat plate is fixed to the end face of the IC chip 6 that is flip-chip mounted. In the figure, a flat plate 13 fixed to the end surface of the IC chip 6 is a heat radiating plate such as a thin metal having good thermal conductivity, for example, an aluminum plate, a copper plate, a metal plate made of Cu-W, and the flat plate 13 is a flat plate. At the same time as surface exposure, it also serves as heat dissipation.
[0041]
The fixing process to the reference member 8 may be fixed with an ultraviolet reactive resin. A UV tape such as a UV tape “UE-2091J” manufactured by Nitto Denko Corporation is used. The UV tape is bonded using a double-sided adhesive. If UV is irradiated before peeling, the adhesive strength is extremely reduced, so that it is easy to peel off.
[0042]
Further, the fixing process to the reference member 8 may be fixed with a heat-reactive resin.
[0043]
Further, the fixing process to the reference member 8 may be fixed with a solvent reaction type resin.
[0044]
Further, in the fixing process to the reference member 8, as described above, the flat surface on the IC chip 6 side may be vacuum-sucked with a chuck table having a vacuum suction hole or the like. While being vacuum-sucked, it is set in the above-described tiling apparatus, and cut and separated by a metal blade along the cut line 2 in the orthogonal X and Y directions.
[0045]
In the cutting process, as shown in FIGS. 4A and 4B, the sealing resin 7 is also cut at the same time so that the outer shape of the semiconductor package is made uniform and can be finished neatly to increase the product value. is there.
[0046]
FIG. 6 is a plan view showing the collective circuit board 1A in which a plurality of circuit patterns for CSP and the like are formed on the circuit board by electrolytic plating. This collective circuit board 1A has two common electrodes 14 extending in the X direction, and further has a plurality of common electrodes 14a connected to the common electrode 14 and extending in the Y direction. A plurality of common electrodes 14a extending in the Y direction have branch-like wiring patterns 14b connected to circuit patterns 14c of CSP products on both sides.
[0047]
For this collective circuit board 1A, IC chip mounting, sealing, solder ball attachment, etc. are performed in the same procedure as described in the previous embodiment, and a flat surface on the IC chip side is used as a reference member. Fix it. Thereafter, when performing the cutting process, in the circuit board by the electrolytic plating method, it is necessary to cut the individual wiring patterns from the common electrode. Therefore, as the cutting procedure in the X direction shown in FIG. , C ·· J, K, but the cutting interval of the common electrode 14b portion in the Y direction (the interval between BC, EF ·· IJ) is narrower than the interval between the other portions. When continuously cut , as shown in FIG. 2B and FIG. 5, when the gap between the adjacent IC chips 6 is not filled with the sealing resin 7, the fixing force to the reference member 8 is weak. There were problems such as the circuit board being deformed and the cutting line being displaced.
[0048]
Therefore, according to the present embodiment, by performing the cutting procedure in the X direction as A, B, D, E, G, H, I, K, C, F, and J, a common electrode portion having a narrow cutting interval is continuously formed. Since cutting is not performed, cutting can be performed without causing problems such as deformation of the circuit board and displacement of the cutting line.
[0049]
As described above, the method for manufacturing the semiconductor package in which the solder bump is formed as the protruding electrode on the external connection electrode formed on the other surface of the circuit board has been described. By forming the solder bump on the motherboard side, the circuit board side is provided. It goes without saying that the pad surface of the external connection electrode may be directly connected to the solder bump on the mother board side without forming the solder bump.
[0050]
【The invention's effect】
As described above, according to the method of manufacturing a semiconductor package of the present invention, a plurality of IC chips are arranged on the upper surface side of the collective circuit board and IC chips are mounted on the circuit board. After forming solder balls on the external connection electrodes on the lower surface side, fixing the IC chip side to the reference member, and cutting it to produce a single semiconductor package, each individual circuit board cut as in the past Solder balls are not attached. It is possible to provide an inexpensive method for manufacturing a semiconductor package that is suitable for multi-cavity mounting on a small portable device or the like and is excellent in productivity and reliability.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a circuit board forming process, an IC mounting process, and a resin sealing process in a manufacturing process of a semiconductor package according to an embodiment of the present invention.
2 is an explanatory view showing a reference member attaching step and a dicing step after the manufacturing step of FIG. 1; FIG.
FIG. 3 is a cross-sectional view showing a flattening step in which a flat surface is formed by cutting an IC chip side end surface and a resin surface. FIG.
FIG. 4 is a cross-sectional view showing a flattening step of forming a flat surface on the IC chip side with a sealing resin.
FIG. 5 is a cross-sectional view showing a flattening step for forming a flat surface by fixing a flat plate also serving as a heat sink to the IC chip side;
FIG. 6 is a plan view showing a collective circuit board in which a plurality of circuit patterns are formed on the circuit board by electrolytic plating.
FIG. 7 is a plan view of a conventional strip-shaped BGA.
FIG. 8 is an explanatory diagram showing a circuit board forming process, an IC mounting process, and a resin sealing process in a conventional BGA manufacturing process.
9 is an explanatory diagram showing a reference member pasting step, a dicing step, and a ball attaching step after the manufacturing step of FIG. 8 in the conventional BGA manufacturing step.
[Explanation of symbols]
1 circuit board 1A collective circuit board 2 cut line 3 electrode for IC connection 4 electrode for external connection 5 solder ball 6 IC chip 7 sealing resin 8 reference member 9 ball electrode (projection electrode)
10 Flip chip BGA
11 Flat surface 11a Cutting surface 12 Frame member 13 Flat plate 14 Common electrode

Claims (13)

ＩＣチップを実装した半導体パッケージの製造方法において、基板の一方の面に前記ＩＣチップ実装用のボンディングパターンを、他方の面に外部接続用電極を形成するための電極パターンを集合回路基板面に複数個分配列して形成する回路基板形成工程と、前記ボンディングパターンと前記ＩＣチップを電気的接続するＩＣチップ実装工程と、該ＩＣチップを樹脂封止する封止工程とによりパッケージ集合体を形成し、該パッケージ集合体のＩＣチップの端面側を基準部材に固定する保持工程と、保持された前記パッケージ集合体の前記集合回路基板を切削して単個の完成半導体パッケージを形成する切削工程とからなることを特徴とする半導体パッケージの製造方法。In a method of manufacturing a semiconductor package having an IC chip mounted thereon, a plurality of bonding patterns for mounting the IC chip are formed on one surface of the substrate, and a plurality of electrode patterns for forming external connection electrodes on the other surface are formed on the surface of the collective circuit board. A package assembly is formed by a circuit board forming step formed by arranging the individual, an IC chip mounting step for electrically connecting the bonding pattern and the IC chip, and a sealing step for resin-sealing the IC chip. from a holding step of fixing the end face of the IC chip of the package assembly to the reference member, and cutting the collective circuit board held the package assembly and cutting process of forming a single-number of the finished semiconductor package A method for manufacturing a semiconductor package, comprising: 前記パッケージ集合体保持工程は、前記ＩＣチップの端面側を平坦化する平坦化工程と、平坦化された前記ＩＣチップ側を前記基準部材に固着する固定工程とからなることを特徴とする請求項１記載の半導体パッケージの製造方法。The package assembly holding step, claims, characterized in that consists of a flattening step of flattening the end surface of the IC chip, a fixing step of fixing the flattened said IC chip side to the reference member 1. A method for producing a semiconductor package according to 1. 前記平坦化工程は、前記ＩＣチップの端面を切削して平坦化することを特徴とする請求項２記載の半導体パッケージの製造方法。The planarization step is a method of manufacturing a semiconductor package according to claim 2, wherein the flattening by cutting the end face of the IC chip. 前記平坦化工程は、封止面を切削して平坦化することを特徴とする請求項２記載の半導体パッケージの製造方法。  3. The method of manufacturing a semiconductor package according to claim 2, wherein in the planarization step, the sealing surface is cut and planarized. 前記平坦化工程は、ワイヤーボンディング実装した前記ＩＣチップの切削面高さが、ワイヤーボンディング形状の最高点より高いことを特徴とする請求項２又は４に記載の半導体パッケージの製造方法。The planarization step, the cutting surface height of the IC chip to which the wire bonding mounting method of producing a semiconductor package according to claim 2 or 4, characterized in that higher than the highest point of the wire bonding shape. 前記平坦化工程は、フリップチップ実装した前記ＩＣチップの切削面高さが、前記ＩＣチップの回路形成面より高いことを特徴とする請求項２〜４のいずれか１項に記載の半導体パッケージの製造方法。The planarization step, the cutting surface height of the IC chip is flip-chip mounting, a semiconductor package according to any one of claims 2-4, characterized in that above the circuit forming surface of the IC chip Production method. 前記平坦化工程は、前記ＩＣチップの端面に平板を固着したことを特徴とする請求項２，３，４，６のいずれか１項に記載の半導体パッケージの製造方法。7. The method of manufacturing a semiconductor package according to claim 2 , wherein the flattening step includes fixing a flat plate to an end face of the IC chip . 前記平板は金属であることを特徴とする請求項７記載の半導体パッケージの製造方法。  8. The method of manufacturing a semiconductor package according to claim 7, wherein the flat plate is a metal. 前記平坦化工程は、集合回路基板の外周部に枠を付け、封止樹脂を充填して平坦化したことを特徴とする請求項２記載の半導体パッケージの製造方法。  3. The method of manufacturing a semiconductor package according to claim 2, wherein in the planarization step, the outer periphery of the collective circuit board is framed and filled with a sealing resin for planarization. 前記ＩＣチップ側を前記基準部材に固定する保持工程は、接着剤で固着することを特徴とする請求項１又は２記載の半導体パッケージの製造方法。3. The method of manufacturing a semiconductor package according to claim 1, wherein the holding step of fixing the IC chip side to the reference member is fixed with an adhesive. 前記保持工程は、前記ＩＣチップ側の平坦面を真空吸着したことを特徴とする請求項１〜４、７、９のいずれか１項に記載の半導体パッケージの製造方法。It said holding step is a method of manufacturing a semiconductor package according to any one of claims 1～4,7,9, characterized in that vacuum suction a flat surface of the IC chip side. 前記切削工程は、ダイシングソーによる切削で行うことを特徴とする請求項１〜１１のいずれか１項に記載の半導体パッケージの製造方法。The cutting step is a method of manufacturing a semiconductor package according to any one of claims 1 to 11, characterized in that the cutting by the dicing saw. 前記切削工程は、前記封止樹脂も同時に切削されることを特徴とする請求項１〜１２のいずれか１項に記載の半導体パッケージの製造方法。The cutting step is a method of manufacturing a semiconductor package according to any one of claims 1 to 12, wherein the sealing resin is also cut at the same time.
JP15868897A 1997-05-09 1997-06-16 Manufacturing method of semiconductor package Expired - Fee Related JP4115556B2 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP15868897A JP4115556B2 (en) 1997-06-16 1997-06-16 Manufacturing method of semiconductor package
EP98917679.7A EP0932198B1 (en) 1997-05-09 1998-04-24 Process for manufacturing semiconductor package and circuit board assembly
PCT/JP1998/001905 WO1998052220A1 (en) 1997-05-09 1998-04-24 Process for manufacturing semiconductor package and circuit board assembly
CNB988005794A CN1185702C (en) 1997-05-09 1998-04-24 Process for mfg. semiconductor package and circuit board assembly
EP08167595.1A EP2015359B1 (en) 1997-05-09 1998-04-24 Process for manufacturing a semiconductor package and circuit board substrate
US09/194,735 US6365438B1 (en) 1997-05-09 1998-04-24 Process for manufacturing semiconductor package and circuit board assembly
KR1019997000071A KR100568571B1 (en) 1997-05-09 1998-04-24 Process for manufacturing a semiconductor package and circuit board aggregation
TW087106959A TW395033B (en) 1997-05-09 1998-05-06 Process for manufacturing a semiconductor package and circuit board aggregation
MYPI98002064A MY123937A (en) 1997-05-09 1998-05-07 Process for manufacturing semiconductor package and circuit board assembly

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