JP4113692B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a tamper resistance function that can counter a confidential decryption of a wiring structure.
[0002]
[Prior art]
A semiconductor device generally has a circuit configuration in which a large number of semiconductor elements are arranged on a substrate, and wiring is provided between electrodes of the respective semiconductor elements.
In such a semiconductor device, a circuit component is covered with an insulating protective film such as silicon oxide or silicon nitride in order to avoid the influence of an external atmosphere such as α rays, moisture, and stress. In addition, with the increase in the circuit scale and the reduction in chip area, the circuit component has been made into multi-layer wiring using an interlayer insulating film.
Some circuit components in a semiconductor device require a long time for development and are highly original. Therefore, some circuit components are processed so as not to be imitated or duplicated by others.
However, since the protective film and the interlayer insulating film described above are disposed for the purpose of protecting the circuit components from the external atmosphere and electrically insulating the metal wiring, a solution (for example, hydrofluoric acid) The structure of the metal wiring in the circuit component can be easily analyzed by peeling off with the acidic solution.
In order to prevent such an analysis, the following semiconductor device has been proposed (Japanese Patent Laid-Open No. 1-165129).
[0003]
As shown in FIG. 5, this semiconductor device includes a circuit component 20 in which a large number of semiconductor elements arranged on a semiconductor substrate are wired to each other, and an insulating protective film 22 (for example, a silicon nitride film) covering them. And have. The surface of the circuit component 20 is covered only with the protective film 22 in an area where security is not required, and is sequentially covered with a lower protective film 22a, a metal film 23, and an upper protective film 22b in a main area where security is required. It has been broken.
As a result, even if the protective film 22 is etched, the metal film 23 is not removed on the area where confidentiality is required, so that the wiring pattern 21 in the circuit component 20 below is not exposed and cannot be visually recognized. Further, even if the metal film 23 is removed by etching in this state, even the wiring pattern 21 made of the same material as the metal film 23, for example, aluminum, is removed, and the circuit component 20 cannot be analyzed.
[0004]
[Problems to be solved by the invention]
However, since the lower protective film 22a exists under the metal film 23, after etching the upper protective film 22b until the metal film 23 is exposed, the protective film 22 and the lower protective film 22a are used as an etching stopper, By etching the metal film 23, only the metal film 23 can be removed, and the wiring pattern 21 disposed below the metal film 23 can be recognized, and there is a problem that the circuit can be analyzed.
The present invention has been made in view of the above problems, and provides a semiconductor device that can easily prevent analysis of a wiring structure by etching a package, a protective film, an insulating film between metal wirings, and the like with a solution. The purpose is to do.
[0005]
[Means for Solving the Problems]
According to the present invention, a semiconductor device having a multilayer wiring structure having an outermost surface coated with a protective film and provided with an interlayer insulating film, wherein the protective film and / or the interlayer insulating film is partially above the wiring layer. In addition, a semiconductor device formed of a material having a high etching rate is provided.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
The semiconductor device of the present invention comprises a semiconductor device having a multilayer wiring structure. Here, a semiconductor device having a multilayer wiring structure is usually formed on a semiconductor substrate with elements such as transistors, capacitors, resistors, etc., on which a first-layer interlayer insulating film, a first-layer wiring, a second-layer interlayer insulation are formed. This means a semiconductor device formed by laminating films ..., n-th layer wiring (n is an integer of 2 or more) in this order. Further, the outermost surface of this semiconductor device is covered with a protective film.
[0007]
In this semiconductor device, the protective film and / or the interlayer insulating film is partially formed of a material having a high etching rate above the wiring layer. The wiring layer here may be any of the first to nth wiring layers, but means at least a part or all of the upper part of the wiring layer for which analysis of the wiring structure is desired to be prevented. The protective film and the interlayer insulating film are not particularly distinguished from each other in terms of materials and functions as long as they can protect the wiring layer and the like in the semiconductor device and can ensure the insulation of the wiring layer. Further, the material having a partially high etching rate means that when the protective film or the interlayer insulating film is etched under a certain condition, the etching ratio of the material having a high etching rate with respect to the protective film or the interlayer insulating film is 2 or more. It means 4 or more, 5 or more, 10 or more, 20 or more, preferably 30 or more, more preferably 40 or more. For example, a film in which the protective film or the interlayer insulating film has an etching rate of about 1 to 200 nm / min and a material having a high etching rate has an etching rate of about 100 to 600 nm / min. The material in this case is not particularly limited as long as it is an insulating film, and it may be the same material as the protective film or the interlayer insulating film but may be of different film quality or of a different material. . Specifically, the protective film or the interlayer insulating film is formed of a thermal CVD oxide film, a plasma CVD oxide film, a plasma CVD oxynitride film, a plasma CVD nitride film, or the like, and a material having a high etching rate in the film, for example, Examples include a film in which an SOG film or the like is disposed. However, any combination of films of these materials may be used as long as the etching rates are different. Note that the protective film and / or the interlayer insulating film formed with the material film having a high etching rate may be combined with different materials for each layer in a semiconductor device having a multilayer wiring structure, but the same combination is used for a plurality of layers. Preferably there is. For the etching, any etching method such as wet etching using an acid or alkali solution, dry etching such as RIE method, and etching conditions may be selected.
[0008]
The film formed of a material having a high etching rate is determined depending on the number of wiring layers stacked in the multilayer wiring structure, the position of the wiring layer having the wiring structure to be kept secret, the position, shape, and film thickness in the protective film or interlayer insulating film. Etc. can be adjusted appropriately. Note that the film formed of this material may be disposed only on the protective film, or may be disposed only on at least one interlayer insulating film, or both the protective film and at least one interlayer insulating film. Alternatively, it may be disposed on the protective film and all interlayer insulating films. Preferably, it is disposed on the interlayer insulating film and the protective film above the wiring layer having a wiring structure for which secrecy is desired. For example, when the semiconductor device has a two-layer wiring structure and it is desired to keep the structure of the first-layer wiring confidential, a material having a high etching rate may be disposed in the protective film and the second-layer interlayer insulating film. preferable. In the case of having a three-layer wiring structure and wanting to keep the first-layer wiring structure confidential, it is preferable to dispose a material having a high etching rate in the protective film and the third and second interlayer insulating films. . In the case of having a three-layer wiring structure and wanting to keep the second-layer wiring structure confidential, it is preferable to dispose a material having a high etching rate for the protective film and the third-layer interlayer insulating film. Note that in the case where it is not desired to keep the structure of the n-th layer wiring, that is, the uppermost layer wiring, a material having a high etching rate is not necessarily disposed in the protective film.
[0009]
The film formed of a material having a high etching rate may be formed in any region in the interlayer insulating film and / or the protective film. It is preferable that a material having a high etching rate is disposed at least on a part of or the entire region of the protective film or interlayer insulating film immediately above the wiring layer where confidentiality is to be maintained. Furthermore, it is preferable that a material having a high etching rate is disposed on all or a part of the entire protective film and / or interlayer insulating film above the wiring layer in which confidentiality is to be maintained. In this case, that is, when a material having a high etching rate is disposed in the plurality of interlayer insulating films or the like, at least a part of a region formed of the material having a high etching rate is viewed from the top surface of the semiconductor device. It is preferable that all the interlayer insulating films overlap.
[0010]
In general, the protective film and the interlayer insulating film may be formed in any thickness as long as each function can be ensured in the semiconductor device. In addition, the thickness of the film formed using a material having a high etching rate may be smaller than or equal to the thickness of the protective film or the interlayer insulating film. The film thickness of these films is preferably adjusted as appropriate according to the material and film quality, the performance of the semiconductor device to be obtained, and the like. For example, when the protective film and / or the interlayer insulating film is removed by etching, the protective film is protected. A material having a high etching rate in the film and / or the interlayer insulating film, and a protective film and / or an interlayer insulating film, a material film having a high etching rate so as to be able to corrode a part or all of the wiring layer for which the wiring structure is to be kept secret It is preferable to set the film thickness. Further, when the protective film and / or the interlayer insulating film is removed by etching, a material having a high etching rate in the protective film and / or the interlayer insulating film and an interlayer insulating film below the protective film and / or the interlayer insulating film (one layer or two or more layers may be used) The film thickness of each film is set so that a material having a high etching rate is removed by etching, and further, a part or all of the wiring layer in which the wiring structure is to be kept secret can be corroded. Is preferred. That is, when the protective film and / or the interlayer insulating film is removed by etching, almost all of the film made of a material having a high etching rate is present above the wiring layer so that the wiring structure of the wiring layer to be kept secret cannot be visually recognized. It is preferable that the thickness of each film is set to such a thickness that the etching is removed and a part or all of the wiring layer to be kept secret is corroded.
[0011]
In the semiconductor device of the present invention, the wiring layer constituting the multilayer wiring structure may be formed in any shape and film thickness as long as it is formed using a normal conductive material. For example, it can be formed of a single layer film or a laminated film such as a metal or an alloy such as aluminum, copper, platinum, gold, nickel, titanium, tantalum, tungsten, or cobalt, a semiconductor thin film or an alloy with reduced resistivity, or the like.
Note that an interlayer insulating film and / or protective film formed of a material having a high etching rate as described above may be used in various devices having a high etching rate when used in a device performing the same type of operation. It is preferable to arrange with different patterns.
[0012]
Embodiments of a semiconductor device of the present invention will be described below with reference to the drawings.
FIG. 1 shows a semiconductor device having a multilayer wiring structure provided with a tamper-resistant interlayer insulating film. This semiconductor device includes a first interlayer insulating film 2, a first layer wiring 3, a second interlayer insulating film 4, a second layer wiring 6, and a third interlayer insulating film on a silicon substrate 1 on which elements such as transistors are formed. The seventh and third wirings 9, the fourth insulating film 10, the lower and upper protective films 12 and 13 are formed in this order. A second film 5 made of a material having a high etching rate is arranged in the second interlayer insulating film 4 immediately above a region where the secret of the structure of the first-layer wiring 3 is desired to be maintained. A third film 8 made of a material having a high etching rate is arranged in a part of the film 7 so as to overlap the second film 5, and is in the fourth insulating film 10, The fourth film 11 is disposed in a region overlapping the film 5 and immediately above a partial region of the third-layer wiring 9.
[0013]
Such a semiconductor device can be manufactured by the following method.
First, as shown in FIG. 2A, a semiconductor element such as a MOS transistor is formed on a silicon substrate 1 in accordance with a normal procedure, and the entire surface of the obtained silicon substrate 1 is subjected to a CVD (Chemical Vapor Deposition) method. A first interlayer insulating film 2 is deposited to a predetermined thickness, a contact hole is opened at a predetermined position, a first conductive film is formed on the first interlayer insulating film 2 including the contact hole, and is patterned into a desired shape. Thus, the first layer wiring 3 is formed. The contact hole can be formed by a method and conditions usually used in the semiconductor integrated circuit manufacturing process. The first layer wiring 3 is formed of a laminated film of a TiW film having a thickness of about 310 nm and an AlSi film having a thickness of about 600 nm. Thereby, wiring between each element is performed.
[0014]
Next, as shown in FIG. 2B, a silicon oxide film having a thickness of about 2000 nm is deposited on the entire surface of the silicon substrate 1 including the first layer wiring 3 by the plasma CVD method, and the unevenness due to the first layer wiring 3 is flattened. For this purpose, the silicon oxide film is polished by about 800 nm by CMP (Chemical Mechanical Polishing) to form the second interlayer insulating film 4 having a thickness of about 1200 nm. Then, holes are formed in the second interlayer insulating film 4 in a region where security is required by photolithography and etching processes. The holes at this time may be formed with a depth that is about the same as the total thickness of the second interlayer insulating film 4 or may be formed with a depth that reaches the upper surface of the first-layer wiring 3.
[0015]
Subsequently, as shown in FIG. 3C, the second film 5 is laminated by SOG (Spin on Glass) method, the surface thereof is flattened, and the second film 5 is formed in the hole of the second interlayer insulating film 4. Embed. The SOG method is an advantageous method for flattening because a fluid insulating film can be easily formed by spin coating and can be formed in a thick film in a concave portion rather than a convex portion. Each of the second interlayer insulating film 4 and the second film 5 is an insulating film containing SiO ₂ as a main component, but an acidic chemical solution (for example, HF) due to moisture contained in the insulating film and the denseness of the film. The etching rate by is different. That is, the second interlayer insulating film 4 has an etching rate of about 100 to 200 nm / min with a 10: 1 buffered hydrofluoric acid solution (water: BHF = 10: 1), and the second film 5 has an etching rate of 10: 1. The etching rate is about 400 to 500 nm / min with BHF.
[0016]
Next, as shown in FIG. 3D, a via hole is formed at a predetermined position of the second interlayer insulating film 4 so as to connect the wirings formed by the first-layer wiring 3 to each other. The via hole can be formed by the same method as the contact hole. A second conductive film is formed on the second interlayer insulating film 4 and the second film 5 including the via hole, and patterned into a desired shape, thereby forming a second-layer wiring 6. The second layer wiring 6 is formed of the same laminated film as the first layer wiring 3.
[0017]
Subsequently, as shown in FIG. 3E, a silicon oxide film of about 2000 nm is deposited on the entire surface of the silicon substrate 1 including the second-layer wiring 6 by the plasma CVD method, and the surface is polished by the CMP method. Thus, a third interlayer insulating film 7 having a thickness of about 1200 nm is formed. Then, holes are formed in the third interlayer insulating film 7 by photolithography and etching processes so as to be in contact with a part of the lower region where confidentiality is required. A third film 8 is stacked on the third interlayer insulating film 7 including holes by the SOG method, the surface thereof is planarized, and the third film 8 is embedded in the holes of the third interlayer insulating film 7.
Thereafter, as shown in FIG. 4F, a via hole is formed at a predetermined position in the third interlayer insulating film 7, and a third conductive film is formed on the third film 8 including the via hole to have a desired shape. The third layer wiring 9 is formed by patterning. The third layer wiring 9 is formed of the same laminated film as the first layer wiring 3.
[0018]
Subsequently, as shown in FIG. 4G, a fourth insulating film 10 made of a silicon nitride film having a thickness of about 1000 nm is formed on the entire surface of the silicon substrate 1 including the third-layer wiring 9 by a plasma CVD method, thereby protecting the security. A hole is formed in the fourth insulating film 10 so as to be in contact with a part of the region requiring the security (the region of the third-layer wiring 9) and the region requiring the confidentiality of the lower layer. A fourth film 11 is stacked on the fourth insulating film 10 including holes by the SOG method, and the surface thereof is planarized, and the fourth film 11 is embedded in the holes of the fourth insulating film 10. The etching rates of the fourth insulating film 10 and the fourth film 11 differ depending on the moisture contained in the insulating film and the denseness of the film, depending on the acid chemical solution (for example, HF). That is, the fourth insulating film 10 has an etching rate of about 10 nm / min with 10: 1 BHF, and the fourth film 11 has an etching rate of about 400 nm / min with 10: 1 BHF.
[0019]
Thereafter, a lower protective film 12 is formed of a silicon nitride film having a thickness of about 200 nm by plasma CVD, and a PSG film having a thickness of about 20000 nm by thermal CVD is formed thereon as an upper protective film 13. The semiconductor device shown in FIG. These lower and upper protective films 12 and 13 are employed to prevent external impurities from being mixed and to improve corrosion resistance.
Thus, when a device formed by combining insulating films having different etching rates is treated with a 10: 1 BHF chemical solution, the third-layer wiring 9 is not acid-resistant and easily corroded, but the upper protective film 13 Visualization is possible by removing the lower protective film 12.
[0020]
In order to visually recognize the second layer wiring 6 and the first layer wiring 3, it is necessary to further peel off the fourth film 11, the fourth insulating film 10, and the third layer wiring 9.
Therefore, first, etching is performed uniformly in the horizontal direction until the surfaces of the fourth film 11 and the fourth insulating film 10 are exposed.
Next, the fourth film 11 and the fourth insulating film 10 are etched by 10: 1 BHF. The etching time at this time needs to be set so that the fourth insulating film 10 having a small etching rate is completely removed, and the etching time is 1000 nm / (10 nm / min) = 100 minutes.
[0021]
However, while the fourth insulating film 10 is etched for 100 minutes, the insulating film, the fourth film 11, the third film 8, and the second film 5 whose etching rate is about 400 nm / min are all removed, and further The first layer wiring 3 is also corroded. Therefore, pattern analysis of the second layer wiring 6 and the first layer wiring 3 cannot be performed.
That is, by forming the interlayer insulating film with a plurality of materials having different etching rates in the same layer, the pattern shape for each material of the interlayer insulating film in each layer can be obtained using the difference in the etching rate for each material of the insulating film. In addition, it is possible to freely set the film thickness of the insulating film up to the metal wiring pattern that needs to be kept confidential, and this makes it possible to analyze illegal metal wiring patterns by stepping off the interlayer insulating film etc. from the top layer Can be prevented.
In addition, since the patterning described above is independent of circuit logic, even an integrated circuit that operates in the same type can be freely patterned, and illegal analysis can be prevented more complicatedly. It becomes possible.
[0022]
【The invention's effect】
According to the present invention, in a semiconductor device having a multilayer wiring structure, the protective film and the interlayer insulating film existing above the wiring layer for which analysis of the wiring structure is to be prevented are formed of a material having a higher etching rate than other parts. That is, by using a simple method of disposing materials having different etching rates in a desired pattern in the protective film and / or the interlayer insulating film, by removing the package, the protective film, the interlayer insulating film, etc. using wet etching. It is possible to provide a tamper-resistant semiconductor device that can effectively prevent analysis of the wiring structure and ensure confidentiality of the wiring structure of the semiconductor device.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of a main part showing an embodiment of a semiconductor device of the present invention.
FIG. 2 is a schematic cross-sectional process diagram of a main part for explaining a manufacturing process of the semiconductor device of FIG. 1;
3 is a schematic cross-sectional process diagram of the main part for explaining a manufacturing process of the semiconductor device of FIG. 1; FIG.
4 is a schematic cross-sectional process diagram of the main part for explaining the manufacturing process of the semiconductor device of FIG. 1; FIG.
FIG. 5 is a schematic cross-sectional process diagram of a main part showing a conventional semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 1st interlayer insulation film 3 1st layer wiring 4 2nd interlayer insulation film 5 2nd film 6 2nd layer wiring 7 3rd interlayer insulation film 8 3rd film 9 3rd layer wiring 10 4th insulation film 11 Fourth film 12 Lower protective film 13 Upper protective film

Claims (3)

A semiconductor device having a multilayer wiring structure, the outermost surface of which is covered with a protective film, includes an interlayer insulating film, and includes at least an upper wiring layer and a lower wiring layer, and an interlayer insulating film in at least a part of the region on the lower wiring layer However, it is desired to keep at least a part where the interlayer insulating film in the non-existing region is made of a material having a higher etching rate than the interlayer insulating film in the non-existing region, having a region where the upper wiring layer is present and a region not existing the semiconductor device that may prepare for the lower wiring layer on the surface. Both the protective film and the interlayer insulating film on the surface of the wiring layer in at least a partial region of the wiring layer that the semiconductor device wants to keep confidential with respect to the protective film and the interlayer insulating film in other regions 2. The semiconductor device according to claim 1, wherein the semiconductor device is made of the same material having a high etching rate. The protective layer and / or the interlayer insulating film, thermal CVD oxide film, a plasma CVD oxide film, formed by plasma CVD oxynitride film or Burazuma CVD nitride film, a large material of the etching rate, Ru SOG film Der claims Item 3. The semiconductor device according to Item 1 or 2 .

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