JP4110643B2 - Grid interconnection inverter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a grid-connected inverter that converts DC input power into AC that is suitable for a grid power supply and supplies power to the grid.
[0002]
[Prior art]
An example of a grid-connected inverter used conventionally will be described with reference to FIG. The grid interconnection inverter 1 converts the DC power supply 2 so as to conform to the power supply specifications of the grid 3 such as 100 V 60 Hz and supplies power to the grid 3. 4 is a load connected to the system 3, and 5 is a switch for separating the system 3 and the system interconnection inverter 1. The grid interconnection inverter 1 includes inverter means 6, reference waveform generation means 7, voltage detection means 8, and ZVP creation means 9. The inverter unit 6 forms an output current waveform based on the reference waveform output from the reference waveform generation unit 7 and supplies power to the system 3. The voltage detection means 8 is composed of a transformer or the like, and takes in the output of the inverter means 6, that is, the output voltage waveform of the grid interconnection inverter 1. The ZVP creating means 9 creates a signal (zero volt pulse) indicating the zero volt phase position based on the information of the voltage detecting means 8 and transmits it to the reference waveform generating means 7. The reference waveform generation means 7 generates a reference waveform of the output current using this signal as a zero volt phase position of the output current.
[0003]
[Problems to be solved by the invention]
However, the conventional grid-connected inverter has a problem that it does not have means for detecting this state when the switch is in an open state or the line leading to the system 3 is disconnected. That is, when the grid-connected inverter continues to supply power to the load in the above state, there is a possibility of causing an accident such as an electric shock of an operator who tries to restore the disconnection.
[0004]
[Means for Solving the Problems]
In the present invention, the inverter means stops operation when the frequency of the zero cross signal created by the ZVP creation means exceeds an allowable value, and the operation is reliably stopped when the grid-connected inverter is disconnected from the system. A safe grid-connected inverter that can be used.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
According to the first aspect of the present invention, there is provided inverter means for converting a direct current input power source into alternating current based on a reference waveform of the reference waveform generating means and outputting it to a system, voltage detection means for detecting an output voltage of the inverter means, voltage Compare the ZVP creation means for outputting a signal indicating the zero volt phase of the output voltage of the inverter means from the output of the detection means, and the current timing and the timing immediately before the zero volt phase output signal created by the ZVP creation means Initial fluctuation comparison means, and initial fluctuation comparison fluctuation means for switching between the initial fluctuation means and the cumulative fluctuation comparison means for comparing the continuous second and subsequent zero-volt phase output signals, and the initial fluctuation comparison means. Or, when the zero volt phase output signal compared by the integrated fluctuation comparator exceeds the specified range, the integrated fluctuation comparator is zero. When it is detected that the default phase output signal exceeds the predetermined range, the reference waveform generation unit generates compared to when the initial fluctuation comparison unit detects that the zero volt phase output signal exceeds the predetermined range. A grid interconnection inverter comprising delay means for delaying the reference waveform signal for a long time, and control means for stopping the inverter means when the frequency detected based on the ZVP signal created by the ZVP creation means exceeds an allowable value Yes.
[0006]
【Example】
(Example 1)
The first embodiment of the present invention will be described below. FIG. 1 is a block diagram showing the configuration of this embodiment. 11 is a grid-connected inverter of this embodiment, which converts the voltage of the DC power source 2 using solar cells or the like into AC such as 100 V, 60 Hz, etc., and connects it to the system 3 via the switch 5. The load 31 is supplied. Here, the system 3 is set to 100 V and 60 Hz. Of course, when the grid 3 is 100 V and 50 Hz, the grid interconnection inverter 11 supplies 100 V and 50 Hz to the load 31.
[0007]
The grid interconnection inverter 11 includes inverter means 16, reference waveform generation means 17, voltage detection means 18, ZVP creation means 19, control means 30, reference waveform period division means 20, and disconnector 21. The inverter means 16 includes a switching element and an inverter control unit that drives the switching element. Further, the reference waveform generating means 17 determines the operation at each moment so that the output of the inverter means 16 becomes a sine wave of 50 Hz or 60 Hz. That is, the inverter unit 16 converts the DC power source 2 into a sine wave having a commercial frequency by referring to the reference waveform generated by the reference waveform generation unit 17. The voltage detection means 18 uses a transformer in this embodiment, takes in the voltage waveform of the output of the inverter means 16, that is, the output of the grid interconnection inverter 11, and converts it into a signal voltage of an appropriate magnitude, and ZVP This is transmitted to the creating means 19. The ZVP creating means 19 receives a signal from the voltage detecting means 18 and creates a zero volt phase position signal (hereinafter referred to as a ZVP signal) indicating the zero volt position, and sends it to the reference waveform generating means 17 and the reference waveform period dividing means 20. Communicating. The reference waveform period dividing means 20 is constituted by a PLL circuit or the like, and generates a signal that equally divides a half cycle or one period by an arbitrary interval by the ZVP signal created by the ZVP creating means 19. . In this embodiment, the half cycle is equally divided into 128. The reference waveform generating means 17 generates the reference waveform based on the ZVP signal created by the ZVP creating means 19 and the divided signal created by the reference waveform period dividing means 20, and the inverter means 16 This is transmitted to the inverter control unit. The control means 30 stops the inverter means 16 and opens the circuit breaker 21 when the frequency of the output voltage of the grid interconnection inverter 11 exceeds the allowable value by the ZVP signal produced by the ZVP creation means 19.
[0008]
The operation of this embodiment will be described below. When the user turns on a switch (not shown), the inverter control unit that constitutes the inverter means 16 drives the switching element that also constitutes the inverter means 16 to turn on and off the voltage of the DC power supply 2 and convert it to commercial AC. , Supplied to the load 31. At this time, when the frequency of the output voltage of the grid interconnection inverter 11 changes due to fluctuations in the commercial frequency of the grid 3, etc., the voltage detection means 18 instantly grasps the change in the output voltage in this state, and ZVP The creating means 19 creates a ZVP signal in this state. Therefore, the reference waveform generation means 17 creates a reference waveform corresponding to this state and transmits it to the inverter control unit. Therefore, since the inverter means 16 operates based on this reference waveform, when there is a change in the commercial frequency, an AC waveform having this changed frequency is created.
[0009]
Further, when the power failure of the system 3 or the opening of the switch 5 occurs, the voltage and frequency at both ends of the load 4 change. The voltage detection means 18 grasps the change in the output voltage and the frequency in the changed state, and the ZVP creation means 19 creates the ZVP signal in this state and transmits it to the control means 30. In the present embodiment, the control means 30 stops the inverter means 16 when the frequency detected based on the ZVP signal created by the ZVP creation means 19 exceeds an allowable value. In this embodiment, the allowable value is set to ± 10%. Thus, when the inverter means 16 is stopped, the grid interconnection inverter 11 stops driving and does not supply current to the load 31.
[0010]
As described above, according to this embodiment, the load 31 is disconnected from the system 3 by a power failure or the like so that the operation is stopped when the frequency of the zero cross signal generated by the ZVP generation unit 19 exceeds the allowable value. Sometimes, the operation can be stopped reliably and a safe grid-connected inverter is realized.
[0011]
(Example 2)
Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram showing the configuration of this embodiment. Components having the same numbers as those in FIG. 1 have the same functions. Reference numeral 22 denotes a grid interconnection inverter of the present embodiment, which has a comparison means 23 and a delay means 24. The comparison means 23 compares the timing immediately before the zero volt phase output signal created by the ZVP creation means 19 with the current timing. The delay means 24 delays the reference waveform signal generated by the reference waveform generation means 17 and supplies it to the inverter means 16 when the zero volt phase output signal compared by the comparison means 23 exceeds a predetermined range. It is.
[0012]
The operation of this embodiment will be described below. As described in the first embodiment, when the power failure of the system 3 or the opening of the switch 5 occurs, the voltage and frequency at both ends of the load 4 change. The voltage detection means 18 grasps the change in the output voltage and the frequency in the changed state, and the ZVP creation means 19 creates the ZVP signal in this state and transmits it to the control means 30. At this time, in this embodiment, the timing immediately before the zero volt phase output signal created by the ZVP creating means 19 is compared with the current timing. By this comparison, since the frequency calculated from the zero volt phase output signal exceeds a predetermined range at the moment when the abnormality such as the power failure occurs, it can be understood that the abnormality such as the power failure has occurred. The output signal of the comparison means 23 is transmitted to the delay means 24, and the delay means 24 delays the reference waveform signal generated by the reference waveform generation means 17 by a predetermined time and supplies it to the inverter means 16. Therefore, in this state, the voltage or current generated by the inverter means 16 has a waveform delayed from a normal sine wave. For this reason, the voltage waveform detected by the voltage detection means 18 is surely shifted in phase from the normal waveform, and the ZVP signal generated by the ZVP generation means 19 is naturally shifted from the normal frequency. Therefore, the frequency recognized by the control means 30 surely exceeds a predetermined range, and the control means 30 immediately stops the inverter means 16 and opens the disconnector 21.
[0013]
As described above, according to the present embodiment, the comparison unit 23 generates a signal for comparing the current timing with the timing just before the frequency calculated from the zero volt phase output signal created by the ZVP creation unit 19. When this signal exceeds a predetermined range, the reference waveform signal generated by the reference waveform generation means 17 is delayed so that the inverter means 15 positively outputs when the load 4 is disconnected from the system 3. This is to realize a safe grid-connected inverter that delays the waveform to be delayed from the regular waveform and can reliably stop the operation.
[0014]
(Example 3)
Next, a third embodiment of the present invention will be described. FIG. 3 is a block diagram showing the configuration of this embodiment. In the present embodiment, the grid interconnection inverter 32 has reset means 36. The output signal of the comparison unit 23 and the output signal of the ZVP creation unit 19 are input to the input terminal of the reset unit 36. The reset means 36 compares the ZVP signal of the ZVP creation means 19 at the timing determined by the output signal of the comparison means 23 with the ZVP signal at the current timing. As a result, when the ZVP signal created by the ZVP creating unit 19 does not change, the reset unit 36 acts to restore the phase of the reference waveform.
[0015]
That is, in this embodiment, when the cause of the load 4 being disconnected from the system 3 is due to noise or the like, the normal state can be immediately restored.
[0016]
Example 4
Next, a fourth embodiment of the present invention will be described. FIG. 4 is a block diagram showing the configuration of this embodiment. In the present embodiment, the voltage detecting means 18 has a band pass filter 42. The band pass filter 42 removes frequency components other than the vicinity of the system frequency such as high frequency noise and harmonic noise. Therefore, according to the present embodiment, the ZVP signal created by the ZVP creating means 19 is accurate without being affected by the noises. For this reason, according to the present embodiment, a phase shift due to a power failure can be clearly understood, and a safe grid-connected inverter that can reliably stop operation when the load is disconnected from the grid.
[0017]
(Example 5)
Next, a fifth embodiment of the present invention will be described. FIG. 5 is a block diagram showing the configuration of this embodiment. In the present embodiment, the ZVP creating means 19 has a bandpass filter correcting means 52. The bandpass filter correction means 52 shifts the phase of the zero volt signal output from the ZVP creation means 19. Alternatively, the phase of the zero volt signal output from the ZVP generating unit 19 is output by one division before or after the equal division signal of the reference waveform period dividing unit 20 by one division. For this reason, the reference waveform signal output by the reference waveform generation means 17 is not affected by the bandpass filter 42 and maintains an accurate phase.
[0018]
As described above, according to this embodiment, the phase shift of the waveform of the reference waveform generation means 20 generated by passing the bandpass filter 42 so as to correct the phase shift due to the frequency characteristics of the bandpass filter 42 is corrected. Thus, the accuracy of the frequency detected by the ZVP creating means 19 is improved, and in addition to the operation of the delay means 23, a grid-connected inverter having a stable detection speed is realized.
[0019]
(Example 6)
Next, a sixth embodiment of the present invention will be described. In this embodiment, the voltage detection means 18 has a 50 Hz band pass filter 62 and a 60 Hz band pass filter 63, and the ZVP creation means 19 has a 50/60 Hz switching means 64. For this reason, the poor detection accuracy due to the phase shift of the bandpass filter at 50 Hz and 60 Hz can be improved, the detection accuracy of the voltage detection means 18 is improved, and frequency components other than those near the system frequency such as high frequency noise and harmonic noise are removed. The ZVP creating means 19 can generate a reliable zero volt signal.
[0020]
As described above, according to the present embodiment, it is possible to realize a grid-connected inverter that can reliably detect a power failure regardless of whether it is a 50 Hz region or a 60 Hz region and can reliably stop the operation in the event of a power failure.
[0021]
(Example 7)
Next, a seventh embodiment of the present invention will be described. In the present embodiment, the grid interconnection inverter 71 has counter means 72. The counter means 72 is connected to the output terminal of the comparison means 23. The comparison means 23 compares the ZVP signal created by the ZVP creation means 19 with the previous timing and the current timing, and outputs an excess fluctuation signal corresponding to the difference between the two to the counter means 72. Yes. The counter means 72 outputs a signal corresponding to the excess fluctuation signal to the delay means 24. For this reason, the delay unit 24 shifts the phase of the reference waveform generated by the reference waveform generation unit 17 by the time set by the counter unit 72.
[0022]
For this reason, the phase of the AC waveform output from the inverter means 16 is shifted by the time delayed by the delay means 24. As a result, the phase of the voltage detected by the voltage detection means 18 is surely shifted from the normal phase, and the control means 30 reliably stops the inverter means 16 or opens the disconnector 21. is there.
[0023]
As described above, according to the present embodiment, the counter unit 72 counts the output signal of the comparison unit 23 that compares the timing immediately before the zero volt phase output signal generated by the ZVP generation unit 18 with the current timing. Then, the delay means 24 delays the reference waveform signal according to the degree to which the zero volt phase output signal deviates from the predetermined value, and the waveform that the inverter means 16 positively outputs when the load 4 is disconnected from the system. It is possible to realize a safe grid-connected inverter that can be reliably stopped by delaying from a regular waveform.
[0024]
(Example 8)
Next, an eighth embodiment of the present invention will be described. FIG. 8 is a block diagram showing the configuration of this embodiment. The grid interconnection inverter 81 of the present embodiment has timer means 82. The timer means 82 is connected to the comparison means 23. For this reason, the timing at which the comparison means 23 performs the comparison operation is determined by the timer means 82. That is, when detecting a power outage or the like of the system 3, in order to prevent erroneous detection due to the influence of noise or the like, the time from when the power outage occurs until the inverter means 16 stops driving is various technologies. It is set by standards or guidelines. For example, “Distributed power system interconnection technical guidelines (issued in November 1993)” supervised by the Agency for Natural Resources and Energy, Ministry of International Trade and Industry It is prescribed.
[0025]
Therefore, in this embodiment, the operation timing of the comparison means 23 is set by the timer means 32. For this reason, according to this embodiment, the time until the frequency shift of the inverter means 16 is observed, that is, the detection time of the comparison means 23 is set to an arbitrary time, so that the time until the inverter stops can be set arbitrarily. It is possible to achieve a grid-connected inverter that can meet market demands, technical standards, guidelines, and the like.
[0026]
Example 9
Next, a ninth embodiment of the present invention will be described. FIG. 9 is a block diagram showing the configuration of this embodiment. In the present embodiment, the grid interconnection inverter 91 includes a positive / negative determining means 92. The positive / negative determining means 92 is connected to the output of the comparing means 23, determines whether the excess fluctuation signal output from the comparing means 23 has an increased frequency or decreased frequency, and determines that the delay means is positive or negative. 24. That is, for example, when the positive / negative determining unit 92 determines that the output of the comparing unit 23 is positive, in other words, when the frequency calculated from the ZVP signal generated by the ZVP generating unit 19 tends to increase, a delay occurs. The means 24 operates so as to advance the phase of the reference waveform generated by the reference waveform generation means 17. When the positive / negative determining means 92 determines that the output of the comparing means 23 is negative, in other words, when the frequency calculated from the ZVP signal created by the ZVP creating means 19 tends to decrease, the delay means 24, the reference waveform generated by the reference waveform generation means 17 is delayed.
[0027]
As a result, the delay means 24 moves the reference waveform in the direction in which the frequency fluctuates. Therefore, for the same reason, the output waveform output from the inverter means 16 is out of phase in the direction of amplifying frequency fluctuations. Therefore, the phase of the voltage detected by the voltage detection means 18 is also shifted as described above. That is, the ZVP signal created by the ZVP creation means 19 is similarly out of phase, and the frequency detected by the control means 30 surely exceeds the reference value. Therefore, the control means 30 stops the inverter means 16 or opens the disconnector 21.
[0028]
Further, it is possible to prevent the inconvenience that a plurality of grid-connected inverters cannot be detected when they are connected to the same system 3. That is, when a plurality of grid-connected inverters detect a disconnection of grid 3, if each moves the reference waveform in a predetermined direction, each cancels each other, resulting in the output of the grid-connected inverter. You may not find a change. This embodiment prevents this, and realizes a grid interconnection inverter that can reliably detect a power failure even when a plurality of grid interconnection inverters are used.
[0029]
As described above, according to this embodiment, the delay unit 24 can reliably detect a power failure by determining the delay time according to the positive / negative of the comparison signal determined by the positive / negative determination unit 92, and a plurality of systems. A grid-connected inverter that can reliably detect a power failure and stop operation even when the grid-connected inverter is connected is realized.
[0030]
(Example 10)
Subsequently, a tenth embodiment of the present invention will be described. FIG. 10 is a block diagram showing the configuration of this embodiment. In this embodiment, the grid interconnection inverter 95 has an initial fluctuation comparing means 96, an integrated fluctuation comparing means 97, and an initial fluctuation / integrated fluctuation instructing means 98. The initial fluctuation comparison means 96 compares the frequency before the division with the system 3 and the frequency after the division, and shifts the phase of the reference waveform with respect to the delay means 24 when there is a frequency fluctuation exceeding an arbitrary standard value. Instruct. The integrated fluctuation comparing means 97 executes a comparison operation in response to an instruction from the initial fluctuation / integrated fluctuation instructing means 98, and the initial fluctuation comparing means 96 compares the signal from the first ZVP creating means 19. On the other hand, the signals from the second and subsequent ZVP creation means 19 are compared, and this signal is transmitted to the delay means 24. In the present embodiment, the delay means 24 integrates the signals from the integrated fluctuation comparing means 97 and delays the reference waveform signal received from the reference waveform generating means 17 according to the integration result.
[0031]
The operation of this embodiment will be described below. When the initial fluctuation comparing unit 96 detects the division of the system 3 based on the ZVP signal from the ZVP creating unit 19, a signal is output to the delay unit 24, and the delay unit 24 delays the reference waveform. As a result, when the frequency of the output voltage of the inverter means 16 shifts, the integrated fluctuation comparison means 97 detects this from the signal of the ZVP creation means 19 and outputs a signal to the delay means 24. Receiving the signal from the integrated fluctuation comparing means 97, the delay means 24 outputs the reference waveform with the phase shifted. At this time, the amount of phase shifted by the delay means 24 can be set differently when the delay means 24 receives a signal from the initial fluctuation comparison means 96 and when it receives a signal from the integration fluctuation means 97. Whether the delay means 24 receives the signal from the initial fluctuation comparison means 96 or the signal from the integration fluctuation comparison means 97 is determined by the initial fluctuation / integration fluctuation instruction means 98. The initial fluctuation / integrated fluctuation instruction means 98 validates the signal of the initial fluctuation comparison means 96 when the frequency fluctuation is the first time, and validates the output signal of the cumulative fluctuation comparison means 97 for the second and subsequent frequency fluctuations. And
[0032]
That is, in this embodiment, the signal to be compared by the initial fluctuation comparing means 96 is used to determine whether the signal is due to noise or due to a power failure of the system 3. That is, when the fluctuation range exceeds a predetermined value by the initial fluctuation comparison means 96, the delay means 24 delays the reference waveform signal received from the reference waveform generation means 17 by a short time. For example, in this embodiment, 1 μs is set. On the other hand, when the integrated fluctuation comparison means 97 detects that the fluctuation width exceeds a predetermined value, the delay means 24 delays the reference waveform signal received from the reference waveform generation means 17 by, for example, 5 μs. As a result, when the control means 30 detects a frequency fluctuation exceeding a predetermined value by the ZVP signal created by the ZVP creating means 19, the inverter means 16 is immediately stopped. Alternatively, the disconnector 21 is opened. That is, the control means 30 clearly grasps the power failure of the system 3 by the detection by the integrated fluctuation comparison means 97.
[0033]
As described above, according to this embodiment, both the initial fluctuation comparing means 96 and the integrated fluctuation comparing means 97 are used properly, so that malfunction due to noise can be prevented and the operation can be reliably stopped in the event of a power failure. It is said.
[0034]
【The invention's effect】
According to the invention described in claim 1, it prevents malfunction caused by noise, and realizes a system interconnection inverter can be stopped reliably operate during a power outage.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a grid interconnection inverter according to a first embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of a grid interconnection inverter according to a second embodiment of the present invention. 3 is a block diagram showing the configuration of a grid interconnection inverter according to a third embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of a grid interconnection inverter according to a fourth embodiment of the present invention. The block diagram which shows the structure of the grid connection inverter which is the 5th Example of this invention. FIG. 6 The block diagram which shows the structure of the grid connection inverter which is the 6th Example of this invention. FIG. 8 is a block diagram showing the configuration of a grid interconnection inverter according to a seventh embodiment of the present invention. FIG. 8 is a block diagram showing the configuration of a grid interconnection inverter according to the eighth embodiment of the present invention. 9 is a block diagram showing the configuration of the grid interconnection inverter that is the ninth embodiment. Click view [10] Tenth block diagram showing the configuration of a system interconnection inverter is a block diagram [11] conventional example showing a configuration of a system interconnection inverter according to the embodiment of the present invention Description of Reference Numerals]
DESCRIPTION OF SYMBOLS 11 Grid connection inverter 16 Inverter means 17 Reference waveform generation means 18 Voltage detection means 19 ZVP preparation means 20 Reference waveform period division means 21 Disconnector 22 Grid connection inverter 23 Comparison means 24 Delay means 30 Control means 31 Load 31 System Linkage inverter 32 Grid connection inverter 36 Reset means 41 Grid connection inverter 42 Band pass filter 51 Grid connection inverter 52 Band pass filter correction means 61 Grid connection inverter 62 50 Hz band pass filter 63 60 Hz band pass filter 64 50/60 Hz Switching means 71 System-connected inverter 72 Counter means 81 System-connected inverter 82 Timer means 91 System-connected inverter 92 Positive / negative determining means 95 System-connected inverter 96 Initial fluctuation comparing means 97 Product Change comparison means 98 initial change and cumulative change instruction means

Claims (1)

Based on the reference waveform of the reference waveform generating means, the inverter means for converting the DC input power to AC and outputting it to the system, the voltage detecting means for detecting the output voltage of the inverter means, and the output of the inverter means from the output of the voltage detecting means A ZVP generating means for outputting a signal indicating a zero volt phase of the voltage, and an initial fluctuation comparing means for comparing the current timing and the timing immediately before the zero volt phase output signal generated by the ZVP generating means. The integrated fluctuation comparison means for comparing the second and subsequent zero volt phase output signals, the initial fluctuation integration fluctuation instructing means for switching the initial fluctuation means and the cumulative fluctuation comparison means, and the zero volt compared by the initial fluctuation comparison means or the cumulative fluctuation comparison means. when the phase output signal exceeds a predetermined range, the integrated variation comparing means zero volt phase output signal is given If the initial fluctuation comparison means detects that the zero volt phase output signal exceeds the predetermined range, the reference waveform signal generated by the reference waveform generation means is delayed for a longer time. A grid interconnection inverter comprising: a delay unit configured to stop; and a control unit configured to stop the inverter unit when a frequency detected based on the ZVP signal generated by the ZVP generation unit exceeds an allowable value .

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