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JP4096741B2 - Semiconductor device - Google Patents

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Publication number
JP4096741B2
JP4096741B2 JP2003007994A JP2003007994A JP4096741B2 JP 4096741 B2 JP4096741 B2 JP 4096741B2 JP 2003007994 A JP2003007994 A JP 2003007994A JP 2003007994 A JP2003007994 A JP 2003007994A JP 4096741 B2 JP4096741 B2 JP 4096741B2
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Prior art keywords
semiconductor element
heat
circuit board
semiconductor
metal
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JP2004221381A (en
Inventor
一博 登
裕平 山下
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73265—Layer and wire connectors
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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Description

【０００１】
【発明の属する技術分野】
本発明は、半導体素子を有する半導体装置に関するもので、例えばモータ駆動用のトランジスタやダイオード等の半導体素子を有する半導体装置に関する。
【０００２】
【従来の技術】
近年、ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）やＭＯＳＦＥＴなどのパワー回路のスイッチング用半導体素子は、高性能及び高機能化に伴い発熱量が多くなり、熱に関する問題が発生している。従来の半導体素子のパッケージ構造を図５に示す。
【０００３】
図５は、トランジスタやダイオードの半導体素子パッケージに使用されているＴＯ２２０パッケージで、１Ａはトランジスタ、１Ｂはダイオード、２はＳｎＡｇＣｕ系はんだ、Ｐｂ系はんだ、ＡｕＳｎ系はんだ等に代表される高温はんだ、３は熱拡散板（銅）、４は金属ワイヤ（アルミ又は金）、５は金属リード、６はエポキシ樹脂、７は２次回路基板、８は回路基板上配線パターン、９ははんだ、１０は放熱板である。
【０００４】
以上のように構成されるＴＯ２２０パッケージについて、以下に説明する。
【０００５】
まず、トランジスタ１Ａ及びダイオード１Ｂの半導体素子１を、高温はんだ２により熱拡散板３に接続する。次に、金属ワイヤ４を用いて、トランジスタ１Ａとダイオード１Ｂとの間、及びこれらの半導体素子１と金属リード５との間を電気的に接合する。尚、通常、金属ワイヤ４は、アルミニウム線又は金線を使用する。例えば、金属ワイヤ４をアルミニウムで用いた場合、半導体素子１の電極はアルミニウムにより形成されているので、常温の状態で電極の表面におけるアルミニウムと、金属ワイヤ４のアルミニウムとを、超音波エネルギーを印加しながら圧接すると、それぞれのアルミニウム表面の酸化膜が除去され、接合が得られる。金属ワイヤ４を、銅にニッケルメッキした金属リード５まで引き回し、金属リード５にウエッジボンディング方式にて接合する。
【０００６】
そして、半導体素子１及び金属ワイヤ４の物理的保護と信頼性向上とを目的として、トランスファー成形技術又はインジェクション成形技術を用いて、半導体素子１、金属ワイヤ４及び熱拡散板３を覆って、エポキシ樹脂６による封止を行う。これらの工程により、半導体素子１、高温はんだ２、熱拡散板３、金属ワイヤ４、金属リード５及びエポキシ樹脂６により形成された、「ＴＯ―２２０」と呼ばれる電子部品が完成する。
【０００７】
次に、金属リード５が、２次回路基板７の挿入穴に挿入された状態で、２次回路基板７の上に電子部品「ＴＯ−２２０」を置き、２次回路基板７全体をディップ工法で、金属リード５と２次回路基板７上にある回路基板上配線パターン８とをはんだ９により、電気的かつ物理的に接合する。
【０００８】
ところで、上述の構成では、半導体素子１の表面温度は、エポキシ樹脂６の材料物性値であるガラス転移温度Ｔｇにより、使用温度制限が与えられる。そこで放熱性を高め、半導体素子の温度を下げるために、半導体素子１から発生した熱を、熱拡散板３、エポキシ樹脂６から放熱板１０への熱伝導を良くして改善しようとする取組みが多かった。
【０００９】
例えば、エポキシ樹脂を使用せず、半導体素子の放熱性を高める方法は、特許文献１に記載されたものが、一般的に知られている。この方法は、パッケージ基板と同一材料で放熱板を形成することを特徴としている。
【００１０】
【特許文献１】
特開平０１−１５１２５７号公報（第２−３頁、第１図）
【００１１】
【発明が解決しようとする課題】
しかしながら、上述した特許文献１の構造では、半導体素子の温度がパッケージ基板によく伝達し、パッケージ基板の温度が上昇する。その結果、パッケージ基板からの熱伝導により、リードフレームが温度上昇する。このため、リードフレームと外部の回路基板とを電気的かつ物理的に接合するはんだ接合部分において、温度上昇による接合信頼性の低下が問題になっている。
【００１２】
本発明は、上述の問題点を解決するためになされたもので、熱伝導抑制手段を設け、接合信頼性を向上させた半導体装置を提供することを目的とする。
【００１３】
【課題を解決するための手段】
この目的を達成するために本発明は、耐熱性の異なる複数種類の半導体素子と、これらの半導体素子を実装した回路基板とを有し、前記半導体素子の中で耐熱性の高い方の半導体素子の接続に熱伝導抑制手段を設けた構成としている。
【００１４】
これにより、半導体装置内部の熱伝導を抑制することが可能となり、接合信頼性を向上させた半導体装置を得ることができる。
【００１５】
【発明の実施の形態】
以下、図面を参照しながら本発明について説明をする。なお、各図において、同じ構成要素については同じ符号を付して、説明を省略する。
【００１６】
図１は、本発明の第１の実施の形態にかかる半導体装置を示しており、耐熱特性の異なる２つの半導体素子、ＳｉＣ半導体素子１１とＳｉ半導体素子１２とを混載させている。ＳｉＣ半導体素子１１の特徴は、４００℃でも動作する高耐熱性であり、Ｓｉ半導体素子１２と比較して低損失を実現している。Ｓｉ半導体素子１２は耐熱性が低く、１５０℃以下での使用に限定される。このように、特性の異なる半導体素子を同一パッケージに実装する場合、耐熱温度によって熱伝導抑制手段を変える必要がある。
【００１７】
熱伝導抑制手段の一例を、図２に示す。半導体素子１３は、モータ等の駆動機器への駆動電流のスイッチングに用いられ、発熱するため放熱処置が必要な駆動用半導体素子であり、トランジスタや、ダイオードから構成される。この半導体素子１３に突起電極１４を形成する。突起電極１４は、図示しない金属ボールを、１００〜３００℃の加熱と６０ｋＨｚの超音波を印加することにより、半導体素子１３に接合している。そして、回路基板１５の上にある金属配線と、再び熱と超音波により金属間接合し、電気的かつ物理的に接合を行なう。この時、突起電極１４の形状を０．３ｍｍφ〜１．０ｍｍφに変化させることにより、電気及び熱の流れを抑制することができる。すなわち、突起電極１４から流れる熱を、突起電極１４の形状、例えば大きさにより抑制している。
【００１８】
また、この状態で金属ワイヤ１６を接合する。金属ワイヤ１６はアルミまたは金で形成されており、半導体素子１３及び金属リード１７に対し、前述のアルミ線のウェッジボンディング工法や金ワイヤのボールボンディング工法により形成される。この時、金属ワイヤ１６の形状、例えば線径を変化させることにより熱伝導を抑制することができる。
【００１９】
さらに、回路基板１５は、回路基板内減圧空間１８と、絶縁材１９と、金属ケース２０を有しており、この状態で減圧雰囲気に投入し、金属ケース２０を圧接し、パッケージとして完成する。パッケージを大気状態に戻すと、金属ケース２０内は減圧された状態のため、金属ケース２０と回路基板１５との密着性は継続される。すなわち、半導体素子１３と回路基板１５との隙間部分は、減圧空間２１になるため、熱の輻射による伝達は少なくなっている。
【００２０】
そして、金属リード１７は、放熱手段である放熱板２２を介して２次回路基板２３上の配線パターン２４にはんだ２５により接続されている。
【００２１】
なお、半導体装置がトランジスタの場合、金属リード１７は３本以上ある。１本は半導体素子１３の下部電極と電気的に接合され、図２においては真中の金属リード１７に相当する。残り２本の金属リードは、半導体素子１３の上部にある２ヶ所の電極に接合され、図２においては左右の金属リード１７に相当する。
【００２２】
ここで、半導体素子１３が駆動状態である際の、熱の流れについて説明する。半導体素子１３は、１００Ｖ〜１５００Ｖの電圧をＯＮとＯＦＦするスイッチ素子である。このスイッチング動作において、損失が発生する。通常のＩＧＢＴなどの半導体素子では、印加電力に対し１０％は熱損失になる。熱は、電気的なスイッチング動作を行っている半導体素子１３全体から発生し、スイッチング動作を行っている限り発生するため、電気の変換ロスから発生した熱を適切に処理しないと、半導体素子１３の誤動作や破壊につながる。
【００２３】
しかしながら、はんだ２５接合部分は熱に弱いため、できる限り熱を流したくない。そこで、半導体素子１３の周囲を減圧空間２１に置き、外部への放熱を遮断する構成としている。このとき、半導体素子１３自身の温度上昇が問題となるが、半導体素子１３にＳｉを用いる場合は１２０℃〜２００℃を上限に、ＳｉＣを用いる場合は３００℃〜４００℃を上限に設計する。減圧空間２１は、魔法瓶と同様の効果を持つため、回路基板１５から金属リード１７への熱の流れを抑制するため、半導体素子１３の熱と金属リード１７との熱勾配が大きくなる。また、回路基板内減圧空間１８によって、同様の効果を得ることができる。この場合、半導体素子１３を実装した部分に回路基板内減圧空間１８を設けることで、より効果を高めることが可能となる。
【００２４】
さらに、２次回路基板２３上のはんだ２５接合部分の温度上昇を抑えるため、金属リード１７に対し、放熱板２２をかしめて接合している。これにより、回路基板１５から伝わった熱は、金属リード１７を伝導し、その一部は放熱板２２にて空気中に放熱され、残部がはんだ２５接合部に伝熱される。はんだ２５接合部は、接合される形状、基板材料、半導体駆動条件などで異なるが、最大温度が８０℃〜１２５℃になるように設計している。
【００２５】
このように、半導体素子１３に対し、熱伝導抑制手段を設けることによって、周囲への熱の影響を少なくするようにしている。これによって、図１に示すように特性の異なる２つの半導体素子、ＳｉＣ半導体素子１１とＳｉ半導体素子１２とを混載させている。すなわち、同一の回路基板１５に、耐熱性の高いＳｉＣ半導体素子１１は、突起電極１４を介し回路基板１５に接合して断熱効果を高め、また耐熱性の低いＳｉ半導体素子１２は、放熱促進手段として、下面電極の全面を回路基板１５に接合し、放熱性を良くしている。このような構造により、耐熱性のことなる半導体を同一パッケージに実装することができる。
【００２６】
熱伝導抑制手段の他の例を、図３に示す。図３において、２６は金属接触部、２７は金属リード押圧部であり、使用される電流が大きく、半導体素子１３のスイッチングロスが大きく、発熱量が多い場合に適用できる。半導体素子１３の下面電極の全面を用いて回路基板１５に接合しているので、許容電流値を上げることができ、したがって大きな電流を流すことができる。しかしながら、熱伝導も良くなるので、回路基板１５内の回路基板内減圧空間１８によって、断熱効果を得ている。半導体素子１３の温度が２００℃〜４００℃になると、図２で示した２００℃以下で使用するアルミ線や金線による接合が、金属の軟化や、半導体素子１３内部への金属拡散の増大により使用できなくなる。このため、半導体素子１３を金属リード押圧部２７により押圧することで、回路基板１５と金属リード押圧部２７との間に挟み込む。金属リード押圧部２７は、２００℃〜４００℃の温度に耐えるよう、接触部にはモリブデンを塗布している。これにより、熱応力が掛かっても接合部分が動くため、応力を開放することができる。
【００２７】
以上のように、半導体素子と回路基板との電気的接続を、従来の配線用ワイヤに変えて突起電極及び金属片を使用することにより、浮遊インダクタンスや導通抵抗の低減を図ることができ、装置全体の小型化を図ることもできる。さらに、金属片及び半導体素子を絶縁樹脂材にてモールドし、かつ回路基板、絶縁樹脂材、及び放熱部材を一体化することにより、半導体素子からの熱の放散を従来に比べて高めることができる。
【００２８】
なお、半導体素子の電極、並びに突起電極に金メッキを施すことで、これらの素材がアルミニウムにてなる場合であっても、半田接合を行うことが可能となる。また、半導体素子の電極の直下にバリア金属を設けることで、半導体素子、特に電極には金メッキを施す必要がなくなり、さらに、半導体素子の側面に保護材を設けることで、半導体素子の接合工程にて当該半導体素子の損傷を防止することが可能となる。
【００２９】
図４は、本発明の第２の実施の形態にかかる半導体装置を示しており、特性の異なる２つの半導体素子、ＳｉＣ半導体素子１１とＳｉ半導体素子１２とを、同一パッケージに実装する構造を示している。耐熱性の高いＳｉＣ半導体素子１１は、突起電極１４を介し、Ｓｉ半導体素子１２の上に積層されている。この時、突起電極１４の断面積を変化させることにより、ＳｉＣ半導体素子１１とＳｉ半導体素子１２との温度差を抑制することが可能となる。この構造により、複数のチップを小さな面積に実装することができ、また耐熱性により積層する場所を決めることができる。
【００３０】
また、複数の半導体素子を積層する場合、積層された半導体素子間も突起電極で接続することで、浮遊インダクタンスや導通抵抗の低減を図ることができる。
【００３１】
なお、熱の伝達は、材料物性である熱伝導係数と形状によって決定される。この熱の流れ易さや流れ難さを、一般的に熱抵抗Ｒ（℃／Ｗ）で定義している。熱抵抗の意味は電気的な抵抗と同様で、ある形状に与えた熱量（Ｗ）に対して、温度差（℃）が発生した場合、その物体が持っている特性のことを示し、熱抵抗が高いと熱を抑制する効果を持つ。そして、熱抵抗を高くするためには、熱伝導率の低い材料選定や、熱が流れ難い形状（例えば熱の流れる断面積が小さい、熱の流れる経路が長い等）、他の物質（空気や水）へ放熱する面積が少ない、及び放熱する他の物質が少ない（例えば真空断熱）等の方法がある。実施の形態で記載した突起電極や金属ワイヤの形状を工夫するということは、この熱抵抗を高めることを意味し、形状以外を工夫することによって、熱抵抗を高めても同様の効果が得られる。
【００３２】
【発明の効果】
以上のように本発明によれば、耐熱性の異なる複数種類の半導体素子と、これらの半導体素子を実装した回路基板とを有し、前記半導体素子の中で耐熱性の高い方の半導体素子の接続に熱伝導抑制手段を設けることで、放熱と断熱の効果を同一パッケージ内部に搭載することができ、装置構成に比べて積層する構造により小型化することができる。したがって、Ｓｉ半導体とＳｉＣ半導体を混載できるパッケージを提供することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施の形態にかかる半導体装置を示す図
【図２】熱伝導抑制手段を説明する図
【図３】熱伝導抑制手段を説明する図
【図４】本発明の第２の実施の形態にかかる半導体装置を示す図
【図５】従来の半導体素子のパッケージ構造を示す図
【符号の説明】
１１ ＳｉＣ半導体素子
１２ Ｓｉ半導体素子
１４ 突起電極
１５ 回路基板
１６ 金属ワイヤ
１７ 金属リード
１８ 回路基板内減圧空間
２０ 金属ケース
２２ 放熱板
２３ ２次回路基板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a semiconductor element, for example, a semiconductor device having a semiconductor element such as a transistor or a diode for driving a motor.
[0002]
[Prior art]
2. Description of the Related Art In recent years, semiconductor devices for switching power circuits such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs have generated a large amount of heat with high performance and high functionality, causing problems related to heat. A conventional package structure of a semiconductor device is shown in FIG.
[0003]
FIG. 5 shows a TO220 package used in a semiconductor element package of a transistor or a diode. 1A is a transistor, 1B is a diode, 2 is a high-temperature solder represented by SnAgCu solder, Pb solder, AuSn solder, etc. Is a heat diffusion plate (copper), 4 is a metal wire (aluminum or gold), 5 is a metal lead, 6 is an epoxy resin, 7 is a secondary circuit board, 8 is a wiring pattern on the circuit board, 9 is solder, 10 is heat dissipation It is a board.
[0004]
The TO220 package configured as described above will be described below.
[0005]
First, the semiconductor element 1 of the transistor 1 </ b> A and the diode 1 </ b> B is connected to the heat diffusion plate 3 with the high temperature solder 2. Next, the metal wire 4 is used to electrically join between the transistor 1A and the diode 1B and between the semiconductor element 1 and the metal lead 5. Usually, the metal wire 4 uses an aluminum wire or a gold wire. For example, when the metal wire 4 is made of aluminum, the electrode of the semiconductor element 1 is made of aluminum. Therefore, ultrasonic energy is applied between the aluminum on the surface of the electrode and the aluminum of the metal wire 4 at room temperature. When pressure welding is performed, the oxide film on each aluminum surface is removed, and bonding is obtained. The metal wire 4 is routed to a metal lead 5 that is nickel-plated on copper and joined to the metal lead 5 by a wedge bonding method.
[0006]
Then, for the purpose of physical protection and reliability improvement of the semiconductor element 1 and the metal wire 4, the semiconductor element 1, the metal wire 4 and the heat diffusion plate 3 are covered using a transfer molding technique or an injection molding technique, and an epoxy is formed. Sealing with resin 6 is performed. Through these steps, an electronic component called “TO-220” formed by the semiconductor element 1, the high-temperature solder 2, the thermal diffusion plate 3, the metal wire 4, the metal lead 5, and the epoxy resin 6 is completed.
[0007]
Next, in a state where the metal lead 5 is inserted into the insertion hole of the secondary circuit board 7, the electronic component “TO-220” is placed on the secondary circuit board 7, and the entire secondary circuit board 7 is dipped. Then, the metal lead 5 and the circuit board wiring pattern 8 on the secondary circuit board 7 are electrically and physically joined by the solder 9.
[0008]
By the way, in the above-described configuration, the surface temperature of the semiconductor element 1 is limited by the glass transition temperature Tg which is a material property value of the epoxy resin 6. Therefore, in order to improve heat dissipation and lower the temperature of the semiconductor element, there is an effort to improve the heat generated from the semiconductor element 1 by improving the heat conduction from the heat diffusion plate 3 and the epoxy resin 6 to the heat dissipation plate 10. There were many.
[0009]
For example, a method described in Patent Document 1 is generally known as a method for improving the heat dissipation of a semiconductor element without using an epoxy resin. This method is characterized in that the heat sink is formed of the same material as the package substrate.
[0010]
[Patent Document 1]
Japanese Patent Laid-Open No. 01-151257 (page 2-3, FIG. 1)
[0011]
[Problems to be solved by the invention]
However, in the structure of Patent Document 1 described above, the temperature of the semiconductor element is well transmitted to the package substrate, and the temperature of the package substrate rises. As a result, the lead frame rises in temperature due to heat conduction from the package substrate. For this reason, in the solder joint portion where the lead frame and the external circuit board are electrically and physically joined, a decrease in joint reliability due to a temperature rise has been a problem.
[0012]
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device provided with heat conduction suppression means and improved in junction reliability.
[0013]
[Means for Solving the Problems]
In order to achieve this object, the present invention includes a plurality of types of semiconductor elements having different heat resistances and a circuit board on which these semiconductor elements are mounted, and the semiconductor element having the higher heat resistance among the semiconductor elements. It is set as the structure which provided the heat conduction suppression means in these connections.
[0014]
Thereby, it becomes possible to suppress the heat conduction inside the semiconductor device, and it is possible to obtain a semiconductor device with improved junction reliability.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described with reference to the drawings. In each figure, the same constituent elements are denoted by the same reference numerals and description thereof is omitted.
[0016]
FIG. 1 shows a semiconductor device according to a first embodiment of the present invention, in which two semiconductor elements having different heat resistance characteristics, a SiC semiconductor element 11 and a Si semiconductor element 12, are mounted together. The SiC semiconductor element 11 is characterized by high heat resistance that operates even at 400 ° C., and realizes low loss compared to the Si semiconductor element 12. The Si semiconductor element 12 has low heat resistance and is limited to use at 150 ° C. or lower. Thus, when mounting semiconductor elements having different characteristics in the same package, it is necessary to change the heat conduction suppressing means depending on the heat-resistant temperature.
[0017]
An example of the heat conduction suppressing means is shown in FIG. The semiconductor element 13 is a driving semiconductor element that is used for switching a driving current to a driving device such as a motor, and that requires heat dissipation because it generates heat, and includes a transistor and a diode. A protruding electrode 14 is formed on the semiconductor element 13. The protruding electrode 14 is bonded to the semiconductor element 13 by heating a metal ball (not shown) at 100 to 300 ° C. and applying an ultrasonic wave of 60 kHz. Then, the metal wiring on the circuit board 15 is again bonded between the metals by heat and ultrasonic waves, and is electrically and physically bonded. At this time, the flow of electricity and heat can be suppressed by changing the shape of the protruding electrode 14 to 0.3 mmφ to 1.0 mmφ. That is, the heat flowing from the protruding electrode 14 is suppressed by the shape, for example, the size of the protruding electrode 14.
[0018]
In this state, the metal wire 16 is bonded. The metal wire 16 is made of aluminum or gold, and is formed on the semiconductor element 13 and the metal lead 17 by the above-described aluminum wire wedge bonding method or gold wire ball bonding method. At this time, heat conduction can be suppressed by changing the shape of the metal wire 16, for example, the wire diameter.
[0019]
Further, the circuit board 15 has a pressure reduction space 18 in the circuit board, an insulating material 19, and a metal case 20. In this state, the circuit board 15 is put into a reduced pressure atmosphere, and the metal case 20 is pressed to complete a package. When the package is returned to the atmospheric state, the inside of the metal case 20 is in a decompressed state, so that the adhesion between the metal case 20 and the circuit board 15 is continued. That is, the gap portion between the semiconductor element 13 and the circuit board 15 becomes the decompressed space 21, so that transmission due to heat radiation is reduced.
[0020]
The metal lead 17 is connected to a wiring pattern 24 on the secondary circuit board 23 by solder 25 via a heat radiating plate 22 which is a heat radiating means.
[0021]
When the semiconductor device is a transistor, there are three or more metal leads 17. One is electrically joined to the lower electrode of the semiconductor element 13 and corresponds to the middle metal lead 17 in FIG. The remaining two metal leads are joined to two electrodes on the upper part of the semiconductor element 13 and correspond to the left and right metal leads 17 in FIG.
[0022]
Here, the flow of heat when the semiconductor element 13 is in the driving state will be described. The semiconductor element 13 is a switch element that turns on and off a voltage of 100V to 1500V. In this switching operation, loss occurs. In a semiconductor element such as a normal IGBT, 10% of the applied power is a heat loss. Since the heat is generated from the entire semiconductor element 13 performing the electrical switching operation and is generated as long as the switching operation is performed, the heat generated from the conversion loss of electricity must be properly processed unless the semiconductor element 13 It leads to malfunction and destruction.
[0023]
However, since the solder 25 joint is vulnerable to heat, it is not desirable to flow heat as much as possible. Therefore, the periphery of the semiconductor element 13 is placed in the decompression space 21 to block heat radiation to the outside. At this time, the temperature rise of the semiconductor element 13 itself becomes a problem, but when Si is used for the semiconductor element 13, the upper limit is set to 120 ° C. to 200 ° C., and when SiC is used, the upper limit is set to 300 ° C. to 400 ° C. Since the decompression space 21 has the same effect as the thermos, the heat gradient from the semiconductor element 13 to the metal lead 17 is increased in order to suppress the flow of heat from the circuit board 15 to the metal lead 17. Moreover, the same effect can be acquired by the decompression space 18 in a circuit board. In this case, the effect can be further enhanced by providing the in-circuit-board decompression space 18 in the portion where the semiconductor element 13 is mounted.
[0024]
Furthermore, in order to suppress the temperature rise of the solder 25 joint portion on the secondary circuit board 23, the heat sink 22 is caulked and joined to the metal lead 17. Thereby, the heat transferred from the circuit board 15 is conducted through the metal lead 17, a part of which is radiated into the air by the heat radiating plate 22, and the remaining part is transferred to the solder 25 joint. The solder 25 joint portion is designed to have a maximum temperature of 80 ° C. to 125 ° C., depending on the shape to be joined, the substrate material, the semiconductor driving conditions, and the like.
[0025]
Thus, by providing the heat conduction suppressing means for the semiconductor element 13, the influence of heat on the surroundings is reduced. As a result, as shown in FIG. 1, two semiconductor elements having different characteristics, SiC semiconductor element 11 and Si semiconductor element 12, are mounted together. That is, the SiC semiconductor element 11 having high heat resistance is joined to the circuit board 15 via the protruding electrodes 14 on the same circuit board 15 to enhance the heat insulation effect, and the Si semiconductor element 12 having low heat resistance is a heat dissipation promoting means. As a result, the entire surface of the lower electrode is joined to the circuit board 15 to improve heat dissipation. With such a structure, a semiconductor having different heat resistance can be mounted in the same package.
[0026]
Another example of the heat conduction suppressing means is shown in FIG. In FIG. 3, reference numeral 26 denotes a metal contact portion and 27 denotes a metal lead pressing portion, which can be applied when a large current is used, a switching loss of the semiconductor element 13 is large, and a heat generation amount is large. Since the entire lower surface electrode of the semiconductor element 13 is joined to the circuit board 15, the allowable current value can be increased, and thus a large current can be passed. However, since heat conduction is also improved, a heat insulating effect is obtained by the reduced pressure space 18 in the circuit board in the circuit board 15. When the temperature of the semiconductor element 13 becomes 200 ° C. to 400 ° C., the bonding by the aluminum wire or the gold wire used at 200 ° C. or less shown in FIG. 2 is caused by the softening of the metal or the increase of the metal diffusion into the semiconductor element 13. Unusable. For this reason, the semiconductor element 13 is pressed between the circuit board 15 and the metal lead pressing portion 27 by being pressed by the metal lead pressing portion 27. The metal lead pressing portion 27 is coated with molybdenum on the contact portion so as to withstand a temperature of 200 ° C. to 400 ° C. Thereby, even if a thermal stress is applied, the joint portion moves, so that the stress can be released.
[0027]
As described above, by changing the electrical connection between the semiconductor element and the circuit board to the conventional wiring wire and using the protruding electrode and the metal piece, the floating inductance and the conduction resistance can be reduced. The overall size can also be reduced. Furthermore, by molding the metal piece and the semiconductor element with an insulating resin material and integrating the circuit board, the insulating resin material, and the heat dissipation member, heat dissipation from the semiconductor element can be increased as compared with the conventional case. .
[0028]
Note that by performing gold plating on the electrodes of the semiconductor element and the protruding electrodes, it is possible to perform solder bonding even when these materials are made of aluminum. In addition, by providing a barrier metal directly under the electrode of the semiconductor element, it is not necessary to apply gold plating to the semiconductor element, in particular, the electrode. Further, by providing a protective material on the side surface of the semiconductor element, the bonding step of the semiconductor element can be performed. Thus, damage to the semiconductor element can be prevented.
[0029]
FIG. 4 shows a semiconductor device according to a second embodiment of the present invention, and shows a structure in which two semiconductor elements having different characteristics, SiC semiconductor element 11 and Si semiconductor element 12, are mounted in the same package. ing. The SiC semiconductor element 11 having high heat resistance is stacked on the Si semiconductor element 12 via the protruding electrodes 14. At this time, it is possible to suppress the temperature difference between the SiC semiconductor element 11 and the Si semiconductor element 12 by changing the cross-sectional area of the protruding electrode 14. With this structure, a plurality of chips can be mounted in a small area, and the place to be stacked can be determined by heat resistance.
[0030]
In addition, when a plurality of semiconductor elements are stacked, stray inductance and conduction resistance can be reduced by connecting the stacked semiconductor elements with protruding electrodes.
[0031]
Note that the heat transfer is determined by the thermal conductivity coefficient and shape, which are material properties. The ease or difficulty of the heat flow is generally defined by the thermal resistance R (° C./W). The meaning of thermal resistance is the same as electrical resistance. When a temperature difference (° C) occurs with respect to the amount of heat (W) given to a certain shape, it indicates the characteristics of the object. High is effective in suppressing heat. In order to increase the thermal resistance, it is necessary to select a material with low thermal conductivity, a shape in which heat does not flow easily (for example, a small cross-sectional area through which heat flows, a long heat flow path, etc.), other substances (air or There are methods such as a small area that radiates heat to water) and a small amount of other substances that radiate heat (for example, vacuum insulation). Devising the shape of the bump electrode and metal wire described in the embodiment means increasing the thermal resistance, and by devising other than the shape, the same effect can be obtained even if the thermal resistance is increased. .
[0032]
【The invention's effect】
As described above, according to the present invention, a semiconductor element having a plurality of types of semiconductor elements having different heat resistances and a circuit board on which these semiconductor elements are mounted has a higher heat resistance among the semiconductor elements. By providing the heat conduction suppressing means for the connection, the effects of heat dissipation and heat insulation can be mounted in the same package, and the size can be reduced by the laminated structure as compared with the device configuration. Therefore, it is possible to provide a package in which a Si semiconductor and a SiC semiconductor can be mixedly mounted.
[Brief description of the drawings]
FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a diagram for explaining heat conduction suppression means. FIG. 3 is a diagram for explaining heat conduction suppression means. FIG. 5 is a diagram showing a semiconductor device according to a second embodiment of the present invention. FIG. 5 is a diagram showing a conventional package structure of a semiconductor element.
DESCRIPTION OF SYMBOLS 11 SiC semiconductor element 12 Si semiconductor element 14 Protruding electrode 15 Circuit board 16 Metal wire 17 Metal lead 18 Decompression space 20 in a circuit board Metal case 22 Heat sink 23 Secondary circuit board

Claims (3)

耐熱性の異なる複数種類の半導体素子と、これらの半導体素子を実装した回路基板とを有し、前記半導体素子の中で耐熱性の高い方の半導体素子を実装する接続部に熱伝導抑制手段を設けた半導体装置であって、前記熱伝導抑制手段として、前記半導体素子を実装した前記回路基板の部分に、減圧された空間である基板内減圧空間を設けたことを特徴とする半導体装置。  A plurality of types of semiconductor elements having different heat resistances, and a circuit board on which these semiconductor elements are mounted, and heat conduction suppressing means is provided at a connection portion for mounting the semiconductor element having the higher heat resistance among the semiconductor elements. A semiconductor device, wherein a reduced pressure space in the substrate, which is a reduced pressure space, is provided as a part of the circuit board on which the semiconductor element is mounted as the heat conduction suppressing means. 複数種類の半導体素子がＳｉ半導体素子とＳｉＣ半導体素子であることを特徴とする請求項１に記載の半導体装置。  The semiconductor device according to claim 1, wherein the plurality of types of semiconductor elements are a Si semiconductor element and a SiC semiconductor element. 熱伝導抑制手段として、半導体素子の周囲に減圧された空間を設けるケースを設けたことを特徴とする請求項１、２のいずれかに記載の半導体装置。  The semiconductor device according to claim 1, wherein a case for providing a decompressed space around the semiconductor element is provided as heat conduction suppressing means.
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