JP4093573B2 - Electric power steering device - Google Patents

Description

  The present invention relates to an electric power steering apparatus that assists a driver's steering operation with a motor, and in particular, communicates between a main CPU that controls a current detected by a motor current detecting means to match a target current, and the main CPU. The present invention relates to an electric power steering apparatus including a sub CPU that enables monitoring of a main CPU.

  The electric power steering device is provided with a motor drive prohibition means that prohibits the drive of the motor, and the motor that should assist the driver's steering operation is prohibited from generating a torque in the direction opposite to the direction of the steering torque that the driver applies to the steering handle. This is disclosed in Patent Document 1 below.

  Further, it is known that an electronic control unit of an electric power steering apparatus is provided with a main CPU (central processing unit) that controls the main motor and a sub CPU that monitors the main CPU. The prohibition function is shared by the sub CPU.

  The main CPU has a function to calculate the actual motor current in order to perform current feedback control to match the actual current flowing to the motor with the target current. Similarly, the sub CPU prevents the current prohibited by the motor drive inhibition function from flowing. Has a function to calculate the actual motor current. In both the main CPU and the sub CPU, the actual current of the motor is calculated based on the voltage difference between both ends of the shunt resistor connected to the H bridge circuit that drives the motor. Since a predetermined offset voltage is detected even when no current flows through the shunt resistor due to the change, the current value calibrated with this offset voltage is calculated as the actual current of the motor.

However, if the timing at which the main CPU calculates the offset voltage and the timing at which the sub CPU calculates the offset voltage are different, different offset voltages are calculated for the main CPU and the sub CPU due to fluctuations in the power supply voltage due to engine start-up. In order to prevent this, it is necessary to provide a communication function between the main CPU and the sub CPU, and to synchronize the calculation timings of the offset voltages of the main CPU and the sub CPU using this communication function.
JP 2000-190861 A

  However, if a communication function is provided between the main CPU and the sub CPU, it is necessary to diagnose whether or not the communication function is functioning normally. Further, after the diagnosis, an offset voltage is calculated between the main CPU and the sub CPU. Since it is necessary to perform communication for synchronizing timing, there is a problem that it takes time until the electric power steering functions normally after the engine is started.

  The present invention has been made in view of the above-described circumstances. While ensuring the synchronism of offset voltage calculation when the actual current of the motor is calculated by the main CPU and the sub CPU of the electric power steering apparatus, The purpose is to be able to check the communication function in a short time.

  In order to achieve the above object, according to the first aspect of the present invention, there is provided a motor for assisting a driver's steering operation, a motor current detecting means for detecting a current supplied to the motor, and a motor current detecting means. A main CPU that controls the detected current to match the target current, and a sub CPU that enables communication between the main CPU and monitors the main CPU. The main CPU and the sub CPU include motor current detection means. In the electric power steering apparatus that calculates the offset voltage of the motor current detection means for calibration, the main CPU transmits an offset voltage calculation request signal to the sub CPU in accordance with the timing at which the offset voltage is calculated. After that, the main CPU sends an offset voltage calculation completion signal from the sub CPU. An electric power steering device characterized in that when the time until transmission is within a predetermined time, it is determined that the communication function between the main CPU and the sub CPU and the offset voltage calculation function of the sub CPU are normal. Is proposed.

  The motor current detection circuit 49 of the embodiment corresponds to the motor current detection means of the present invention.

  According to the configuration of the first aspect, the main CPU transmits the offset voltage calculation request signal to the sub CPU in accordance with the timing for calculating the offset voltage of the motor current detecting means, and after the transmission is performed, the sub CPU receives the offset voltage calculation request signal. Check whether the time until the offset voltage calculation completion signal is received by the main CPU is within a predetermined time, and if it is within the predetermined time, the communication function between the main CPU and the sub CPU is normal, In addition, since it is determined that the offset voltage calculation function of the sub CPU is normal, the calculation of the offset voltage in the main CPU and the calculation of the offset voltage in the sub CPU can be reliably synchronized, and the calculation request signal and calculation Whether the communication function between the main CPU and the sub CPU is normal by using transmission / reception of the completion signal When, it is possible to offset the voltage calculating function of the sub CPU to confirm in a short time and whether it is normal.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below based on examples of the present invention shown in the accompanying drawings.

  1 to 6 show an embodiment of the present invention, FIG. 1 is an overall perspective view of an electric power steering apparatus, FIG. 2 is an enlarged sectional view taken along line 2-2 of FIG. 1, and FIG. FIG. 4 is a diagram showing a motor drive circuit, FIG. 5 is a diagram for explaining the operation at the time of normal rotation and reverse rotation of the motor, and FIG. 6 is a flowchart for explaining the fault diagnosis operation of the main CPU and sub CPU. is there.

  As shown in FIG. 1, the upper steering shaft 12 that rotates integrally with the steering handle 11 has a pinion shaft 17 that protrudes upward from the speed reducer 16 via an upper universal joint 13, a lower steering shaft 14, and a lower universal joint 15. Connected to. Tie rods 19 and 19 projecting from the left and right ends of the steering gear box 18 connected to the lower end of the speed reducer 16 are connected to knuckles (not shown) of the left and right wheels WL and WR. A motor M is supported on the reduction gear 16, and the operation of the motor M is controlled by a main CPU 61 to which a signal from a steering torque sensor St housed in the reduction gear 16 is input.

  2 and 3, the speed reducer 16 is coupled to the lower case 21 integrated with the steering gear box 18, the intermediate case 23 coupled to the upper surface thereof with bolts 22 ..., and the upper surface thereof coupled to the bolts 24 ... The pinion shaft 17 is rotatably supported by the steering gear box 18 and the upper case 25 by ball bearings 26 and 27. A pinion 28 provided at the lower end of the pinion shaft 17 meshes with a rack 30 provided on a rack bar 29 supported inside the steering gear box 18 so as to be movable left and right. A pressing member 31 is slidably accommodated in a through hole 18 a formed in the steering gear box 18, and the pressing member 31 is attached to the rack bar 29 by a spring 33 disposed between the nut member 32 closing the through hole 18 a. By biasing toward the back, the deflection of the rack bar 29 is suppressed.

  A rotation shaft 34 of the motor M extending inside the reduction gear 16 is rotatably supported by the lower case 21 by a pair of ball bearings 35 and 36, and a worm 37 provided on the rotation shaft 34 of the motor M is a pinion. It meshes with a worm wheel 38 fixed to the shaft 17.

  Therefore, when the motor M is driven, the torque of the rotating shaft 34 is transmitted to the pinion shaft 17 via the worm 37 and the worm wheel 38, and the driver's steering operation is assisted by the motor M.

  FIG. 4 shows a motor drive circuit C that drives the motor M in response to commands from the main CPU 61 and the sub CPU 62 connected thereto. The motor drive circuit C includes an H-bridge circuit 41, and the high-voltage terminal TH is connected to the plus pole 45a of the on-vehicle 12V battery 45 via the shunt resistor 42, the power relay 43 and the choke coil 44, and the low-voltage terminal The TL is grounded and connected to the negative electrode 45b of the battery 45. The first output terminal TM1 and the second output terminal TM2 of the H bridge circuit 41 are connected to the motor M, the low voltage terminal TL and the first output terminal TM1 are connected by the first switching element 46a, and the low voltage terminal TL and the second output terminal TM1 are connected. The output terminal TM2 is connected by the second switching element 46b, the high voltage terminal TH and the first output terminal TM1 are connected by the third switching element 46c, and the high voltage terminal TH and the second output terminal TM2 are connected by the fourth switching element 46d. The The first to fourth switching elements 46a to 46d are configured by, for example, field effect transistors (FETs). A fail safe relay 47 is disposed between one of the first output terminal TM1 and the second output terminal TM2 (first output terminal TM1 in the embodiment) and the motor M.

  The power relay 43 that turns on / off the supply of power from the battery 45 to the H bridge circuit 41 and the fail safe relay 47 that stops the motor M in the event of an abnormality are connected to a common relay drive circuit 48 that is controlled by the main CPU 61. The power relay 43 and the fail safe relay 47 are turned on / off in conjunction with each other. That is, when the power relay 43 is turned on, the fail safe relay 47 is also turned on, and when the power relay 43 is turned off, the fail safe relay 47 is also turned off, thereby reducing the cost and the failure rate of the relay drive circuit 48.

  A shunt resistor 42 disposed between the power relay 43 and the H bridge circuit 41 is connected to a motor current detection circuit 49, and the motor current detection circuit 49 connected to both the main CPU 61 and the sub CPU 62 is connected to the shunt resistor 42. Based on the potential difference between both ends and the resistance value of the shunt resistor 42, the current supplied from the battery 45 to the H bridge circuit 41 is detected.

  The potential VMN of the first output terminal TM1 and the potential VMP of the second output terminal TM2, that is, the potentials of both terminals of the motor M are detected by the motor terminal voltage detection circuit 50 connected to the main CPU 61. When the motor M is not operating, the potential VMN of the first output terminal TM1 and the potential VMP of the second output terminal TM2 are pulled up to 2V to 3V by the battery 45.

  The first to fourth switching elements 46 a to 46 d of the H bridge circuit 41 are duty-controlled by the switching element drive circuit 51. That is, as shown in FIG. 5A, when the first switching element 46a and the fourth switching element 46d at the diagonal positions are turned on, the first output terminal TM1 is connected to the low voltage terminal TL and becomes 0V. The motor M rotates forward by the 2 output terminal TM2 being connected to the high voltage terminal TH and becoming 12V. At this time, the current flowing through the motor M can be controlled by controlling the duty ratio of one of the first switching element 46a and the fourth switching element 46d.

  Further, as shown in FIG. 5B, when the second switching element 46b and the third switching element 46c at other diagonal positions are turned ON, the second output terminal TM2 is connected to the low voltage terminal TL and becomes 0V. When the first output terminal TM1 is connected to the high voltage terminal TH and becomes 12V, the motor M is reversely rotated. At this time, the current flowing through the motor M can be controlled by controlling the duty ratio of one of the second switching element 46b and the third switching element 46c.

  A motor drive prohibition circuit 52 is disposed between the main CPU 61 and the sub CPU 62 and the switching element drive circuit 51. The sub CPU 62 having a monitoring function of the main CPU 61 detects the direction of the steering torque detected by the steering torque detection means St. When the motor M is driven in the opposite direction for a predetermined time, the motor drive inhibition signal is sent to the switching element drive circuit 51 via the motor drive inhibition circuit 52. Is output.

  Incidentally, the main CPU 61 has a function of calculating the actual current of the motor M based on a signal from the motor current detection circuit 49 in order to perform current feedback control for matching the actual current flowing through the motor M with the target current. The CPU 62 has a function of calculating the actual current of the motor M based on the signal from the motor current detection circuit 49 in order to perform the motor drive prohibition control by the motor drive prohibition circuit 52 described above. Further, in order to calibrate the actual current of the motor M, the main CPU 61 and the sub CPU 62 offset the offset voltage output by the motor current detection circuit 49 during the initial process immediately after turning on the ignition switch (output voltage when the motor current does not flow). In order to avoid the influence of the voltage fluctuation of the battery 45, the calculation of the offset voltage in the main CPU 61 and the sub CPU 62 needs to be performed synchronously. Furthermore, the port Pm of the main CPU 61 and the port Ps of the sub CPU 62 are connected for mutual communication, and it is diagnosed whether the mutual communication is performed without any trouble during the initial process.

  Hereinafter, the synchronization operation of offset voltage calculation of the main CPU 61 and the sub CPU 62 and the diagnostic operation of the mutual communication function of the main CPU 61 and the sub CPU 62 will be described with reference to the flowchart of FIG.

  First, when the ignition switch is turned on in step S1, calculation of an offset voltage based on a signal from the motor current detection circuit 49 in the main CPU 61 is commanded in step S2. When calculation of the offset voltage is completed in step S3, In S4, an offset voltage calculation command signal is transmitted from the main CPU 61 to the sub CPU 62 by communication between the main CPU 61 and the sub CPU 62, and at the same time, a timer is started in step S5.

  When the calculation of the offset voltage in the sub CPU 62 is completed in the subsequent step S6, an offset voltage calculation completion signal is transmitted from the sub CPU 62 to the main CPU 61 through communication between the main CPU 61 and the sub CPU 62 in step S7. At this time, if the timer started in step S5 is not up in step S8, that is, if the offset voltage calculation completion signal is transmitted from the sub CPU 62 to the main CPU 61 within a predetermined time defined by the timer. In step S9, a normal determination is made. On the contrary, if the timer is up in step S8, that is, if the offset voltage calculation completion signal is not transmitted from the sub CPU 62 to the main CPU 61 within the predetermined time defined by the timer, the abnormality determination is made in step S10. Be defeated.

  As described above, when the normal determination is made in step S9, it is confirmed that the communication function between the main CPU 61 and the sub CPU 62 is normal and the calculation of the offset voltage in the sub CPU 62 is normally performed. In addition, since the calculation of the offset voltage in the main CPU 61 and the calculation of the offset voltage in the sub CPU 62 are performed in synchronization, the occurrence of an error in calculating the offset voltage between the main CPU 61 and the sub CPU 62 due to battery voltage fluctuation or the like is prevented. In addition, the communication function between the main CPU 61 and the sub CPU 62 is used to check whether or not the communication function between the main CPU 61 and the sub CPU 62 is normal, so that the ignition switch is turned on. Thus, the time required for the synchronization process and the confirmation process in the initial process can be shortened, and the function of the electric power steering apparatus can be exhibited quickly.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various design changes can be made without departing from the present invention described in the claims. It is.

  For example, in the embodiment, the offset voltage calculation request signal is transmitted to the sub CPU 62 after the offset voltage calculation in the main CPU 61 is completed. However, the offset voltage is calculated to the sub CPU 62 simultaneously with the offset voltage calculation request signal in the main CPU 61. A command may be transmitted.

Overall perspective view of electric power steering device 2-2 line enlarged sectional view of FIG. 3-3 sectional view of FIG. The figure which shows the drive circuit of the motor Action diagram for forward and reverse rotation of motor Flowchart explaining failure diagnosis action of main CPU and sub CPU

Explanation of symbols

49 Motor current detection circuit (motor current detection means)
61 Main CPU
62 Sub CPU
M motor

Claims (1)

The motor (M) that assists the steering operation of the driver, the motor current detection means (49) that detects the current supplied to the motor (M), and the current detected by the motor current detection means (49) match the target current. And a sub CPU (62) for monitoring the main CPU (61) by enabling communication between the main CPU (61) and the main CPU (61).
In the electric power steering apparatus in which the main CPU (61) and the sub CPU (62) respectively calculate the offset voltage of the motor current detecting means (49) in order to calibrate the motor current detecting means (49),
The main CPU (61) transmits an offset voltage calculation request signal to the sub CPU (62) at the timing when the offset voltage is calculated, and the offset voltage calculation from the sub CPU (62) is completed after the transmission is performed. When the time until the signal is received by the main CPU (61) is within a predetermined time, the communication function between the main CPU (61) and the sub CPU (62) and the offset voltage calculation function of the sub CPU (62) An electric power steering apparatus characterized by determining that the power is normal.

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