JP4087354B2 - 4x4 switch and 8x8 switch - Google Patents

Description

  The present invention relates to a multi-input multi-output switch that switches an input signal to an arbitrary output and outputs the multi-input multi-output switch that switches a signal path by turning on / off a field effect transistor (hereinafter abbreviated as FET). In particular, it relates to 4 × 4 switches and 8 × 8 switches.

  Single-pole n-throw (SPnT / single-pole n-throw) switches using FETs and n-pole n-throw (n-pole n-throw) switches are characterized by wide bandwidth, low power consumption, and high-speed switching speed. It is widely used for transmission / reception change-over switches of mobile terminals and multi-input / multi-output switch matrices for switching input signals to arbitrary outputs. For example, the following “Non-Patent Document 1” discloses a configuration of a 4-input 4-output switch (hereinafter referred to as 4 × 4 switch) shown in FIG.

In FIG. 24, this 4 × 4 switch includes four 2 × 2 switches 12 _{1 to} 12 ₄ and four transmission lines 5 _{21 to} 5 ₂₄ . Each 2 × 2 switch is configured using four SPDT (single pole double throw) switches each using a plurality of FETs. FIG. 25 shows a conventional example disclosed in the following “Patent Document 1” as the 2 × 2 switch.

The conventional 2 × 2 switch in FIG. 25 includes SPDT switches 9 ₁₁ , 9 ₁₂ , 9 ₂₁ , 9 ₂₂ at input terminals 1 ₁₁ , 1 ₁₂ and output terminals 2 ₁₁ , 2 ₁₂ , respectively. By connecting the switches with four interconnecting transmission lines 5 _{1 to} 5 ₄ , the switch operates as a switch matrix. Each SPDT switch is a series shunt FET configuration, for example, in the case of the SPDT switch _{9 11,} and a series FET 3 ₁₁ and the shunt _{FET 3 11S} and series FET 3 ₁₂ and the shunt _{FET 3 12S.}

The operation of this 2 × 2 switch is as follows.
A signal input from the input terminal 1 _{11 is} input to the SPDT switch 9 ₁₁ common terminal, and is a transmission line 5 ₁ that is a connection path to the SPDT switch 9 ₂₁ or a transmission line that is a connection path to the SPDT switch 9 ₂₂ . 5 is output to ₂ .

Similarly, the signal input from the input terminal _{1 12} is input to the common terminal of the SPDT switch _{9 12,} connection route to the transmission line ₃ or a connection route to the SPDT switch _{9 21} or SPDT switch _{9 22,} is output to the transmission line 5 ₄ is.

In SPDT switch _{9 21} is controlled to output either a signal from the transmission line _{5 1} or the transmission line ₃ to the output terminal _211, the SPDT switch _{9 22,} the transmission line _{5 2} or transmission lines It is controlled to output either one of the signal to the output terminal 2 ₁₂ from 5 _4.

Here, the gate bias of the FETs in the SPDT switches 9 ₁₁ and 9 ₂₁ is such that the series FET 3 ₁₁ and the shunt FET 3 _12S of the SPDT switch 9 _{11 and} the series FET 3 ₂₁ and the shunt FET 3 _{22S of} the SPDT switch 9 ₁₂ are controlled from the control terminal 6 _1. , series FET 3 ₁₂ of the SPDT switch _{9 11,} a shunt _{FET 3 11S} series FET 3 ₂₂ of the SPDT switch _{9 12,} which is to be applied to the common each shunt _{FET 3 21S} from the control terminal _{6 2.} Note that a same manner, can be applied to two control terminals ₆ 1, _{6 2} from the gate bias configured to output terminal _{2 11, 2 12} SPDT switch ₉ connected to the _{21, 9 22} in the FET.

The switch of the series shunt FET configuration controls the series FET to be ON and the shunt FET to be OFF when passing, and controls the series FET to be OFF and the shunt FET to be ON when the switch is cut off. Therefore, in the conventional example shown in FIG. 25, by applying complementary voltages to the control terminals _{6 1} and _{6 2,} (the output terminal _{2 12} from the input terminal _{1 11} from the output terminal _{2 11,} an input terminal _{1 12)} And (passage of input terminal 1 ₁₁ to output terminal 2 ₁₂ , input terminal 1 ₁₂ to output terminal 2 ₁₁ ) can be switched. Further, by providing the input / output terminals on opposite sides of the square arrangement shown in FIG. 25, the cascade connection is facilitated and the switch can be easily scaled up.

When applying this 2 × 2 switch to 4 × 4 switch shown in FIG. 24, the number of control terminals requires only eight, and the length of the transmission line 5 _{21-5 24} the same, and the 2 × 2 switch If 12 _{1 to} 12 ₄ have the same configuration, there is an advantage that the insertion loss and the signal passing time (passing phase) can be made uniform in all passing states that can be realized by this configuration. Will occur.

First, there is a problem that it does not operate as a complete 4 × 4 switch matrix. This is because _one of the signals input to the 2 × 2 switch 12 ₁ is always input to the 2 × 2 switch 124 _4, and one of the signals input to the 2 × 2 switch 12 ₂ is always to the 2 × 2 switch 12 ₃ . This is because the signal is not switched between the input 2 × 2 switches 12 ₃ and 12 ₄ . Therefore, among the 24 passage states necessary for the matrix operation, (input terminal 1 ₁ to output terminal 2 ₁ , input terminal 1 ₂ to output terminal 2 ₂ , input terminal 1 ₃ to output terminal 2 ₃ , input terminal 1 ₄ to 8 including the output terminal 2 ₄ ) cannot be realized.

Second, since the signal passing path is connected to the ground by the shunt FETs 3 _11S , 3 _12S , 3 _21S , and 3 _22S , a baseband signal having a logic level other than 0V cannot be passed. Is a point.

  Thirdly, since two SPDT switches are arranged for both the input and output of each 2 × 2 switch, the circuit scale is increased and the number of control line intersections is increased, resulting in isolation characteristics. It is a problem that will deteriorate.

  Fourth, if the scale of SPDT, which is the smallest unit switch, is further increased, it becomes impossible to make the gate bias common in the series shunt FET configuration, so gate bias control for each series / shunt FET Wires and control terminals are required, resulting in degradation of isolation characteristics due to an increase in the number of wiring intersections, and an increase in circuit scale and mounting difficulty due to an increase in the number of control terminals. is there.

  Fifth, when a switch is configured by MESFET or HEMT using a compound semiconductor such as GaAs, there is a problem that the positive power supply operation is difficult.

  What is important in the characteristics of the switch is the insertion loss of the ON path and the isolation of the OFF path. Of these, the insertion loss mainly depends on the ON resistance of the FET used, and the isolation mainly depends on the OFF capacitance of the FET. For this reason, MESFETs and HEMTs using compound semiconductors such as GaAs that can reduce the ON resistance and the OFF capacitance are frequently used as high frequency switching devices.

However, since MESFET and HFMT are generally depletion (normally on) type FETs, the threshold voltage (Vth) is a negative voltage. Therefore, when the drain and source potentials are automatically set to 0V by the shunt FET as in the conventional example, the FET is in the ON state when the gate bias is 0V, and is lower than Vth to turn the FET in the OFF state. A negative voltage is required, and a negative voltage generating circuit is required for the control circuit. In particular, in a portable terminal, since the negative voltage generation circuit occupies a large area for mounting, a positive power supply operation of the FET switch is strongly desired.
Japanese Patent Laid-Open No. 6-232604 MJ Schindler et al, "DC-20GHz NxM Passive Switches," IEEE Transactions on Microwave Theory and Techniques, vol.36, no.12, pp.1604-1613, Dec. 1988

  The object of the present invention is to solve the above-mentioned conventional problems, enable matrix operation, pass a baseband signal having a logic level other than 0V DC level, easily increase the scale, and perform positive power supply operation. It is to provide a possible switch.

To achieve the above object, in claim 1 of the present invention, and four signal input terminals, and five 2 × 2 switch of the first to fifth, and four signal output terminals, the two Transmission means, and each of the five 2 × 2 switches includes first and second input terminals and first and second output terminals, and the first and second 2 switches. Signals input to one input terminal are output to the first and second output terminals or the second and first output terminals, respectively, and the four signal input terminals are the first and second output terminals, respectively. Connected to the first and second input terminals of the 2 × 2 switch, and the first output terminal of the first 2 × 2 switch is connected to the first input terminal of the third 2 × 2 switch. And a first output terminal of the second 2 × 2 switch is connected to the third 2 × 2 switch. And the second output terminal of the first 2 × 2 switch is connected to the first input terminal of the fourth 2 × 2 switch, and the second 2 × 2 switch is connected to the second input terminal of the second 2 × 2 switch. The second output terminal of the two switches is connected to the second input terminal of the fourth 2 × 2 switch, and the first output terminals of the third and fourth 2 × 2 switches are the two output terminals. Respectively connected to one end of the transmission means, the second output terminals of the third and fourth 2 × 2 switches are respectively connected to the first and second input terminals of the fifth 2 × 2 switch; The four signal output terminals are connected to the other end of the two transmission means and the first and second output terminals of the fifth 2 × 2 switch, respectively, and pass signals passing through the transmission means. The time is set to be the same as the transit time of the signal passing through the fifth 2 × 2 switch. It stipulates.

  In claim 2, in the 4 × 4 switch according to claim 1, a configuration in which the four input terminals and the four output terminals are interchanged is defined.

  According to a third aspect of the present invention, in the 4 × 4 switch according to the first or second aspect, the insertion loss or gain of the transmission means is equal to the insertion loss or gain of the fifth 2 × 2 switch, and a desired bandwidth. It is stipulated that they are set to be the same.

  According to a fourth aspect of the present invention, in the 4 × 4 switch according to the first or second aspect, the first two resistors are further provided, and the first two resistors are respectively connected to the two transmission units. Connected in series, the total insertion loss or gain of each of the resistors and transmission means connected in series is set to be the same as the insertion loss or gain of the fifth 2 × 2 switch in the desired band. It stipulates that

  In a fifth aspect of the present invention, in the 4 × 4 switch according to any one of the first to fourth aspects, each of the first to fifth 2 × 2 switches includes at least two single-pole double-throw switches. It stipulates the configuration used.

  According to a sixth aspect of the present invention, in the 4 × 4 switch according to the fifth aspect of the present invention, the single-pole double-throw switch is defined as a micromechanical switch.

  According to a seventh aspect of the present invention, in the 4 × 4 switch according to the fifth aspect, the single-pole double-throw switch is constituted by at least two FETs.

According to claim 8, in the 4 × 4 switch according to claim 7, the 2 × 2 switch includes first and second two single-pole double-throw switches and first to fourth four switches. The single-pole double-throw switch is composed of two FETs, one of which is connected to a common terminal and the other is connected to two terminals other than the common terminal. One end of each of the first and second transmission lines is connected to two terminals other than the common terminal of one single-pole double-throw switch, and two terminals other than the common terminal of the second single-pole double-throw switch are connected to each other. One end of each of the third and fourth transmission lines is connected, and the first and second input terminals or the first and second output terminals of the 2 × 2 switch are connected to the first and second single terminals, respectively. Connected to the common terminal of the pole double throw switch, Two switch first and second output terminals or first and second input terminals are connected to the other ends of the first and third transmission lines and to the other ends of the second and fourth transmission lines. Each connected configuration is defined.

  According to claim 9, in the 4 × 4 switch according to claim 7, the 2 × 2 switch includes first and second two single-pole double-throw switches, first two connection means, The single-pole double-throw switch comprises two FETs each having one of its drain or source connected to a common terminal and the other connected to two terminals other than the common terminal. The first and second input terminals or the first and second output terminals of the 2 × 2 switch are respectively connected to the common terminals of the first and second single-pole double-throw switches, Two terminals other than the common terminal of the first single-pole double-throw switch and two terminals other than the common terminal of the second single-pole double-throw switch are arranged so as to face each other at a predetermined interval, and face each other. Of the first single-pole double-throw switch Two terminals other than the communication terminal and two terminals other than the common terminal of the second single-pole double-throw switch are respectively connected by the first two connection means, and the second two connection means are connected to one end. Is connected to the first and second output terminals or the first and second input terminals of the 2 × 2 switch, and the other end is connected to the first two connection means, respectively, and one of the second connection means Defines a configuration intersecting with the first connection means that is not connected to the second connection means.

  According to a tenth aspect of the present invention, in the 4 × 4 switch according to any one of the first to ninth aspects, each group further includes 1 to 5 groups of second resistors each including four resistors, and at least One of the four resistors belonging to each of the groups, one end of which is connected to the control terminal, and the other end of the first and second 2 × 2 switches. Two input terminals, or first and second output terminals of the first and second 2 × 2 switches, and first and second input terminals of the third and fourth 2 × 2 switches, or It defines the configuration connected to at least one of the first and second output terminals of the third and fourth 2 × 2 switches or the four signal output terminals.

  According to an eleventh aspect, in the 4 × 4 switch according to the tenth aspect, four resistors belonging to at least one of the first to fifth groups are replaced with four inductors.

  In a twelfth aspect of the present invention, in the 4 × 4 switch according to the tenth aspect, the second four resistors are parallel to the connection means or the transmission means between the connection means or the transmission means. It was set as the structure to arrange.

  In a thirteenth aspect of the present invention, the 4 × 4 switch according to any one of the first to twelfth aspects further includes four capacitors, and the four capacitors are connected in series to the four input terminals. Connected configuration.

  In the fourteenth aspect, the 4 × 4 switch according to any one of the tenth to twelfth aspects further includes eight capacitors, and the four signal input terminals and the four signal output terminals are provided with: Each of the eight capacitors is connected in series.

  In Claim 15, The 4 * 4 switch in any one of Claim 1 thru | or 14 WHEREIN: Each said 1st-5th 2 * 2 switch, or said 1st and 2nd 2 * 2 switch Or the third and fourth 2 × 2 switches, or the fifth 2 × 2 switch and the first resistor and the transmission means, or the fifth 2 × 2 switch and the first resistor. Either the circuit including the first to fourth 2 × 2 switches excluding the transmission means or the entire 4 × 4 switch is integrated on a semiconductor substrate.

The sixteenth aspect of the present invention includes eight signal input terminals, first to fifth five 4 × 4 switches, eight signal output terminals, and four transmission means. The x4 switch includes four first to fourth input terminals and four first to fourth output terminals, respectively, and signals input to the first to fourth input terminals are respectively The eight signal input terminals are output to any one of the first to fourth output terminals, and the eight signal input terminals are respectively connected to the first to fourth input terminals of the first and second 4 × 4 switches. And the first and second output terminals of the first 4 × 4 switch are connected to the first and second input terminals of the third 4 × 4 switch, respectively, and the second 4 × 4 switch The first and second output terminals of the four switch are connected to the third and fourth input terminals of the third 4 × 4 switch, respectively. The third and fourth output terminals of the first 4 × 4 switch are respectively connected to the first and second input terminals of the fourth 4 × 4 switch, and the second 4 × 4 switch is connected to the second 4 × 4 switch. The third and fourth output terminals of the x4 switch are connected to the third and fourth input terminals of the fourth 4x4 switch, respectively, and the third and fourth 4x4 switches are connected to the third and fourth input terminals, respectively. The first and second output terminals are respectively connected to one ends of the four transmission means, and the third and fourth output terminals of the third and fourth 4 × 4 switches are the fifth 4 × 4, respectively. The eight signal output terminals are connected to the first to fourth input terminals of the switch, respectively, and the other one end of the four transmission means and the first to fourth of the fifth 4 × 4 switch. Each signal connected to the output terminal and passing through the transmission means passes through the fifth switch. Defines that was set to be the same as the transit time of issue.

  In the seventeenth aspect, in the 8 × 8 switch according to the sixteenth aspect, the eight input terminals and the eight output terminals are interchanged.

  In Claim 18, in the 8 × 8 switch according to any one of Claims 16 to 17, the insertion loss or gain of the transmission means is the insertion loss or gain of the fifth 4 × 4 switch; It is defined that the same band is set in a desired band.

  According to a nineteenth aspect of the present invention, in the 8 × 8 switch according to any one of the sixteenth to eighteenth aspects, a third four resistors are further provided, and the third four resistors are the four transmissions. And the total insertion loss or gain of the respective series-connected resistor and the transmission means is substantially equal to the insertion loss or gain of the fifth 4 × 4 switch and the desired bandwidth. That they are set to be the same.

  According to Claim 20, in the 8 × 8 switch according to any one of Claims 16 to 19, each of the first to fifth 4 × 4 switches includes at least four single-pole four-throws (SP4T). ) It stipulates that it is configured using a switch.

  According to a twenty-first aspect, in the 8 × 8 switch according to the twentieth aspect, the single-pole four-throw switch is constituted by a micro mechanical switch.

  According to a twenty-second aspect, in the 8 × 8 switch according to the twenty-second aspect, the single-pole four-throw switch includes at least four or more FETs.

  23. The 8 × 8 switch according to claim 22, wherein the 4 × 4 switch includes four single-pole four-throw switches, a first four connection means, and a second four connections. And a third four connection means having three connection points including both ends. The single-pole four-throw switch has one of its drain or source connected to a common terminal and the other connected to a common terminal. The four single-pole four-throw switches are each composed of four FETs connected to the other four terminals, and each of the four single-pole four-throw switches forms a first and second switch pair comprising two single-pole four-throw switches. The single-pole four-throw switches of the switch pair are arranged so that the four terminal sides other than the common terminals face each other at a predetermined interval, and the single-pole four-throw switches of the first switch pair face each other. Between the four terminals, the first The four connection means are respectively connected, and the four terminals facing each other of the single-pole four-throw switch of the second switch pair are respectively connected by the second four connection means, and the 4 × 4 Four input terminals or four output terminals of the switch are arranged on one side of the 4 × 4 switch, and one connection point of both ends of the third four connection means is the square arrangement of the 4 The other two connection points of the third connection means are connected to the four input terminals or the four output terminals arranged on one side of the × 4 switch, respectively. It defines the configuration in which one different connection means among the connection means and one different connection means among the second four connection means are connected.

According to Claim 24, in the 8 × 8 switch according to any one of Claims 16 to 23, at least one of the first to fifth 4 × 4 switches is any one of Claims 1 to 9. 26. In the 25 × 8 switch according to any one of claims 16 to 24, each set further includes eight resistors. The eight resistors belonging to each set are connected to the control terminal at one end, and the other end is connected to the control terminal. The first to fourth input terminals of the first and second 4 × 4 switches, or the first to fourth output terminals of the first and second 4 × 4 switches, respectively, or the third and First to fourth input terminals of a fourth 4 × 4 switch; Others are defined for connected to each said third and first to fourth output terminals of the fourth 4 × 4 switches or the eight signal output terminals, at least one.

  According to a twenty-sixth aspect, in the 8 × 8 switch according to the twenty-fifth aspect, eight resistors belonging to at least one of the first to fifth groups are replaced with eight inductors.

  According to Claim 27, in the 8 × 8 switch according to Claim 25, the fourth eight resistors are arranged in parallel to the connection means or the transmission means between the connection means or between the transmission means. It is configured.

  According to a twenty-eighth aspect of the present invention, in the 8 × 8 switch according to any one of the sixteenth to twenty-seventh aspects, the apparatus further includes eight capacitors, and the eight capacitors are respectively connected in series to the eight signal input terminals. It is set as the structure connected to.

  29. The 8 × 8 switch according to claim 25, further comprising 16 capacitors, wherein the 16 signal input terminals and the 8 signal output terminals respectively have the 16 capacitors. The configuration is such that a plurality of capacitors are connected in series.

  30. The 8 × 8 switch according to any one of claims 16 to 29, wherein each of the first to fifth 4 × 4 switches or the first and second 4 × 4 switches is provided. Or the third and fourth 4 × 4 switches, or the fifth 4 × 4 switch and the first resistor and the transmission means, or the fifth 4 × 4 switch and the first resistor. It defines a configuration in which either a circuit including first to fourth 4 × 4 switches excluding the transmission means or an entire 8 × 8 switch is integrated on a semiconductor substrate.

In addition to the 4 × 4 switch and the 8 × 8 switch according to the present invention, each unit switch is composed of five 2 × 2 switches and 4 × 4 switches combined with a plurality of transmission means and resistors. The SPDT switch and the SP4T switch constituting the 2 × 2 switch and the 4 × 4 switch are configured by only the series FET, and only one FET passes through each 2 × 2 switch and the 4 × 4 switch. For this reason, in addition to realizing a complete switch matrix operation, a baseband signal having a logic level other than 0V can be passed. Therefore, it greatly contributes to the small size and high performance of Ethernet (registered trademark) switches and routers. In addition, since positive power supply operation is possible, it is possible to contribute to miniaturization and high performance of the wireless communication terminal.

[First Embodiment]
FIG. 1 is a diagram showing a 4 × 4 switch according to the first embodiment of the present invention. This 4 × 4 switch, a 4 × 4 switch of the prior art shown in FIG. 24, has a configuration obtained by adding a 2 × 2 switch 12 ₅ and the transmission line _{5 25, 5 26.} Here, the 4 × 4 switch of the present embodiment is preferably a 2 × 2 switch 12 ₁ and 12 ₂ , and a 2 × 2 switch 12 ₃ and a 2 × 2 switch 12 ₄ are 2 × 2 switches having the same configuration. Each 2 × 2 switch is configured such that the amplitude and phase of the signal passing through them are the same.

  The operation of this 4 × 4 switch will be described focusing on the difference from the conventional example.

The difference between the prior art example shown in the first embodiment and FIG. 24, by adding a 2 × 2 switch 12 _5, to be able to realize the transmissivity of 24 kinds necessary for a complete matrix operation simultaneously, by the same transit time of the transmission line 5 _25, 5 transit time ₂₆ signal passing through the 2 × 2 signal passing through the switch 12 _5, signal transit time in all of the passing state of the 24 ways (passing phase ).

This is in addition to the addition of the 2 × 2 switch 12 ₅ can realize the transmissivity of the two types, the delay time of the signal passing through the 2 × 2 switch 12 _5, can be compensated by the transmission line _{5 25, 5 26} Because. Note that the present invention is not limited to the embodiment illustrated in FIG. 1, and the signal input terminal and the signal output terminal may be replaced with each other.
[Second Embodiment]
FIG. 2 is a diagram showing a 4 × 4 switch according to the second embodiment of the present invention. The second embodiment is different from the first embodiment illustrated in FIG. 1 in that resistors 4 ₂₅ and 4 ₂₆ having the same resistance value are added. The second embodiment will be described centering on differences from the first embodiment.

This in 4 × 4 switch of the second embodiment, there is resistance 4 _25, 4 the most important feature in that by adding ₂₆ having the same resistance value. For example, 2 and insertion loss of × 2 switch 12 _5, by setting the resistance _{4 25} and the transmission line _{5 25} connected in series, and the resistor _{4 26} and the insertion loss of the transmission line _{5 26} the same, 24 ways It is possible to make the insertion loss or gain uniform in all the passing states.

When the switch illustrated in FIG. 2 is integrated on a semiconductor substrate, the entire circuit of FIG. 2 can be integrated, but 2 × 2 switches 12 _{1 to} 12 ₄ and transmission lines 5 _{21 to} 5 are integrated. the configuration portion _24, it is also possible to separately integrate each configured portion and at the 2 × 2 switch 12 _5, and the transmission line 5 ₂₅ and 5 _26.
Without being limited to the embodiments, instead of applying the resistor 4 _25, 4 _26, by adjusting the conductor width and conductor thickness of the transmission line 5 _25, 5 _26, in the desired band, 2 × 2 it may be configured to implement the same insertion loss and the switch 12 _5. Further, as illustrated in FIG. 3, the signal input terminal and the signal output terminal may be replaced.
[Third Embodiment]
FIG. 4 is a diagram showing a 4 × 4 switch according to the third embodiment of the present invention.

The third embodiment specifically exemplifies the embodiment of the 2 × 2 switches 12 _{1 to} 12 _{5 in} the second embodiment illustrated in FIG. In the third embodiment, since the 2 × 2 switches 12 _{1 to} 12 ₅ have the same configuration, the 2 × 2 switch 12 ₁ will be described as a representative.

The 2 × 2 switch 12 ₁ includes two input and output terminals, two SPDT switches 9 ₁ and 9 ₂ , first transmission lines 5 ₁₁ and _512, and second transmission lines 5 ₂₁ and 5, respectively. ₂₂ . SPDT switch ₉ 1, _{9 2} are the same configuration, when the SPDT switch _{9 1,} and two _{FFT3 11, 3 12,} formed of the two resistors ₄ 11 connected to the gate of the _{FET, 4 12} The Here, one of the sources or drains of the FETs 3 ₁₁ and 3 ₁₂ is connected to the common terminal to constitute an SPDT switch. Further, the first transmission line _{5 12} and the second transmission line _{5 22} crosses the wiring intersection portion 11 _1. The resistance values of the resistors 4 ₁₁ and 4 ₁₂ are set to a very large value as compared with the characteristic impedance of the input / output, and one ends of the resistors 4 ₁₁ and 4 ₂₁ and the resistors 4 ₁₂ and 4 ₂₂ are Control terminals 6 ₁₁ and 6 ₁₂ are connected to each other. Preferably, the resistance values of the resistors 4 ₁₁ , 4 ₂₁ , 4 ₁₂ , and 4 ₂₂ are the same, and the first transmission lines 5 ₁₁ , 5 ₁₂ and the second transmission lines 5 ₂₁ , 5 ₂₂ The length is also set to the same value. The line length is preferably set to 1/36 or less of the in-line wavelength.

The operation of this 2 × 2 switch is as follows. Signal input from the input terminal _{1 1} is connected via a first transmission line _{5 11, 5 12,} the drain of the SPDT switch ₉ FET 3 ₁₁ drain or source in the ₁ and SPDT switch ₉ in ₂ FET 3 ₂₂ or Input to the source. Signal input from the input terminal _{1 2,} through the second transmission line _{5 21, 5 22, SPDT FET3} 21 drain or the source of the switch ₉ in _2, and the drain of the FET 3 ₁₂ of the SPDT switch ₉ in _one or Input to the source. Even if the input terminals 1 ₁ and 1 ₂ are arranged on one side of the 2 × 2 switch 12 ₁ , the signal can be input to both the SPDT switch 9 ₁ and the SPDT switch 9 ₂ in this way. ₁₂ and because the second transmission line _{5 22} intersect in the wiring intersection portion 11 _1. Such cross is for example, an overlay structure sandwiching a dielectric or an insulator, a first transmission line 5 ₁₂ and an air bridge wiring in the wiring intersection portion 11 ₁ one of the second transmission line 5 ₂₂ This can be realized.

Here, the gate biases of the FETs 3 ₁₁ and 3 ₂₁ are commonly applied from the control terminal 6 ₁₁ , and the gate biases of the FETs 3 ₁₂ and 3 ₂₂ are commonly applied from the control terminal 6 ₁₂ . Therefore, by applying a complementary voltage to the control terminals 6 ₁₁ and 6 ₁₂ , the FETs 3 ₁₁ and 3 ₂₁ can be simultaneously turned on or off, and the FETs 3 ₁₂ and 3 ₂₂ can be simultaneously turned off or on. Therefore, 2 × 2 of (input terminal 1 ₁ to transmission line 5 ₂₁₁ , input terminal 1 ₂ to transmission line 5 ₂₂₁ ) or (input terminal 1 ₁ to transmission line 5 ₂₂₁ , input terminal 1 ₂ to transmission line 5 ₂₁₁ ). Switch matrix operation can be realized.

Here, the (transmission line _{5 211} from the input terminal _{1 1,} from the input terminal _{1 2} transmission line _{5 221)} when the pass condition of the first transmission line _{5 12} and the second transmission line _{5 22} each FET 3 _{22 312 When} the drain or source terminal is in an open (open) state (passage from the input terminal 1 ₁ to the transmission line 5 ₂₂₁ , the input terminal 1 ₂ to the transmission line 5 ₂₁₁ ), the first transmission line 5 ₁₁ Since the second transmission line 5 ₂₁ is open at the drain or source ends of the FETs 3 ₁₁ and 3 ₂₁ , the length of these transmission lines is not negligible compared to the wavelength of the operating frequency band. In some cases, the switch characteristics deteriorate as an open stub.

FIG. 5 shows a simulation of this situation. Insertion loss relative to the length of the first and second transmission lines (5 ₁₁ , 5 ₁₂ , 5 ₂₁ , 5 ₂₂ ) on the horizontal axis (wavelength in the line) and the vertical axis as the reference when the transmission line length is zero The amount of degradation, reflection loss, and isolation are plotted. From this figure, it can be seen that as the transmission line becomes longer, the effect of the open stub appears gradually, the insertion loss increases, and the reflection loss decreases. On the other hand, isolation is improved by turning over the reduction in reflection loss. For example, when the length of the transmission line is set to 1/36 or less of the in-line wavelength, the deterioration of the reflection loss can be suppressed to 3.5 dB, and the deterioration of the insertion loss can be suppressed to 0.12 dB or less.

  The main differences between the conventional example shown in FIG. 25 and the present embodiment are that the SPDT switch is composed of only a series FET, and the number of required SPDT switches is halved. By removing the shunt FET, the signal path can be disconnected from the ground, so that a baseband signal having a logic level other than 0V can be passed. Along with halving the number of required SPDT switches, it is possible to achieve high isolation and circuit size reduction by halving the number of required control lines. In the 2 × 2 switch of the third embodiment, since the signal passes through only one FET, in order to realize the same insertion loss, compared with the conventional example shown in FIG. One having twice the ON resistance value of each FET can be applied. Therefore, since the required gate width of each FET can be halved, the circuit can be further miniaturized. The downsizing of the 2 × 2 switch section is extremely effective for downsizing the entire switch circuit, particularly when a large-scale switch is configured by cascading a plurality of 2 × 2 switches as in this embodiment. is there.

In the 4 × 4 switch embodiment shown in FIG. 4, preferably, the transmission line _{5 25, 5 26} and 2 × 2 switch 12 ₅ in the transmission line _{(5 91,} 5 _{92, 5 101,} 5 ₁₀₂ ) are set to the same length. Accordingly, the 2 × 2 switches 12 _{1 to} 12 ₅ have the same configuration, and the signal passing times (passing phases) are made uniform in the passing states of all 24 4 × 4 switch matrix operations. be able to. Furthermore, the resistance of the resistor _{4 25} and _{4 26, FET3 91, 3 92} , 3 101, 3 by the ₁₀₂ same ON resistance of the can to align the insertion loss in all the pass state 24 ways Become.

Note that without being limited to the embodiments illustrated in FIG. 4, a configuration in which interchanged signal input and output terminals, one or more 2 × 2 switch of the five 2 × 2 switch 12 ₁ to 12 ₅ May be reversed left or right or rotated 180 degrees.
[Fourth Embodiment]
FIG. 6 is a diagram showing a 4 × 4 switch according to the fourth embodiment of the present invention.

The fourth embodiment specifically illustrates the embodiment of the 2 × 2 switches 12 _{1 to} 12 ₅ in the second embodiment illustrated in FIG. 2, and is illustrated in FIG. 4. An embodiment different from the third embodiment is provided. In the fourth embodiment, since the 2 × 2 switches 12 _{1 to} 12 ₅ all have the same configuration, the 2 × 2 switch 12 ₁ will be described as a representative. Further, the difference from the third embodiment illustrated in FIG. 4 will be mainly described.

2 × 2 switch 12 ₁ is composed of a 2 by one of the input and output terminals, respectively, at a common terminal other than the two terminals arranged in the oppositely each other two SPDT switches 9 _1, 9 _2. SPDT switch ₉ 1, _{9 2} are the same configuration, when the SPDT switch _{9 1,} two _{FET 3 11, 3 12,} formed of the two resistors ₄ 11 connected to the gate of the _{FET, 4 12} The Here, one of the sources or drains of the FETs 3 ₁₁ and 3 ₁₂ is connected to the common terminal to constitute an SPDT switch. The resistance values of the resistors 4 ₁₁ and 4 ₁₂ are set to a very large value compared to the characteristic impedance of the input / output. One end of each of the resistors 4 ₁₁ and 4 ₂₁ and the resistors 4 ₁₂ and 4 ₂₂ is It is connected to the control terminal _{611, 6 12.} Preferably, the resistance values of the resistors 4 ₁₁ , 4 ₂₁ , 4 ₁₂ , and 4 ₂₂ are set to be the same.

In the fourth embodiment, the drain or source terminal sides of the FETs 3 ₁₁ and 3 ₁₂ and 3 ₂₁ and 3 _{22 in} the SPDT switches 9 ₁ and 9 ₂ are arranged facing each other at a predetermined interval. a FET 3 ₁₁ and _{3 22} drain or source terminal of, the FFT3 _{12 3 21} drain or source terminal of, in addition to each be connected to one another, intersect FET 3 _{12, 3} and ₂₁ the drain or source terminal of, the the most important feature that connects the FET 3 ₁₁ and 3 drain or source terminal and the signal input terminal 1 ₁ of ₂₂ connected to each other. Note that, by this intersection, the input / output terminals of the 2 × 2 switch can be arranged to face each other. In the fourth embodiment, the connection length between the SPDT switches 9 ₁ and 9 ₂ can be shortened compared to the third embodiment illustrated in FIG. And downsizing of the circuit can be achieved.

In the 4 × 4 switch embodiment shown in FIG. 6, preferably the length of the transmission line _{5 25, 5 26,} the transit time of the signal passing through the transmission line _{5 25, 5 26,} 2 × the average value of the transit time of the signal passing through the second switch 1 ₂₅ is set to be the same. Accordingly, in addition to having the same configuration for each of the 2 × 2 switches 12 _{1 to} 12 ₅ , the signal passing time (passing phase) is set in the passing state of all 24 4 × 4 switch matrix operations. Can be almost identical. Furthermore, the resistance of the resistor _{4 25} and _{4 26, FET3 91, 3 92} , 3 101, 3 by the ₁₀₂ same ON resistance of the can to align the insertion loss in all the pass state 24 ways Become.

It should be noted that the present invention is not limited to the embodiment illustrated in FIG. 6, and a configuration in which signal input / output terminals are replaced or one or more 2 × 2 switches of 2 × 2 switches 12 _{1 to} 12 ₅ are horizontally reversed. Alternatively, it may be configured to rotate 180 degrees or turn 180 degrees by turning left and right.
[Fifth Embodiment]
7 to 11 are diagrams showing a 4 × 4 switch according to the fifth embodiment of the present invention. This 4 × 4 switch of the fifth embodiment, FIG. 2, the configuration added to 4 × 4 switch of the second embodiment illustrated in FIG. 3, a resistor _{4 121-4 124} and a control terminal _{6 6} It has become. The resistance values of the resistors 4 ₁₂₁ to 4 ₁₂₄ are sufficiently larger than the input / output characteristic impedance, and are preferably set to the same value.

The embodiment shown in FIGS. 7 to 10 has a configuration capable of producing the same effect, although the connection locations of the resistors 4 ₁₂₁ to 4 ₁₂₄ are different. Resistance _{4 121-4 124} downstream of the 2 × 2 switch ₁₂ 3, 12 ₄ in the embodiment of FIG. 7, in the embodiment of FIG. 8 of the 2 × 2 switch 12 _5, and the transmission path _{5 25 5 26} downstream, upstream of the 2 × 2 switches ₁₂ 1, 12 ₂ in the embodiment of Figure 9 obtained by rearranging the signal input and output terminals, to the subsequent 2 × 2 switches ₁₂ 1, 12 ₂ in the embodiment of FIG. 10, Each is arranged. FIG. 11 specifically illustrates an embodiment of the 2 × 2 switches 12 _{1 to} 12 _{5 in} the embodiment illustrated in FIG. 7, and therefore FIG. 11 will be described as a representative.

In the illustrated embodiment in FIG. 11, one end of the resistor _{4 121-4 124} 2 × 2 connected to output terminals of the switch ₁₂ 3, 12 _4, most major that the other end thereof is connected to the control terminal _{6 6} Features.

The SPDT switches in the 2 × 2 switches 12 _{1 to} 12 ₅ are all composed of series FETs, and the 2 × 2 switches 12 _{1 to} 12 ₅ perform ON / OFF control of each FET so as to operate a switch matrix. the control terminal _{6 6} through the resistor _{4 121-4 124} from, it is possible to apply a bias voltage to the source / drain of the 2 × 2 all FET switches ₁₂ 1 to 12 _5. Therefore, even when a depletion (normally on) FET having a negative threshold voltage (Vth) is used, the source / drain potential of the FET can be raised, and a positive power supply operation is possible. This makes it possible to apply MESFETs and HEMTs using compound semiconductors such as GaAs, which have the features of low ON resistance and low OFF capacity, to 4 × 4 switches that operate with positive power supply. Performance can be achieved.

Moreover, if passing a signal including a DC component, suppressed by the variation in DC level due to the 2 × 2 switches 12 ₁ to 12 ₄ in ON resistance of FET, a bias voltage is applied from the control terminal 6 ₆ It is also possible to do. This voltage drop occurring when passing through the FET, is because it becomes possible to compensate by a bias voltage from the control terminal 6 _6.

FIG. 12 shows an embodiment of a pattern layout in the vicinity of the resistors 4 ₁₂₁ to 4 ₁₂₄ in FIG. 11, and the coplanar lines 8 ₁ to 8 ₄ are connected to the subsequent stage of the 2 × 2 switches 12 ₃ and 12 _4. This is an example.

The most important feature of the embodiment shown in FIG. 12 is that the resistors 4 ₁₂₁ to 4 ₁₂₄ are arranged approximately in the middle of the center conductor and the ground conductor of the coplanar line so that the longitudinal directions thereof are parallel to each other. It is.

In the embodiment shown in FIG. 11, since the output terminals of the 2 × 2 switches 12 ₃ and 12 ₄ are connected to each other by the resistors 4 ₁₂₁ to 4 ₁₂₄ , the signal also leaks through these resistors. . Since this leakage causes an increase in insertion loss and deterioration of isolation, it is desirable that the resistance values of these resistors be as large as possible.

  Generally, the resistance value of a resistor formed on a semiconductor substrate is uniquely determined by the ratio of length to width. For example, when the sheet resistance value is 100Ω, a resistance of 1 kΩ can be formed if the ratio of length to width is 10, and a resistance of 10 kΩ can be formed if the ratio is 100. Therefore, as the elongated resistor is used, a larger resistance value can be realized.

Therefore, by adopting the pattern layout as shown in FIG. 12, the resistance values of the resistors 4 ₁₂₁ to 4 ₁₂₄ can be increased without intersecting with the central conductor and the ground conductor, so that the insertion loss caused by these resistors can be reduced. Increase and degradation of isolation can be greatly suppressed.

Note that the present invention is not limited to the embodiment illustrated in FIG. 12, and a configuration using another transmission line such as a microstrip line instead of the coplanar line may be used. Also, four, eight, or twelve resistors different from the resistors 4 ₁₂₁ to 4 ₁₂₄ are provided, and a plurality of connection locations are provided by connecting other than the output terminals of the 2 × 2 switches 12 ₃ and 12 ₄ . It does not matter if it is configured. Further, a configuration in which a part or all of the 2 × 2 switches 12 _{1 to} 12 ₅ are replaced with the 2 × 2 switches illustrated in FIG. 4, or one or more of the 2 × 2 switches 12 _{1 to} 12 ₅ A configuration may be adopted in which the × 2 switch is reversed left and right or rotated 180 degrees or reversed left and right and rotated 180 degrees.
[Sixth Embodiment]
FIG. 13 is a diagram showing a 4 × 4 switch according to the sixth embodiment of the present invention.

The 4 × 4 switch of the sixth embodiment has a configuration in which capacitors 7 _{1 to} 7 ₄ are added to the 4 × 4 switch of the fifth embodiment illustrated in FIG. Note capacitance value of the capacitor 7 _{1-7 4} is adapted its impedance is sufficiently small values as compared to the characteristic impedance of the input and output in a desired signal band are preferably set to the same value. If the capacitors 7 _{1 to} 7 ₄ are externally configured by individual components, a capacitor having a large capacitance value can be easily applied, so that a signal having a low frequency component close to direct current can be passed through without deterioration. become.

In the illustrated embodiment in FIG. 13, the most important feature in that the four capacitors 7 _{1-7 4} input terminals 1 ₁ to 1 ₄ are connected respectively in series.

With such a configuration, the baseband signal can be level-shifted to an arbitrary DC level and output. By applying a voltage of brass to the control terminal 6 ₆ can output a signal having a positive DC offset voltage, so that it is possible to output a signal having a negative DC offset voltage by applying a negative voltage . Therefore, it is possible to output the input baseband signal by shifting the level of the DC offset voltage to +0.5 V, −0.5 V or the like, for example, in accordance with the interface of the device connected to the subsequent stage.

Note that without being limited to the embodiments illustrated in FIG. 13, a part or all of the 2 × 2 switches 12 ₁ to 12 ₅ structure and is replaced by the 2 × 2 switch illustrated in FIG. 4, 2 × The configuration may be such that one or more 2 × 2 switches among the two switches 12 _{1 to} 12 ₅ are rotated left and right or reversed 180 degrees or reversed left and right and rotated 180 degrees. Further, it may be in the form of a capacitor 7 _{1-7 4} were respectively connected in series to the signal input terminal of the 4 × 4 switch illustrated in FIGS. 8 to 10. For the purpose of passing a signal having no DC component, the signal output terminals 2 ₁ to 2 ₄ may have capacitors connected in series.
[Seventh embodiment]
FIG. 14 is a diagram showing an 8 × 8 switch according to the seventh embodiment of the present invention. This 8 × 8 switch has a signal input terminal ₁ 1 to 1 _8, 4 × 4 switch _{131-134 5,} a first transmission line _{5 21-5 28,} the second transmission line _{5 29-5 32} And signal output terminals 2 ₁ to 2 ₈ . Each 4 × 4 switch includes four input terminals and four output terminals, respectively, and can output signals input to the four input terminals to any one of the four output terminals. It has the same function as the 4 × 4 switch illustrated in FIG.

Signal input terminals ₁ 1 to 1 _8, 4 × 4 is connected to an input terminal of the switch ₁₃ 1, 13 _2, 4 × 4 switches 13 ₁ and 13 ₂ of the output terminals, a first transmission line _{5 21-5 28} Are connected to two input terminals of 4 × 4 switches 13 ₃ and 13 ₄ respectively. 4 × 4 switch ₁₃ 3, 13 2 by one of the _four output terminals are connected to the input terminal of the 4 × 4 switch 13 _5, and the remaining 2 by one, the second transmission line _{5 29-5 32} Is connected to one end. Signal output terminal ₂ 1 to 2 ₈ is connected to four output terminals of the other end 4 × 4 switch 13 ₅ of the second transmission line _{5 29-5 32.}

Incidentally, preferably, 4 × 4 switches 13 ₁ and 13 _2, and 4 × 4 switch 13 ₃ and 13 ₄ are composed of the same 4 × 4 switches each, the first transmission line _{5 21-5 28} and the second The transmission lines 5 _{29 to} 5 ₃₂ are configured such that the amplitude and phase of signals passing through them are the same. Moreover, transit time of the signal passing through the second transmission line 5 _{29-5 32} is configured so as to be the same as the transit time of the signal passing through the 4 × 4 switch 13 _5.

This embodiment has a configuration obtained by extending the 8 × 8 switch 4 × 4 switch shown in FIG. 1, a 4 × 4 switch 13 ₅ on the output side of the second transmission line 5 _{29-5 32} The most important feature is the provision. Thus, similar to the 4 × 4 switch shown in FIG. 1, all the passing states necessary for the 8 × 8 switch matrix operation can be realized, and at the same time, the signal passing time (passing phase) in all the passing states can be realized. Can be aligned.

Note that the present invention is not limited to the embodiment illustrated in FIG. 14, and a configuration in which the signal input terminal and the signal output terminal are replaced may be employed.
[Eighth Embodiment]
FIG. 15 is a diagram showing an 8 × 8 switch according to the eighth embodiment of the present invention.

The eighth embodiment is different from the seventh embodiment illustrated in FIG. 14 in that resistors 4 ₂₉ to 4 ₃₂ having the same resistance value are added. The eighth embodiment will be described centering on differences from the seventh embodiment.

The 8 × 8 switch of the eighth embodiment has the most main feature in that resistors 4 ₂₉ to 4 ₃₂ having the same resistance value are added. For example, 4 × insertion loss of the four switch 13 _5, by setting the resistor _{4 29} which are respectively connected to the serial transmission line _{5 29,} resistor _{4 30} and the insertion loss of such transmission line _{5 30} the same, all It is possible to make the insertion loss or gain uniform in the passing state.

Note that without being limited to the embodiments illustrated in Figure 15, instead of applying the resistor _{4 29-4 32,} by adjusting the conductor width and conductor thickness of the transmission line _{5 29-5 32,} desired in the band it may be adapted to realize the same insertion loss and 4 × 4 switch 13 _5. Further, as illustrated in FIG. 16, the signal input terminal and the signal output terminal may be interchanged.
[Ninth Embodiment]
FIG. 17 is a diagram showing an 8 × 8 switch according to the ninth embodiment of the present invention. This embodiment specifically exemplifies the embodiment of 4 × 4 switches 13 _{1 to} 13 ₅ in the eighth embodiment illustrated in FIG. In this embodiment, since the 4 × 4 switches 13 _{1 to} 13 ₅ have the same configuration, the 4 × 4 switch 13 ₁ will be described as a representative. In FIG. 17, for example, in the 4 × 4 switches 13 _1, at the intersection between the first transmission line _{5 11-5 16} and the second transmission line _{5 21-5 26,} blacked out circle marks the connection The circles that represent gray with a dot pattern indicate intersections without being connected.

4 × 4 switch 13 ₁ is composed of four SP4T switches ₁₀ 1 to 10 ₄ and the like. SP4T switches ₁₀ 1 to 10 ₄ have the same configuration, when the SP4T switches 10 _1, four _{FET 3} 11 _{to 3 14,} consists of four resistors _{4 11-4 14} connected to the gates of the FET The Here, one of the sources or drains of the FETs 3 _{11 to} 3 ₁₄ is connected to the common terminal to constitute an SP4T switch. The resistance values of the resistors 4 ₁₁ to 4 ₁₄ are set to a very large value compared to the input / output characteristic impedance, and preferably set to the same resistance value. The gate bias control line and the control terminal are not shown.

In the present embodiment, the drain or source terminal side of each FET in the SP4T switches 10 ₁ and 10 ₄ forming the first switch pair and the SP4T switches 10 ₂ and 10 ₃ forming the second switch pair is determined in advance. arranged to oppositely each other at intervals, the drain or source terminals of the FET, which face each other, that connects the first transmission line _{5 11-5 16} respectively in the second transmission line _{5 21-5 26} in addition, the first transmission line _{5 11-5 16} between the second transmission line _{5 21-5 26,} respectively to choose one by one place from the first switch pair and a second pair of switches, the third and transmission line _{5 31-5 34} most important features that are connected with the.

  With such a configuration, the interconnection of each SP4T switch can be made extremely compact and the connection length thereof can be made very short, so that the switch can be reduced in size, reduced in loss, and widened in bandwidth.

Further, by applying the fourth transmission line _{5 35-5 37} enables connection to the 4 × 4 switch 13 ₁ of the collected signals to the one side input terminal ₁ 1 to 1 _4, 4 × 4 switch Facilitates cascade connection.

  Here, the first and second transmission lines and the third and fourth transmission lines are configured to cross each other except at the connection point. Such an intersection may be, for example, an overlay structure with a dielectric or insulator sandwiched therebetween, or one of the first transmission line and the second and third transmission lines as an air bridge wiring at the wiring intersection. Can be realized. In this embodiment, since the SP4T switch is composed of only the series FET, the signal path can be disconnected from the ground, so that it is possible to pass a baseband signal having a logic level other than DC level of 0V. . Compared with the configuration of the conventional example shown in FIG. 25, the 4 × 4 switch, which is a unit switch, can be configured so that only one switch (SP4T switch) through which a signal passes is required, thereby reducing the number of required switches. Miniaturization of the circuit can be achieved. In addition, since the number of required control lines can be greatly reduced by the configuration with only series FETs and the reduction in the number of required switches, high isolation and a reduction in circuit size can be realized. Furthermore, compared to the conventional configuration example shown in FIG. 25, the required gate width of each FFT can be halved, so that the circuit can be further reduced in size. The downsizing of the 4 × 4 switch section is extremely effective for downsizing the entire switch circuit, particularly when a large-scale switch is configured by cascading a plurality of 4 × 4 switches as in this embodiment. is there.

In the 8 × 8 switch embodiment shown in FIG. 17, preferably the length of the transmission line _{5 29-5 32} includes a transit time of the signal passing through the transmission line _{5 29-5 32,} 4 × It is set so that the average value of the transit time of the signal passing through the 4 switch ₁₃₅ is the same. As a result, the 4 × 4 switches 13 _{1 to} 13 ₅ have the same configuration, and the signal passing time (passing phase) is substantially the same in all 8 × 8 switch matrix operations. can do. Furthermore, the resistance value of the resistor _{4 29-4 32,} by the same ON resistance value of 4 × 4 FET switch 13 _5, it is possible to align the insertion loss in all the pass state.

It should be noted that the present invention is not limited to the embodiment illustrated in FIG. 17, and the configuration in which the signal input / output terminals are replaced or one or more of the 4 × 4 switches 13 _{1 to} 13 ₅ are reversed left or right or 180 degrees. You may be the structure rotated 180 degree | times by rotating or reversing right and left. Further, one or more 4 × 4 switches among the 4 × 4 switches 13 _{1 to} 13 ₅ may be replaced with the 4 × 4 switches shown in FIGS. 1 to 4 and 6. In this case, there is an advantage that the number of required control terminals can be reduced.
[Tenth embodiment]
18 to 22 are diagrams showing an 8 × 8 switch according to the tenth embodiment of the present invention.

8 × 8 switch of the embodiment, FIG. 15, the 8 × 8 switch of the eighth embodiment illustrated in FIG. 16, the resistor _{4 331-4 338} and a control terminal _{6 6} becomes added structure Yes. The resistance values of the resistors 4 ₃₃₁ to 4 ₃₃₈ are sufficiently larger than the input / output characteristic impedance, and are preferably set to the same value.

The embodiment shown in FIGS. 18 to 21 has a configuration capable of producing the same effect, although the connection locations of the resistors 4 ₃₃₁ to 4 ₃₃₈ are different. Resistance _{4 331-4 338,} downstream of the 4 × 4 switch ₁₃ 3, 13 ₄ in the embodiment of Figure 18, the 4 × 4 switch 13 _5, and the transmission line _{5 29-5 32} in the embodiment of FIG. 19 downstream, upstream of the 4 × 4 switches ₁₃ 1, 13 ₂ in the embodiment of Figure 20 obtained by rearranging the signal input and output terminals, to the subsequent 4 × 4 switches ₁₃ 1, 13 ₂ in the embodiment of FIG. 21, Each is arranged. FIG. 22 specifically illustrates the embodiment of the 4 × 4 switches 13 _{1 to} 13 _{5 in} the embodiment illustrated in FIG. 18, and therefore FIG. 22 will be described as a representative.

In the illustrated embodiment in FIG. 22, the resistance _{4 331-4 338} one end of 4 × 4 switch ₁₃ 3, 13 ₄ output terminals respectively connected, most major that the other end thereof is connected to the control terminal _{6 6} Features.

The SP4T switches in the 4 × 4 switches 13 _{1 to} 13 ₅ are all composed of series FETs, and the 4 × 4 switches 13 _{1 to} 13 ₅ perform ON / OFF control of each FET so as to operate a switch matrix. , via a resistor _{4 331-4 338} from the control terminal _{6 6,} it is possible to apply a bias voltage to the source or drain of any FET of 4 × 4 switches _{131-134 5.} Therefore, even when a depletion (normally on) type FET having a negative threshold voltage (Vth) is used, the potential of the source or drain of the FET can be raised, and a positive power supply operation is possible. This makes it possible to apply MESFETs and HEMTs using compound semiconductors such as GaAs, which have the features of low ON resistance and low OFF capacity, to 8 × 8 switches that operate with positive power supply, and reduce the size and height of the device. Performance can be achieved.

Moreover, if passing a signal including a DC component, suppressed by the variation in DC level due to the 4 × 4 switches 13 ₁ to 13 ON resistance of the FET _4, a bias voltage is applied from the control terminal 6 ₆ It is also possible to do. This voltage drop occurring when passing through the FET, is because it becomes possible to compensate by a bias from the control terminal 6 _6.

The resistors 4 ₃₃₁ to 4 ₃₃₈ are preferably laid out in a pattern similar to that illustrated in FIG. As a result, the resistance values of the resistors ₄₃₃₁ to ₄₃₃₈ can be increased without intersecting with the central conductor and the ground conductor, so that the increase in insertion loss and the deterioration of isolation caused by these resistors can be greatly suppressed. Is possible.

Note that the present invention is not limited to the embodiment illustrated in FIG. 22, and the configuration in which the signal input / output terminals are replaced or one or more of the 4 × 4 switches 13 _{1 to} 13 ₅ are reversed left or right or 180 degrees. You may be the structure rotated 180 degree | times by rotating or reversing right and left. Further, with different eight or 16 or 24 resistors and the resistor _{4 331-4 338,} by connecting the other output terminal of the 4 × 4 switch ₁₃ 3, 13 _4, provided with a plurality of connecting portions It does not matter if it is configured. Further, one or more 4 × 4 switches among the 4 × 4 switches 13 _{1 to} 13 ₅ may be replaced with the 4 × 4 switches shown in FIGS. 1 to 4 and 6. In this case, there is an advantage that the number of required control terminals can be reduced.
[Eleventh embodiment]
FIG. 23 is a diagram showing an 8 × 8 switch according to the eleventh embodiment of the present invention.

The 8 × 8 switch of the present embodiment has a configuration in which capacitors 7 _{1 to} 7 ₈ are added to the 8 × 8 switch of the tenth embodiment illustrated in FIG. Note capacitance value of the capacitor 7 _{1-7 8,} has a sufficiently small value as compared to the characteristic impedance of the input and output its impedance in the signal band, it is preferably set to the same value. If the capacitors 7 _{1 to} 7 ₈ are externally configured by individual components, a capacitor having a large capacitance value can be easily applied, so that a signal having a low frequency component close to direct current can be passed through without deterioration. become.

The embodiment illustrated in FIG. 23 is characterized in that eight capacitors 7 _{1 to} 7 ₈ are connected in series to input terminals 1 ₁ to ₁₈ , respectively.

With such a configuration, the baseband signal can be level-shifted to an arbitrary DC level and output. By applying a voltage of the positive to the control terminal 6 ₆ can output a signal having a positive DC offset voltage, so that it is possible to output a signal having a negative DC offset voltage by applying a negative voltage . Therefore, it is possible to output the input baseband signal by shifting the level of the DC offset voltage to +0.5 V, −0.5 V or the like, for example, in accordance with the interface of the device connected to the subsequent stage.

Note that without being limited to the embodiments illustrated in Figure 23, was connected to the capacitor ₇ 1-7 ₈ to the input terminal ₁ 1 to 1 ₈ of 8 × 8 switch illustrated in FIGS. 19 to 21 in series The configuration may be possible, and one or more of the 4 × 4 switches 13 _{1 to} 13 ₅ may be horizontally reversed or rotated 180 degrees or horizontally reversed and rotated 180 degrees. Further, one or more 4 × 4 switches among the 4 × 4 switches 13 _{1 to} 13 ₅ may be replaced with the 4 × 4 switches shown in FIGS. 1 to 4 and 6. In this case, there is an advantage that the number of required control terminals can be reduced. For the purpose of passing a signal having no DC component, the output terminals 2 ₁ to 2 ₈ may be connected in series with capacitors.
[Other embodiments]
The SPDT switch and the SP4T switch in the 4 × 4 switch and the 8 × 8 switch exemplified in this embodiment may be configured by a micro mechanical switch (MEMS / Micro-Electro-Mechanical Switch) instead of the FET. In this case, the loss of the switch and the high isolation can be achieved, although there is a demerit that the control voltage is increased and the switching time is delayed as compared with the configuration using the FET.

  Further, part or all of the 4 × 4 switch and the 8 × 8 switch exemplified in this embodiment are preferably integrated on a semiconductor substrate. The scale of the circuit to be integrated takes into account the required number of input / output terminals, the number of control terminals, the circuit size, etc. Two switch circuits, two switch circuits on the output side, four switches on the input / output side, or a fifth switch and two transmission means, or a resistance connected in series to these two transmission means The circuit can be easily mounted on the package depending on the situation of the peripheral circuit.

  Furthermore, the present invention is not limited to the 4 × 4 switch and the 8 × 8 switch exemplified in the present embodiment, and may be a switch with more inputs and more outputs. For example, if an 8 × 8 switch is used as a unit switch and a method similar to the 4 × 4 switch exemplified in the present embodiment is applied, it can be easily analogized that a 16 × 16 switch can be configured.

The circuit block diagram which shows the 4x4 switch of 1st Embodiment. The circuit block diagram which shows the 4x4 switch of 2nd Embodiment. The circuit block diagram which shows the 4 * 4 switch of the modification of 2nd Embodiment. The circuit block diagram which shows the 4x4 switch of 3rd Embodiment. The characteristic view by simulation of 2x2 switch in a 3rd circuit. The circuit block diagram which shows the 4x4 switch of 4th Embodiment. The 1st circuit block diagram which shows the 4x4 switch of 5th Embodiment. The 2nd circuit lineblock diagram showing the 4x4 switch of a 5th embodiment. The 3rd circuit block diagram which shows the 4x4 switch of 5th Embodiment. The 4th circuit block diagram which shows the 4x4 switch of 5th Embodiment. The 5th circuit block diagram which shows the 4x4 switch of 5th Embodiment. The figure which shows a part of pattern layout in the 4x4 switch of 5th Embodiment. The circuit block diagram which shows the 4x4 switch of 6th Embodiment. The circuit block diagram which shows the 8x8 switch of 7th Embodiment. The circuit block diagram which shows the 8x8 switch of 8th Embodiment. The circuit block diagram which shows the 8 * 8 switch of the modification of 8th Embodiment. The circuit block diagram which shows the 8x8 switch of 9th Embodiment. The 1st circuit block diagram which shows the 8x8 switch of 10th Embodiment. The 2nd circuit lineblock diagram showing the 8x8 switch of a 10th embodiment. The 3rd circuit block diagram which shows the 8x8 switch of 10th Embodiment. The 4th circuit block diagram which shows the 8x8 switch of 10th Embodiment. The 5th circuit block diagram which shows the 8x8 switch of 10th Embodiment. The circuit block diagram which shows the 8x8 switch of 11th Embodiment. The circuit block diagram which shows the conventional 4x4 switch. The circuit block diagram which shows the 2 * 2 switch in the conventional 4 * 4 switch.

Explanation of symbols

1 ₁ to 1 ₈ : input terminal 2 ₁ to 2 ₈ : output terminal 3 _{11 to} 3 ₁₀₂ : FET 4 ₁₁ to 4 ₃₃₈ : resistor 5 _{1 to} 5 ₃₂ : transmission line 6 _{11 to} 6 ₅₂ : control terminal 7 _{1 to} 7 ₈ : Capacitors 8 ₁ to 8 ₄ : Coplanar lines 9 _{1 to} 9 ₁₀ : SPDT switch 10: SP4T switch 12 _{1 to} 12 ₅ : 2 × 2 switch 13 _{1 to} 13 ₅ : 4 × 4 switch

Claims (30)

Comprising four signal input terminals, first to fifth five 2 × 2 switches, four signal output terminals, and two transmission means,
Each of the five 2 × 2 switches includes first and second input terminals and first and second output terminals,
The signals input to the first and second input terminals are output to the first and second output terminals or the second and first output terminals, respectively.
The four signal input terminals are connected to first and second input terminals of the first and second 2 × 2 switches, respectively.
A first output terminal of the first 2 × 2 switch is connected to a first input terminal of the third 2 × 2 switch;
A first output terminal of the second 2 × 2 switch is connected to a second input terminal of the third 2 × 2 switch;
A second output terminal of the first 2 × 2 switch is connected to a first input terminal of the fourth 2 × 2 switch;
A second output terminal of the second 2 × 2 switch is connected to a second input terminal of the fourth 2 × 2 switch;
The first output terminals of the third and fourth 2 × 2 switches are respectively connected to one ends of the two transmission means,
The second output terminals of the third and fourth 2 × 2 switches are connected to the first and second input terminals of the fifth 2 × 2 switch, respectively.
The four signal output terminals are respectively connected to the other end of the two transmission means and the first and second output terminals of the fifth 2 × 2 switch,
The 4 × 4 switch is characterized in that the transit time of the signal passing through the transmission means is set to be the same as the transit time of the signal passing through the fifth 2 × 2 switch. The 4 × 4 switch according to claim 1,
4. A 4 × 4 switch, wherein the four signal input terminals and the four signal output terminals are interchanged. 4. The 4 × 4 switch according to claim 1 or 2,
4. A 4 × 4 switch, characterized in that the insertion loss or gain of the transmission means is set to be the same as the insertion loss or gain of the fifth 2 × 2 switch in a desired band. 4. The 4 × 4 switch according to claim 1 or 2,
In addition, the first two resistors,
The first two resistors are connected in series to the two transmission means, respectively.
The total insertion loss or gain of the resistor and the transmission means connected in series is set to be the same as the insertion loss or gain of the fifth 2 × 2 switch in a desired band. 4x4 switch to do. The 4 × 4 switch according to claim 1, wherein:
Each of the first to fifth 2 × 2 switches is configured by using at least two single-pole double-throw switches. The 4x4 switch according to claim 5,
The single-pole double-throw switch is composed of a micro mechanical switch. The 4x4 switch according to claim 5,
4. The 4 × 4 switch, wherein the single pole double throw switch is composed of at least two FETs. The 4x4 switch according to claim 7,
The 2 × 2 switch includes the first and second single-pole double-throw switches, and first to fourth transmission lines.
The single-pole double-throw switch is composed of two FETs each having one of its drain or source connected to a common terminal and the other connected to two terminals other than the common terminal,
One end of each of the first and second transmission lines is connected to two terminals other than the common terminal of the first single-pole double-throw switch,
One end of each of the third and fourth transmission lines is connected to two terminals other than the common terminal of the second single-pole double-throw switch,
The first and second input terminals or the first and second output terminals of the 2 × 2 switch are respectively connected to the common terminals of the first and second single-pole double-throw switches;
The first and second output terminals or the first and second input terminals of the 2 × 2 switch are connected to a connection point between the other ends of the first and third transmission lines, and the second and second 4 × 4 switch, characterized in that it is connected to a connection point between the other ends of the four transmission lines. The 4x4 switch according to claim 7,
The 2 × 2 switch is composed of first and second two single-pole double-throw switches, first two connection means, and second two connection means,
The single-pole double-throw switch is composed of two FETs each having one of its drain or source connected to a common terminal and the other connected to two terminals other than the common terminal,
The first and second input terminals or the first and second output terminals of the 2 × 2 switch are respectively connected to the common terminals of the first and second single-pole double-throw switches;
Two terminals other than the common terminal of the first single-pole double-throw switch and two terminals other than the common terminal of the second single-pole double-throw switch are arranged to face each other at a predetermined interval. ,
Two terminals other than the common terminal of the first single-pole double-throw switch and two terminals other than the common terminal of the second single-pole double-throw switch arranged opposite to each other are connected to the first 2 Connect each with two connecting means,
The second two connecting means have one end connected to the first and second output terminals or first and second input terminals of the 2 × 2 switch, and the other end connected to the first two connecting means, respectively. Connected,
One of the second connection means intersects with the first connection means that is not connected to the second connection means. The 4 × 4 switch according to any one of claims 1 to 9,
Each set further includes 1 to 5 sets of second resistors each composed of four resistors, and at least one control terminal.
The four resistors belonging to each set have one end connected to the control terminal and the other end connected to the first and second input terminals of the first and second 2 × 2 switches, or First and second output terminals of the first and second 2 × 2 switches, or first and second input terminals of the third and fourth 2 × 2 switches, or the third and fourth terminals. A 4 × 4 switch connected to at least one of the first and second output terminals of the 2 × 2 switch or the four signal output terminals. The 4 × 4 switch according to claim 10,
4. A 4 × 4 switch, wherein the four resistors belonging to at least one of the first to fifth groups are replaced with four inductors. The 4 × 4 switch according to claim 10,
The second four resistors are arranged between the 2 × 2 switch connections or between the transmission means in parallel to the transmission lines constituting these connections or transmission means, 4 × 4 switch. The 4x4 switch according to any one of claims 1 to 12,
It also has 4 capacitors,
4. A 4 × 4 switch, wherein the four capacitors are connected in series to the four signal input terminals. The 4 × 4 switch according to any one of claims 10 to 12,
It also has 8 capacitors,
4. A 4 × 4 switch, wherein the eight capacitors are connected in series to the four signal input terminals and the four signal output terminals, respectively. The 4 × 4 switch according to any one of claims 1 to 14,
Each of the first to fifth 2 × 2 switches,
Or the first and second 2 × 2 switches,
Or the third and fourth 2 × 2 switches,
Or the first to fourth 2 × 2 switches,
Or a circuit composed of the fifth 2 × 2 switch and the transmission means excluding the first to fourth 2 × 2 switches, or the fifth 2 × 2 switch, the transmission means, and the transmission means. A circuit comprising the first two resistors connected in series;
Alternatively, any 4 × 4 switch is integrated on a semiconductor substrate. Eight signal input terminals, first to fifth five 4 × 4 switches, eight signal output terminals, and four transmission means,
Each of the five 4 × 4 switches includes first to fourth input terminals and first to fourth output terminals, and is input to the first to fourth input terminals. Output the output signal to any one of the first to fourth output terminals,
The eight signal input terminals are respectively connected to the first to fourth input terminals of the first and second 4 × 4 switches,
The first and second output terminals of the first 4 × 4 switch are connected to the first and second input terminals of the third 4 × 4 switch, respectively.
The first and second output terminals of the second 4 × 4 switch are connected to the third and fourth input terminals of the third 4 × 4 switch, respectively.
The third and fourth output terminals of the first 4 × 4 switch are connected to the first and second input terminals of the fourth 4 × 4 switch, respectively.
The third and fourth output terminals of the second 4 × 4 switch are connected to the third and fourth input terminals of the fourth 4 × 4 switch, respectively.
The first and second output terminals of the third and fourth 4 × 4 switches are respectively connected to one ends of the four transmission means,
Third and fourth output terminals of the third and fourth 4 × 4 switches are respectively connected to first to fourth input terminals of the fifth 4 × 4 switch,
The eight signal output terminals are respectively connected to the other end of the four transmission means and the first to fourth output terminals of the fifth 4 × 4 switch,
The 8 × 8 switch is characterized in that the transit time of the signal passing through the transmission means is set to be the same as the transit time of the signal passing through the fifth switch. The 8x8 switch according to claim 16,
8. An 8 × 8 switch, wherein the eight signal input terminals and the eight signal output terminals are interchanged. 18. The 8 × 8 switch according to any one of claims 16 to 17,
8. An 8 × 8 switch characterized in that the insertion loss or gain of the transmission means is set to be the same as the insertion loss or gain of the fifth 4 × 4 switch in a desired band. The 8 × 8 switch according to any one of claims 16 to 18,
In addition, it has a third four resistors,
The third four resistors are respectively connected in series to the four transmission means,
The total insertion loss or gain of the resistors connected in series and the transmission means is set to be the same as the insertion loss or gain of the fifth 4 × 4 switch in a desired band. Features 8x8 switch. 20. The 8 × 8 switch according to any one of claims 16 to 19,
Each of the first to fifth 4 × 4 switches is configured using at least four or more single-pole four-throw switches. The 8x8 switch according to claim 20,
The single-pole four-throw switch is an 8 × 8 switch configured by a micro mechanical switch. The 8x8 switch according to claim 20,
The single-pole four-throw switch is composed of at least four or more FETs. The 8x8 switch according to claim 22,
The 4 × 4 switch is composed of four single-pole four-throw switches, first four connection means, second four connection means, and third four connections having three connection points including both ends. Means and
The single-pole four-throw switch is composed of four FETs each having one of its drain or source connected to a common terminal and the other connected to four terminals other than the common terminal,
The four single-pole four-throw switches form first and second switch pairs each consisting of two single-pole four-throw switches,
The single-pole four-throw switch of the switch pair is arranged so that the four terminal sides other than the common terminal face each other at a predetermined interval,
The four terminals facing each other of the single-pole four-throw switch of the first switch pair are connected by the first four connection means, respectively.
The four terminals facing each other of the single-pole four-throw switch of the second switch pair are respectively connected by the second four connection means,
The four input terminals or the four output terminals of the 4 × 4 switch are arranged on one side of the 4 × 4 switch,
One connection point of both ends of the third four connection means is respectively connected to the four input terminals or the four output terminals arranged on one side of the 4 × 4 switch,
The four output terminals or input terminals are respectively connected to common terminals of the four single-pole double-throw switches,
The other two connection points of each of the third connection means are one connection means different from each other among the first four connection means and one different from one among the second four connection means. 8 × 8 switch characterized in that it is connected to two connecting means. 24. The 8 × 8 switch according to claim 16, wherein
10. An 8 × 8 switch, wherein at least one of the first to fifth 4 × 4 switches is configured by the 4 × 4 switch according to any one of claims 1 to 9. 25. The 8 × 8 switch according to any one of claims 16 to 24,
Each set further includes 1 to 5 sets of fourth resistors each composed of 8 resistors, and at least one control terminal.
The eight resistors belonging to each set have one end connected to the control terminal and the other end respectively.
First to fourth input terminals of the first and second 4 × 4 switches;
Or first to fourth output terminals of the first and second 4 × 4 switches,
Or first to fourth input terminals of the third and fourth 4 × 4 switches,
Or first to fourth output terminals of the third and fourth 4 × 4 switches,
Or the eight signal output terminals,
An 8 × 8 switch connected to at least one of 26. The 8x8 switch of claim 25.
8. An 8 × 8 switch, wherein eight resistors belonging to at least one of the first to fifth groups are replaced with eight inductors. 26. The 8x8 switch of claim 25.
The fourth eight resistors are arranged between the 4 × 4 switch connections or between the transmission means in parallel to the transmission lines constituting these connections or transmission means. switch. 28. The 8 × 8 switch according to any one of claims 16 to 27,
It also has 8 capacitors,
8. An 8 × 8 switch, wherein the eight capacitors are connected in series to the eight signal input terminals. 28. The 8 × 8 switch according to any one of claims 25 to 27,
The 8 × 8 switch further comprising 16 capacitors, wherein the 16 capacitors are connected in series to the 8 signal input terminals and the 8 signal output terminals, respectively. 30. The 8 × 8 switch according to any one of claims 16 to 29,
Each of the first to fifth 4 × 4 switches,
Or the first and second 4 × 4 switches,
Or the third and fourth 4 × 4 switches,
Or the first to fourth 4 × 4 switches,
Or a circuit constituted by the fifth 4 × 4 switch and the transmission means excluding the first to fourth 4 × 4 switches, or the fifth 4 × 4 switch, the transmission means, and the transmission means. A circuit in which the third four resistors are respectively connected in series;
Alternatively, the entire 8 × 8 switch is integrated on a semiconductor substrate.

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