JP4068194B2 - MOS transistor and method for controlling potential of MOS transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MOS transistor and a MOS transistor potential control method, and more particularly to a MOS transistor having a plurality of impurity diffusion regions and a potential control method for the impurity diffusion regions.
[0002]
[Prior art]
In recent years, the power supply voltage in a semiconductor device, for example, a non-volatile memory such as a flash memory, has been reduced from 5 V single to 3 V single and further to 3 V or less. As the power supply voltage is lowered, a method using FN tunnel current (Fowler-Nordheim Tunneling Current) has become promising for data writing and data erasing to the flash memory.
[0003]
According to this FN tunnel current, current consumption during data writing or data erasing can be made extremely small, so that a high voltage necessary for data writing / erasing can be generated inside the chip.
[0004]
By the way, in a transistor constituting a memory cell, a flash having recently adopted a double well structure for the purpose of alleviating an electrical load between a source and a drain to which a high voltage is applied at the time of data writing / erasing. Memory has become mainstream.
[0005]
Here, FIG. 5 shows a schematic configuration of a conventional flash memory 101 having a double well structure. In the flash memory 101, an N well 105 in which N type impurities are diffused is formed inside a P type substrate 103, and further, a P well 107 in which P type impurities are diffused is formed inside the N well 105. Has been. A memory cell 117 is configured by the P well 107, two N + regions 109 and 111 formed inside the P well 107, a control gate 113, and a floating gate 115. The P-type substrate 103 is connected to the ground potential Vss, and the N well 105 is connected to the power supply potential Vcc.
[0006]
For example, in order to erase the data in the memory cell 117, the control gate 113 is controlled to a predetermined gate potential VG as shown in FIG. 5, and the P well 107 and the N + regions 109 and 111 are controlled to a predetermined substrate. It is necessary to control the potential to -VS. In general, when data is written / erased in a nonvolatile memory such as a flash memory, the gate potential VG and the substrate potential -VS are required to be about ± 6V to ± 20V.
[0007]
[Problems to be solved by the invention]
By the way, as the power supply voltage is lowered as described above, the boost efficiency of the voltage generation circuit for generating a high voltage necessary for writing / erasing data in the memory cell is reduced, and a predetermined voltage is generated in a short time. It has become difficult to make.
[0008]
Furthermore, in the case of the flash memory 101 having a double well structure as shown in FIG. 5, a capacitance component naturally occurs at the junction between the N well 105 and the P well 107. In particular, the capacitance of the capacitive component in recent large-capacity nonvolatile memories may reach several tens of μF. Then, most of the time required for the P well 107 and the two N + regions 109 and 111 to reach the predetermined substrate potential −VS is spent for charging this capacitive component.
[0009]
That is, in a non-volatile memory having a double well structure, such as the flash memory 101, the boost efficiency is reduced due to the lower power supply voltage, and the capacitance component generated at the junction between the N well 105 and the P well 107 is data This was an obstacle to speeding up writing / erasing.
[0010]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a capacitor having a capacitance of, for example, several tens of μF at the junction between one impurity diffusion region and another impurity diffusion region. A new and improved MOS transistor capable of controlling the potential of one impurity diffusion region to a desired value in a short time even when a component is generated and the power source is a low voltage of about 3 V, for example. An object is to provide a method for controlling the potential of a MOS transistor .
[0011]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, according to claim 1, an N well formed by diffusing an N-type impurity inside a semiconductor substrate and a P-type impurity diffused inside the N well are formed. The P well is formed in a double well structure, and includes two N + regions formed inside the P well, a control gate, and a floating gate, and writing is performed by controlling the P well to a desired potential. A MOS transistor in which an erase operation is performed is provided. Then, such MOS transistors, it is possible to control the potential of the P-well, and to control the first and the potential control circuit capable of electrically floating state P-well, the potentials of the N-well A second potential control circuit capable of performing the write / erase operation, the first potential control circuit causes the P-well at the initial potential to be in an electrically floating state, and then the second potential control circuit The control circuit controls the N well from one potential to another potential . According to such a configuration, the potential of the N well can be changed while the P well is in an electrically floating state. Since a capacitance component is generated at the junction between the P well and the N well , the potential of the P well is changed by changing the potential of the N well . For example, by changing the potential of the N-well, the potential of the P-well is brought close to the potential that is finally required, and the potential of the P-well is controlled based on that potential, thereby controlling the potential of the P-well to a desired value. The time required to do this will be shortened.
[0012]
Then, as described in claim 2, by the potential of the N well is controlled by a second potential control circuit and less power supply potential, it is possible to perform the potential control at high speed, resulting in P-well The potential control time can be shortened.
[0014]
According to a third aspect of the present invention, the first potential control circuit includes a charge pump circuit capable of changing the potential of the P well in accordance with the clock signal, and the potential of the P well is fixed to a predetermined reference potential. And a level shift circuit that controls the reference potential adjustment unit. According to this configuration, it is possible to efficiently control the potential of the P well and easily create an electrical floating state.
[0015]
According to a fourth aspect of the present invention, the second potential control circuit includes a potential selection unit capable of setting the N well to either one potential or another potential, and a level shift for controlling the potential selection unit. You may make it comprise from a circuit. According to such a configuration, the potential of the P well in the electrically floating state through the N well can be changed by a difference between one potential and another potential.
[0016]
According to the fifth aspect of the present invention, the semiconductor device includes an N well formed by diffusing N-type impurities inside the semiconductor substrate, and a P well formed by diffusing P-type impurities inside the N well. A double well structure is provided, which includes two N + regions formed inside the P well, a control gate, and a floating gate, and a write / erase operation is performed by controlling the P well to a desired potential. A potential control method for a MOS transistor for controlling a P-well in a MOS transistor to a desired potential is provided. The potential control method of such a semiconductor device includes a first step of the P-well in the initial potential and electrically floating state, a second step of controlling the N-well from one potential to another potential, P And a third step of controlling the well to a desired potential. According to such a potential control method, the potential fluctuation of the N well can be reflected to the P well in the first and second steps. Therefore, the time required for controlling the potential of the P well in the third process thereafter to a desired value is shortened.
[0017]
Furthermore, as described in claim 6 , after the third step in the potential control method of the semiconductor device according to claim 5 , the fourth step of bringing the P well into an electrically floating state, and the N well with another potential The fifth step of controlling to the first potential and the sixth step of controlling the P well to the initial potential may be performed. According to this potential control method, in the fourth and fifth steps, it is possible to reflect the potential fluctuation of the N well with respect to the P well . Therefore, the time required for controlling the potential of the P well to the initial value in the sixth step thereafter is shortened.
[0018]
Further, as described in claim 7 , by setting the one potential and the other potential to be equal to or lower than the power supply potential, the potential control of the N well can be performed at high speed, resulting in the potential control time of the P well. Can be shortened.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Exemplary embodiments of a MOS transistor and a potential control method for the MOS transistor according to the present invention will be described below in detail with reference to the accompanying drawings. In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals, and redundant description is omitted.
[0021]
FIG. 1 shows a schematic configuration of a flash memory 1 as a MOS transistor according to an embodiment of the present invention. In this flash memory 1, an N well 5 is formed as a second impurity diffusion region in which an N type impurity is diffused inside a P type substrate 3, and further a P type impurity is diffused inside the N well 5. A P well 7 is formed as a first impurity diffusion region. A memory cell 17 is constituted by the P well 7, the two N + regions 9 and 11 formed inside the P well 7, the control gate 13, and the floating gate 15. The P-type substrate 3 is connected to the ground potential Vss.
[0022]
A voltage generation circuit 21 as a first potential control circuit is connected to the P well 7 and the N + regions 9 and 11, and a well potential control circuit 61 as a second potential control circuit is connected to the N well 5. It is connected.
[0023]
Here, the configuration of the voltage generation circuit 21 as the first potential control circuit will be described. As shown in FIG. 2, the voltage generation circuit 21 includes a charge pump circuit 23, an NMOS transistor 25 as a reference potential adjustment unit, a level shift circuit 27, and a NAND gate 29. Further, the charge pump circuit 23 includes five PMOS transistors 31, 32, 33, 34, 35, four capacitors 36, 37, 38, 39, and an inverter 40. On the other hand, the level shift circuit 27 includes two PMOS transistors 41 and 42, two NMOS transistors 43 and 44, and an inverter 45. The four capacitors 36, 37, 38, 39 belonging to the charge pump circuit 23 can be formed by PMOS transistors having a common drain and source.
[0024]
The clock signal CLK is input to one input of the NAND gate 29, and the first activation signal EN1 is input to the other input. The first activation signal EN1 is also input to the inverter 45 and the gate of the PMOS transistor 42 belonging to the level shift circuit 27.
[0025]
Next, the circuit configuration of the charge pump circuit 23 will be described. The gates of the five PMOS transistors 31, 32, 33, 34, and 35 are shared with the respective sources. The source of the PMOS transistor 31 is connected to the ground potential Vss, while the drain is connected to the source of the PMOS transistor 32 and one end of the capacitor 36. Similarly, the drain of the PMOS transistor 32 is connected to the source of the PMOS transistor 33 and one end of the capacitor 37, the drain of the PMOS transistor 33 is connected to the source of the PMOS transistor 34 and one end of the capacitor 38, and the drain of the PMOS transistor 34. Are connected to the source of the PMOS transistor 35 and one end of the capacitor 39. The drain of the PMOS transistor 35 is connected to the output node N1.
[0026]
The output of the NAND gate 29 is connected to the input of the inverter 40 and is connected to the other ends of the capacitors 36 and 38, and the output of the inverter 40 is connected to the other ends of the capacitors 37 and 39.
[0027]
Next, the circuit configuration of the level shift circuit 27 will be described. The sources of the PMOS transistors 41 and 42 are connected to the power supply potential Vcc. The drain of the PMOS transistor 41 is connected to the drain of the NMOS transistor 43 and the gate of the NMOS transistor 44. The drain of the PMOS transistor 42 is connected to the drain of the NMOS transistor 44, the gate of the NMOS transistor 43, and the node Na. Further, the node Na is connected to the gate of an NMOS transistor 25 as a reference potential adjusting unit.
[0028]
The sources, substrate gates of the NMOS transistors 43 and 44, and the substrate gate of the NMOS transistor 25 serving as the reference potential adjusting unit are all made common and connected to the output node N1. Note that the source of the NMOS transistor 25 is connected to a ground potential Vss as a reference potential. The output node N1 is configured to output the output OUT1 to the P well 7.
[0029]
Next, the configuration of the well potential control circuit 61 as the second potential control circuit will be described with reference to FIG. The well potential control circuit 61 includes a potential selection unit 63 and a level shift circuit 65. Further, the potential selection unit 63 is composed of a PMOS transistor 67 and an NMOS transistor 68, and the level shift circuit 65 is composed of two PMOS transistors 69 and 70, two NMOS transistors 71 and 72, and an inverter 73.
[0030]
The second activation signal EN2 is input to the gate of the NMOS transistor 71 belonging to the level shift circuit 65 and the input of the inverter 73. Further, the output of the inverter 73 is connected to the gate of the NMOS transistor 72 so that the logic inversion signal of the second activation signal EN2 is inputted. Note that the sources of the two NMOS transistors 71 and 72 belonging to the level shift circuit 65 and the source of the NMOS transistor 68 belonging to the potential selector 63 are commonly connected to the ground potential Vss.
[0031]
The drain of the NMOS transistor 71 is connected to the drain of the PMOS transistor 69 and the gate of the PMOS transistor 70. On the other hand, the drain of the NMOS transistor 72 is connected to the drain of the PMOS transistor 70, the gate of the PMOS transistor 69, and the node Nb. The node Nb is connected to the gate of the PMOS transistor 67 and the gate of the NMOS transistor 68 belonging to the potential selection unit 63.
[0032]
All the source and substrate terminals of the two PMOS transistors 69 and 70 belonging to the level shift circuit 65 and the PMOS transistor 67 belonging to the potential selection unit 63 are connected to a predetermined well potential VNW. The drain of the PMOS transistor 67 and the drain of the NMOS transistor 68 belonging to the potential selection unit 63 are commonly connected to the output node N2. The output node N2 is configured to output the output OUT2 to the N well 5.
[0033]
The operation of the flash memory 1 as the MOS transistor according to the embodiment of the present invention having the above configuration will be described with reference to FIG.
[0034]
In the flash memory 1, for example, when erasing data in the memory cell 17, the control gate 13 is controlled to a predetermined gate potential VG, and the P well 7 and the N + regions 9 and 11 are connected by the output OUT 1 of the voltage generation circuit 21. It is necessary to control to a predetermined substrate potential -VS.
[0035]
Here, the operation of the voltage generation circuit 21 as the first potential control circuit is started. First, the first activation signal EN1 is changed from the ground potential Vss (hereinafter referred to as “L level”) to the power supply potential Vcc (hereinafter referred to as “H level”). As the first activation signal EN1 changes to H level in this way, the PMOS transistor 41 belonging to the level shift circuit 27 is turned on. Incidentally, since the node Na at the moment when the first activation signal EN1 changes from the L level to the H level is still at the initial H level, the NMOS transistor 43 is also turned on. These gates try to balance near the middle of the H and L levels. However, since the PMOS transistor 42 is turned off immediately thereafter, the NMOS transistor 44 starts to turn on weakly. As a result, the node Na gradually changes from the H level to the L level, and the NMOS transistor 43 starts to turn off, so that the node Na further approaches the L level. Finally, the PMOS transistor 41 and the NMOS transistor 44 are completely turned on, the PMOS transistor 42 and the NMOS transistor 43 are completely turned off, and the node Na becomes L level.
[0036]
By the way, when paying attention to the PMOS transistor 35 connected to the output node N1, since the NMOS transistor 25 is on in the initial state, the output node N1 is at the power supply potential Vss. Therefore, the potential of the gate and source of the PMOS transistor 35 is at least − | Vtp | (Vtp is the threshold voltage of the PMOS transistor 35), and the PMOS transistor 35 is kept off. After that, as described above, when the node Na becomes L level and the NMOS transistor 25 is turned off, the output node N1, that is, the P well 7 is in an electrically floating state that is not fixed to any potential.
[0037]
As described above, when the P well 7 is brought into an electrically floating state, the operation of the well potential control circuit 61 as the second potential control circuit is started. First, the second activation signal EN2 is changed from L level to H level. The node Nb of the well potential control circuit 61 is changed from the ground potential Vss to the predetermined well potential VNW by the level shift circuit 65 in accordance with the change of the second activation signal EN2, and the output node N2, that is, the N well 5 is The initial value of the well potential VNW returns to the ground potential Vss.
[0038]
At this time, as described above, since the P well 7 is in an electrically floating state, the potential change of the N well 5 remains unchanged by the junction capacitance formed between the N well 5 and the P well 7. 7 changes in potential. That is, when the N well 5 changes from the well potential VNW to the ground potential Vss, the P well 7 is lowered from the ground potential Vss in the initial state by the well potential VNW and becomes the intermediate potential −VNW. Note that the value of the well potential VNW is limited to the power supply potential Vcc or less, so that the N well 5 can be held at the well potential VNW even in a so-called standby state where the write / erase operation of the flash memory 1 is not performed. Thus, time for raising the well potential VNW is not required when starting the write / erase operation.
[0039]
Next, when the clock signal CLK is oscillated, the charge pump circuit 23 belonging to the voltage generation circuit 21 starts a so-called pump operation in which the potential of the output node N1 is gradually lowered in the cycle of the clock signal CLK. Therefore, the P-well 7 that has been in an electrically floating state until then is released, and finally is set to a desired substrate potential −VS. At this time, the data in the memory cell 17 is erased.
[0040]
After completion of the data erasing operation of the memory cell 17 as described above, the pumping operation of the charge pump circuit 23 is completed by stopping the oscillation of the clock signal CKL. At this point, the P-well 7 is again brought into an electrically floating state. Next, by changing the second activation signal EN2 from the H level to the L level, the node Nb to which the output of the level shift circuit 65 in the well potential control circuit 61 is connected is changed from the well potential VNW to the ground potential Vss. Will return. As a result, the N well 5 returns from the ground potential Vss to the well potential VNW which is the initial value. The potential variation of the N well 5 promotes the potential variation of the P well 7 due to the capacitance component between the N well 5 and the P well 7, and the P well 7 is increased from the substrate potential -VS by the well potential VNW. The intermediate potential is −VS + VNW.
[0041]
Thereafter, by returning the first activation EN1 from the H level to the L level, the node Na in the voltage generation circuit 21 returns to the power supply potential Vcc. As a result, the NMOS transistor 25 is turned on, and the output node N1, that is, the P well 7, is reset to the ground potential Vss which is the initial value.
[0042]
As described above, according to the flash memory 1 according to the embodiment of the present invention, when the potential of the P well 7 is controlled to the desired substrate potential −VS, the P well 7 is brought into an electrically floating state. Since the potential of the P well 7 is lowered in advance by the well potential VNW by lowering the potential of the N well 5 by the well potential VNW, a desired substrate is obtained from the ground potential Vss which is the initial value. Compared to the conventional case where the potential is gradually lowered to the potential −VS by the pump operation, the time can be dramatically shortened. Similarly, the time required for returning the P well 7 from the desired substrate potential −VS to the ground potential Vss which is the initial value is also minimized. Therefore, the data writing / erasing operation of the memory cell 17 can be speeded up.
[0043]
By the way, as for the specific value of the well potential VNW, for example, when the power supply potential Vcc is 5V and the desired substrate potential −VS is −2V, the well potential VNW is 5V. Due to the potential fluctuation, the P-well 7 is lowered to −5V which is lower than the desired substrate potential −VS (= −2V). Therefore, in this case, it is preferable to set the well potential VNW to 2 V or less. In addition, when the desired substrate potential is, for example, −7V, the well potential VNW is set to the power supply potential Vcc of 5V, which is the most efficient and in a short time. It becomes possible to control to (= -7).
[0044]
As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, this invention is not limited to this example. It will be obvious to those skilled in the art that various changes or modifications can be conceived within the scope of the technical idea described in the claims, and these are naturally within the technical scope of the present invention. It is understood that it belongs.
[0045]
For example, the voltage generation circuit 21 as the first potential control circuit and the well potential control circuit 61 as the second potential control circuit are not limited to the circuit configurations shown in FIGS. Further, the memory cell 17 is not limited to the configuration shown in FIG.
[0046]
In the embodiment of the present invention, the flash memory 1 is used as the semiconductor device. However, the present invention is not limited to this, and can be applied to, for example, an EEPROM or a DRAM.
[0047]
【The invention's effect】
As described above, according to the MOS transistor and the MOS transistor potential control method of the present invention, when the potential of the P well is controlled to a desired value, the potential of the N well in contact with the P well is controlled. Accordingly, in order to be able to assist the potential control of the P-well, the time required for controlling the P-well to a desired potential is shortened. Therefore, if the present invention is applied to, for example, a non-volatile memory or the like, it is possible to speed up the data write operation to the memory cell and the data erase operation of the memory cell.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration of a flash memory according to an embodiment of the present invention.
2 is a circuit diagram showing a configuration of a voltage generation circuit used in the flash memory of FIG. 1. FIG.
3 is a circuit diagram showing a configuration of a well potential control circuit used in the flash memory of FIG. 1. FIG.
4 is a timing chart showing the operation of the flash memory of FIG. 1. FIG.
FIG. 5 is a cross-sectional view showing a configuration of a conventional flash memory.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Flash memory 3 P type substrate 5 N well 7 P well 17 Memory cell 21 Voltage generation circuit 23 Charge pump circuit 25 NMOS transistor 27 Level shift circuit 61 Well potential generation circuit 63 Potential selection part 65 Level shift circuit VNW Well potential -VS sub Straight potential Vcc Power supply potential Vss Ground potential

Claims (7)

An N-well formed by diffusing N-type impurities inside the semiconductor substrate;
A P-well formed by diffusing P-type impurities inside the N-well;
Formed into a double well structure consisting of
Two N + regions formed inside the P-well, a control gate, and a floating gate;
In a MOS transistor in which a write / erase operation is performed by controlling the P well to a desired potential,
A first potential control circuit capable of controlling the potential of the P-well and allowing the P-well to be in an electrically floating state;
A second potential control circuit capable of controlling the potential of the N well;
With
When performing the write / erase operation, the second potential control circuit sets the N well to one potential after the P potential at the initial potential is brought into an electrically floating state by the first potential control circuit. A MOS transistor characterized by being controlled to a different potential from   2. The MOS transistor according to claim 1, wherein the potential of the N well controlled by the second potential control circuit is equal to or lower than a power supply potential. The first potential control circuit includes:
A charge pump circuit capable of changing the potential of the P-well according to a clock signal;
A reference potential adjusting unit capable of fixing the potential of the P well to a predetermined reference potential;
A level shift circuit for controlling the reference potential adjustment unit;
The MOS transistor according to claim 1, comprising: The second potential control circuit is:
A potential selection section capable of setting the N well to one potential or another potential;
A level shift circuit for controlling the potential selection unit;
The MOS transistor according to claim 1, comprising: An N-well formed by diffusing N-type impurities inside the semiconductor substrate;
A P-well formed by diffusing P-type impurities inside the N-well;
Formed into a double well structure consisting of
Two N + regions formed inside the P-well, a control gate, and a floating gate;
A potential control method for a MOS transistor in which a write / erase operation is performed by controlling the P-well to a desired potential,
A first step of bringing the P-well at an initial potential into an electrically floating state;
A second step of controlling the N well from one potential to another;
A third step of controlling the P-well to the desired potential;
A potential control method for a MOS transistor, comprising: A fourth step of bringing the P-well into an electrically floating state after the third step;
A fifth step of controlling the N well from the other potential to the one potential;
A sixth step of controlling the P-well to the initial potential;
6. The method for controlling a potential of a MOS transistor according to claim 5, comprising:   7. The method for controlling a potential of a MOS transistor according to claim 5, wherein the one potential and the other potential are equal to or lower than a power supply potential.

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