JP4061751B2 - MOS semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a gate electrode such as a polycrystalline silicon film in a MOS semiconductor device having a gate having a metal-oxide-semiconductor (MOS) structure and a method for manufacturing the same.
[0002]
[Prior art]
FIG. 4 is a partial cross-sectional view of a MOS field effect transistor (hereinafter referred to as MOSFET) which is the most basic example of a MOS semiconductor device. A p-well region 2 is formed on the surface layer of the high resistivity n drift layer 1 b, and an n ⁺ source region 3 is formed in the p-well region 2. A gate electrode 6a of a polycrystalline silicon film is provided on the surface of p well region 2 sandwiched between the exposed surface portion of n drift layer 1b and n ⁺ source region 3 with gate oxide film 5 interposed. The surface exposed portion of n drift layer 1 b is covered with thick field oxide film 4, and gate electrode 6 extends on field oxide film 4. Reference ^numeral 7 denotes a source electrode that contacts both the n ⁺ source region 3 and the p well region 2. The source electrode 7 and the gate electrode 6 a, are insulated by an interlayer insulating film 9 made of boric Motrin silica glass (BPSG). A gate metal electrode 6b is provided in contact with the gate electrode 6a through a window provided in the interlayer insulating film 9. On the back side of the n drift layer 1b, a drain electrode 8 is provided via a high impurity concentration n ⁺ drain layer 1a. A peripheral metal electrode 10 having the same potential as the drain electrode 8 is provided at the peripheral portion of the chip. The interlayer insulating film 9 also insulates between the peripheral electrode 6 c of the polycrystalline silicon film in contact with the peripheral metal electrode 10 and the gate metal electrode 6 b.
[0003]
[Problems to be solved by the invention]
With the miniaturization of semiconductor elements, the thickness of the interlayer insulating film 9 is also reduced, and insulation is performed between the source electrode 7 and the gate electrode 6a and between the gate metal electrode 6b and the peripheral electrode 6c in a reliability test such as a gate high temperature application test. Some were subject to deterioration or destruction.
When the cross section of the defective product was observed, the edges of the upper surfaces of the gate electrode 6a and the peripheral electrode 6c were sharp at the edge portions (B and C portions) of the gate electrode 6a and the peripheral electrode 6c, and the thickness of the interlayer insulating film 9 was about 1 / 3 or thinner was observed.
[0004]
In particular, when the pattern of the gate electrode 6a and the peripheral electrode 6c has a corner portion of 90 degrees or less as shown in the perspective view of FIG. It was found that the insulating film 9 becomes thin. It is conceivable that the deterioration or breakdown of the insulation is caused by the concentration of the electric field or the injection of electric charge in the thinned portion of the interlayer insulating film 9.
In view of the above problems, an object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the same, which can prevent an interlayer insulating film on a gate electrode from being thinned.
[0005]
[Means for Solving the Problems]
The present invention for the above SL solving the problem includes a gate electrode made of which, for example, polycrystalline silicon film formed over the gate insulating film on a semiconductor substrate, an interlayer insulating film covering at least a portion of the gate electrode, the In a MOS semiconductor device having a metal electrode provided on an interlayer insulating film, the end of the upper surface of the gate electrode is inclined at an obtuse angle.
[0006]
By doing so, it improves the coverage covering the end portion of the gate electrode of the interlayer insulating film, a thin layer of the interlayer insulating film can be prevented.
In particular, if the planar corners of the gate electrode are deleted or arcuate, a three-dimensional apex at the end of the upper surface of the gate electrode does not occur.
As a manufacturing method of a MOS semiconductor device in which the end of the upper surface of the gate electrode is inclined at an obtuse angle, it is preferable to perform etching after depositing a polycrystalline silicon film and irradiating the surface layer with ions.
[0007]
By doing so, a damage layer is formed on the surface layer by ion irradiation and the etching rate is increased, so that the edge of the upper surface of the gate electrode can be inclined at an obtuse angle.
The ion dose is 1 × 10 ¹⁴ to 3 × 10 ¹⁵ cm ⁻² .
As the dose increases, the edge angle of the upper surface of the gate electrode becomes gentler, but the range of 1 × 10 ¹⁴ to 3 × 10 ¹⁵ cm ⁻² is most suitable as shown in the experimental results described later.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
[Example 1]
FIG. 1 is a partial sectional view of a vertical MOSFET according to a first embodiment of the present invention.
The basic structure is the same as in FIG. A p well region 12 is formed in the surface layer of the high resistivity n drift layer 11 b, and an n ⁺ source region 13 is formed in the p well region 12. A gate electrode 16a of a polycrystalline silicon film is provided on the surface of the p well region 12 sandwiched between the exposed surface portion of the n drift layer 11b and the n ⁺ source region 13 with a gate oxide film 15 interposed therebetween. The surface exposed portion of n drift layer 11b is covered with thick field oxide film 14, and gate electrode 16a extends on field oxide film 14. Reference numeral 17 denotes a source electrode that contacts both the n ⁺ source region 13 and the p well region 12. The source electrode 17 and the gate electrode 16a are insulated by an interlayer insulating film 19 made of boron phosphorous silica glass (BPSG). A gate metal electrode 16b is provided in contact with the gate electrode 16a through a window provided in the interlayer insulating film 19 . A drain electrode 18 is provided on the back surface side of the n drift layer 11b via a high impurity concentration n ⁺ drain layer 11a. A peripheral metal electrode 20 having the same potential as the drain electrode 18 is provided at the peripheral portion of the chip. The interlayer insulating film 19 also insulates between the peripheral electrode 16 c of the polycrystalline silicon film in contact with the peripheral metal electrode 20 and the gate metal electrode 16 b.
[0009]
For example, the thickness of the gate oxide film 15 is 100 nm, the field oxide film 14 is 450 nm, the thickness of the gate electrode 16a is 0.8 μm, the interlayer insulating film 19 is 0.5 μm, and the thickness of the source electrode 13 is 5 μm.
The difference from FIG. 4 is that the end portions B and C (FIG. 4) on the upper surface of the gate electrode 16a and the peripheral electrode 16c are inclined so that the obtuse angle is obtained, and the interlayer insulating film 19 thereon becomes thin. That is not.
[0010]
Inclination processing of the ends of the gate electrode 16a and the polycrystalline silicon layer 16c was performed in the following steps.
After depositing and annealing a polycrystalline silicon film by low pressure CVD, arsenic ions are implanted on the entire surface under conditions of an acceleration voltage of 50 keV and a dose of 1 × 10 ¹⁵ cm ⁻² . Next, the oxide film on the surface is removed, a photoresist is applied, and a mask is formed by photolithography. Subsequently, the polycrystalline silicon film is etched by dry etching using carbon tetrafluoride gas and patterned to form the gate electrode 16a and the polycrystalline silicon layer 16c.
[0011]
By such a method, the upper end portions of the gate electrode 16a and the polycrystalline silicon layer 16c become obtuse and are not sharpened as in the prior art. Since it is difficult to directly measure the angle of the upper surface end, the lower angle (hereinafter referred to as the taper angle) A was measured and found to be about 30 degrees.
In this way, by making the upper ends of the gate electrode 16a and the polycrystalline silicon layer 16c obtuse, the insulating film 19 deposited thereon is not thinned after reflow, and defects in the reliability test are drastically reduced.
[0012]
FIG. 2 is a characteristic diagram showing the dose dependency of the taper angle A at the end when arsenic ions are implanted with an acceleration voltage of 50 keV and a different dose. In the case of using arsenic, the etching shape can be tapered at an appropriate angle with a dose of 1 × 10 ^{14 to} 3 × 10 ¹⁵ cm ⁻² .
When the dose is less than 1 × 10 ¹⁴ cm ⁻² , the taper angle A at the end is not sufficiently small. In particular, the taper angle A is not uniform, and the inclination becomes tighter as it approaches the upper surface. Even if it is 60 degrees as a whole, the upper end is close to 90 degrees and is quite sharp. On the other hand, when the dose amount is larger than 3 × 10 ¹⁵ cm ⁻² , the taper angle A is sufficiently small, but the time required for the process becomes long and is useless. Accordingly, a range of 1 × 10 ^{14 to} 3 × 10 ¹⁵ cm ⁻² is appropriate.
[0013]
[Embodiment 2] The above method also has an effect of reducing the sharpness of planar corners. FIG. 3B is a perspective view of a planar corner portion to which the above method is applied. FIG. 3A shows that the sharpness of the corners is relaxed.
[0014]
However, when the interlayer insulating film 9 is thin, there are rare cases where it deteriorates in the reliability test. As a countermeasure, we tried a pattern with a processed corner.
FIG. 3 (c) that cut the isosceles triangle corners, the (d) of FIG is that where the corners and arc-like pattern, a perspective view after etching by the method of Example 1 is there. In both cases, the sharpness of the upper end of the polycrystalline silicon layer disappeared, and no defect was found in the reliability test.
[0015]
In each of the examples, the example of the vertical semiconductor device in which the main electrode is provided on both surfaces of the semiconductor substrate is given. However, the present invention is not limited to the vertical semiconductor device, and the main electrode is provided on one main surface of the semiconductor substrate. The present invention can also be applied to a horizontal semiconductor device provided with Further, it is also effective in a so-called trench gate type semiconductor device in which a trench is provided on the surface of a semiconductor substrate and a gate electrode is embedded in the trench.
[0016]
【The invention's effect】
As described above, according to the present invention, the coverage of the interlayer insulating film can be improved by inclining the end of the upper surface of the gate electrode at an obtuse angle.
Furthermore , in the planar corners of the gate electrode, the corners are eliminated or the shape is given a curvature, thereby smoothing the three-dimensional pointed shape and improving the coverage of the interlayer insulating film. I was able to.
[0017]
As a result, electric field concentration and charge injection are alleviated, and a semiconductor device with greatly improved resistance to a gate high temperature application test can be obtained.
[Brief description of the drawings]
FIG. 1 is a partial cross-sectional view of a MOSFET according to an embodiment of the present invention. FIG. 2 is a characteristic diagram showing dependency of a taper angle A on arsenic dose. FIG. ) Is a perspective view of a corner portion according to the method of Example 1, FIG. 4C is a perspective view of the corner portion removed, and FIG. 4D is a perspective view of a corner portion having an arc shape. Partial cross section [Explanation of symbols]
1a, 11a n ⁺ drain layer
1b, 11b n drift layer
2, 12 p-well region
3, 13 n ⁺ source region
4, 14 Field oxide film
5, 15 Gate oxide film
6a, 16a Gate electrode
6b, 16b Gate metal electrode
6c, 16c Perimeter electrode
7, 17 Source electrode
8, 18 Drain electrode
9, 19 Interlayer insulation film (BPSG film)
10, 20 Perimeter metal electrode

Claims (3)

In a MOS semiconductor device having a gate electrode provided on a semiconductor substrate via a gate insulating film, an interlayer insulating film covering at least a part of the gate electrode, and a metal electrode provided on the interlayer insulating film, A MOS semiconductor device, characterized in that the gate electrode is made of a polycrystalline silicon film, and a planar corner portion of the gate electrode is deleted or an end of the upper surface of the gate electrode is inclined to an obtuse angle as an arc shape . A gate electrode made of a polycrystalline silicon film provided on a semiconductor substrate via a gate insulating film, an interlayer insulating film covering at least a part of the gate electrode, and a metal electrode provided on the interlayer insulating film In a method for manufacturing a MOS semiconductor device, a polycrystalline silicon film is deposited, and the surface layer is irradiated with ions, and then the planar corners of the polycrystalline silicon film are removed by etching or are formed into an arc shape. A method of manufacturing a MOS semiconductor device characterized by 3. The method of manufacturing a MOS semiconductor device according to claim 2 , wherein a dose amount of ions irradiated to the polycrystalline silicon film is set to 1 * 10 < ¹⁴ > to 3 * 10 ^{< 15} > cm ^<-2> .

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