JP4060973B2 - LCD controller IC - Google Patents
LCD controller IC Download PDFInfo
- Publication number
- JP4060973B2 JP4060973B2 JP03482399A JP3482399A JP4060973B2 JP 4060973 B2 JP4060973 B2 JP 4060973B2 JP 03482399 A JP03482399 A JP 03482399A JP 3482399 A JP3482399 A JP 3482399A JP 4060973 B2 JP4060973 B2 JP 4060973B2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- pad
- chip
- terminals
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000012360 testing method Methods 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 4
- 239000011295 pitch Substances 0.000 description 17
- 239000000523 sample Substances 0.000 description 6
- 238000005259 measurement Methods 0.000 description 5
- 230000002950 deficient Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 101100008046 Caenorhabditis elegans cut-2 gene Proteins 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
Images
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【0001】
【発明の属する技術分野】
本発明はパッド端子の間隔が狭いピッチであるLCDコントローラICに関するものである。
【0002】
【従来の技術】
図1に従来技術のパッド端子を示す。パッド端子9の間隔がピッチで100um程度と広かったので、ICチップのテスト時には全てのパッド端子を試験することができた。
【0003】
【発明が解決しようとする課題】
液晶画面の大画面化と、実装技術の向上に伴い、パッド端子の総数が著しく増加してきた。それによりICチップ上に配置されたパッド端子によりICチップの大きさが決まるようになって、ICチップのコストを決める要因はパッド端子の間隔となった。間隔を狭くしてパッド端子の間隔が狭いピッチであるICチップの全てのパッド端子をテスターで測定するためには、狭いピッチのプローブカードが必要であるが、針の間隔は80um程度のピッチが限界であり今後行われるであろう50um以下のピッチには対応出来ない。また狭いピッチのパッド端子を間引いてプローブを当てようとすると、隣り合うパッド端子に接触してしまい、端子間のショートを招く可能性があった。また狭ピッチになるに従いパッド端子の開口部の面積も小さくなるためプローブの合わせ精度に対するマージンも小さくなっていた。
【0004】
【課題を解決するための手段】
ICチップ間を分離し実使用時には切断する部分にあたるスクライブ領域に、プローブカードで十分に対応できるパッド端子ピッチで大きな面積となるテスト用パッド端子を設け、これを狭ピッチのパッド端子の複数個に一個の割合で繋いで間引きした。
【0005】
これにより、ウエハー状態においては全パッド端子を測定することは出来ないが、ウエハー状態においてICチップのスクリーニングを高い確率でできる。
【0006】
【発明の実施の形態】
(実施例1)
図2に本発明の平面図を示す。ICチップ5の四辺には50umの狭ピッチパッド端子3が設けられている。スクライブ領域2には100umピッチで面積の大きなテスト用端子4が設けられ、狭ピッチのパッド端子3の二個に一個の割合で金属配線6により接続されている。またこの金属配線6は隣接するICチップの狭ピッチパッド端子とも繋がれおり、端子を共有している。この時テスト用パッド端子はテスト工程においてプローブの針が正確に当たる事の出来るだけの面積を有していなければならない。このようにすれば、テスターによる測定時にパッド端子のピッチが広くかつ面積の大きなテスト用パッド端子4に合わせてプローブカードを作製すればよい。 テスト用端子4の測定後はICチップが切断される中心線に沿ってテスト用端子4が切断される。この切断によりテスト用端子4を共有していた隣接するICチップの間は電気的に分離される。本発明による測定では間引き測定となるために、実使用時の実装において全端子が正常に動作するかの確認することが好ましい。また本実施例に於は狭ピッチパッドの二個に一個の割合でテスト用パッドを接続したが、間引く割合によってICチップの合否確率を算定し見積もることもできる。
【0007】
(実施例2)
図3に本発明の他の実施例を示す。LCDコントローラICは液晶パネルを駆動するためのセグメントとコモンの出力端子10と、制御端子7から成っている。制御端子が端子毎に異なった形状を有するのに対し、端子の大多数(80%くらい)を占めるセグメントとコモンの出力端子はメモリセルのような繰り返しパターンとなっており、セグメントとコモンの出力端子を狭ピッチ化することが非常に効果がある。それに対して制御端子は多くとも20端子くらいしかないために、図3のようにICチップの四辺のうち一辺のみのセグメントとコモンの出力端子にテスト用端子を設けても良い。この場合隣接するICチップとは電気的に分離されている。
【0008】
【発明の効果】
ウエハ測定によるICの選別を行なわずに、実装後のテストによりIC選別する方法も考えられるが、本来不良となるべきICの実装のコストは非常に大きくなってしまう。しかし、本発明によればチップ面積の増加を招くことなく、LCDコントローラICのテスターでの間引きテストを行なうことができる。よってテスターにおいて間引きに比例した確率でICが選別できるため、本来不良ICとなる実装費を著しく減らすことが出来る。
【図面の簡単な説明】
【図1】従来ICの平面図である。
【図2】本発明の平面図である。
【図3】本発明の平面図である。
【符号の説明】
1 ICチップが切断される中心線
2 スクライブ領域
3 狭ピッチパッド端子
4 テスト用パッド端子
5 ICチップ
6 金属配線
7 制御端子
8 セグメントとコモンの出力端子
9 パッド端子
10 セグメントとコモンの出力端子[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an LCD controller IC in which the pitch between pad terminals is a narrow pitch.
[0002]
[Prior art]
FIG. 1 shows a conventional pad terminal. Since the pitch between the
[0003]
[Problems to be solved by the invention]
The total number of pad terminals has increased remarkably with the increase in the size of liquid crystal screens and the improvement in mounting technology. As a result, the size of the IC chip is determined by the pad terminals arranged on the IC chip, and the factor that determines the cost of the IC chip is the interval between the pad terminals. Narrow pitch probe cards are required to measure all the pad terminals of an IC chip with a narrow pitch and a small pitch between pad terminals with a tester, but the needle spacing should be about 80 um. This is a limit and cannot be used for pitches of 50um or less, which will be performed in the future. Further, if the probe is applied by thinning out the pad terminals having a narrow pitch, the adjacent pad terminals may be contacted, which may cause a short circuit between the terminals. Further, since the area of the opening of the pad terminal becomes smaller as the pitch becomes narrower, the margin for the alignment accuracy of the probe is also reduced.
[0004]
[Means for Solving the Problems]
A test pad terminal having a large area with a pad terminal pitch that can be sufficiently accommodated by a probe card is provided in a scribe region that is a portion that is separated between IC chips and is actually used. I connected them at a rate of 1 and thinned them out.
[0005]
As a result, although all pad terminals cannot be measured in the wafer state, screening of IC chips can be performed with high probability in the wafer state.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
Example 1
FIG. 2 shows a plan view of the present invention. Narrow pitch pad terminals 3 of 50 μm are provided on the four sides of the
[0007]
(Example 2)
FIG. 3 shows another embodiment of the present invention. The LCD controller IC comprises a segment for driving the liquid crystal panel, a
[0008]
【The invention's effect】
Although a method of selecting an IC by a test after mounting without performing IC selection by wafer measurement is also conceivable, the cost of mounting an IC that should originally be defective becomes very high. However, according to the present invention, the thinning test can be performed by the tester of the LCD controller IC without increasing the chip area. Therefore, since the IC can be selected with a probability proportional to the thinning in the tester, it is possible to remarkably reduce the mounting cost which is originally a defective IC.
[Brief description of the drawings]
FIG. 1 is a plan view of a conventional IC.
FIG. 2 is a plan view of the present invention.
FIG. 3 is a plan view of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Center line where IC chip is cut 2 Scribe area 3 Narrow
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP03482399A JP4060973B2 (en) | 1999-02-12 | 1999-02-12 | LCD controller IC |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP03482399A JP4060973B2 (en) | 1999-02-12 | 1999-02-12 | LCD controller IC |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2000236005A JP2000236005A (en) | 2000-08-29 |
JP4060973B2 true JP4060973B2 (en) | 2008-03-12 |
Family
ID=12424930
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP03482399A Expired - Fee Related JP4060973B2 (en) | 1999-02-12 | 1999-02-12 | LCD controller IC |
Country Status (1)
Country | Link |
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JP (1) | JP4060973B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3901004B2 (en) * | 2001-06-13 | 2007-04-04 | セイコーエプソン株式会社 | ELECTRO-OPTICAL DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE |
TW558772B (en) * | 2001-08-08 | 2003-10-21 | Matsushita Electric Ind Co Ltd | Semiconductor wafer, semiconductor device and fabrication method thereof |
-
1999
- 1999-02-12 JP JP03482399A patent/JP4060973B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JP2000236005A (en) | 2000-08-29 |
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