JP4060450B2 - Dry etching method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a dry etching method for forming the gate electrode or the like in a semiconductor integrated circuit.
[0002]
[Prior art]
In a semiconductor integrated circuit, it is common to use polysilicon as a gate electrode. In addition, due to the demand for reduction in the gate electrode wiring resistance and the reduction in film thickness due to the high integration and high performance of semiconductor integrated circuits in recent years, a structure in which tungsten (W) is superimposed on polysilicon has been developed. . Such a gate electrode is generally formed by the following process.
[0003]
First, a polysilicon layer, a barrier metal layer made of WN or TiN, and a W layer are sequentially formed by a PVD method or the like on a silicon oxide film (SiO ₂ film) as a gate oxide film, and then a desired mask is formed thereon. Form a pattern. In the case of using the CVD method, a W nucleation layer is formed between the barrier metal layer and the W layer in order to improve the adhesion between both layers.
[0004]
Next, dry etching is performed on the barrier metal layer and the W layer, or the layer including the barrier metal layer, the W nucleation layer, and the W layer, that is, the metal layer, using a reactive gas mainly containing SF _6. . If this etching progresses and a part of the surface of the polysilicon layer is exposed, the etching of the metal layer is temporarily terminated with that point as an end point.
[0005]
At the end point, the lower part of the barrier metal layer is not completely removed. For this reason, conventionally, overetching is performed for a predetermined time using the same reactive gas even after the end point, and the skirt on the side of the wiring of the metal layer is taken. When the overetching of the metal layer is completed, the polysilicon layer is dry etched by switching to a reactive gas containing Cl ₂ as a main component. In this way, a gate electrode having a desired pattern is formed.
[0006]
[Problems to be solved by the invention]
However, the conventional dry etching method described above has the following problems.
[0007]
First, the reactive gas containing SF ₆ has a small selectivity ratio of W to polysilicon (ratio of W etching rate to polysilicon etching rate) of about 0.2 to 0.3. However, there is a problem that the surface of the already exposed polysilicon layer becomes rough. As is apparent from FIG. 4 which is an SEM micrograph showing the layer state immediately after over-etching of the metal layer, this appears remarkably in an open space where the space between the masks is wide. When the etching of the polysilicon layer is started with the surface of the polysilicon layer being rough as described above, the etching of the recesses proceeds first, and there is a possibility that the silicon oxide film is pitched (through).
[0008]
On the other hand, when the over-etching time for the metal layer is shortened in order to avoid such problems, the skirted part remains on the side of the metal layer wiring, so that the vertical shape of the gate electrode is impaired and the desired characteristics are obtained. May not be obtained. In addition, if the skirting portion on the side of the wiring remains, a severe residue starting from the W layer or the barrier metal layer tends to occur during the subsequent etching of the polysilicon layer.
[0009]
An object of the present invention is to provide a novel dry etching method capable of solving the above problems.
[0010]
[Means for Solving the Problems]
Therefore, the present invention according to claim 1 includes a first step of disposing a substrate to be processed having a polysilicon layer and a metal layer formed thereon on a susceptor in the reaction vessel, and the inside of the reaction vessel. A second step of reducing the pressure to a predetermined pressure; a third step of applying a negative bias power to the susceptor; and supplying a first reactive gas containing NF ₃ gas into the reaction vessel; Forming a plasma therein and etching the metal layer; and after the completion of the fourth step, the gas in the reaction vessel is exhausted and the second reactive gas is supplied into the reaction vessel. And a fifth etching step of etching the polysilicon layer by forming plasma in the reaction vessel, wherein NF ₃ gas is added to the second reactive gas. age There.
[0011]
As described above, when NF ₃ gas is used as the reactive gas used for etching the metal layer, the selective ratio of W to polysilicon of the NF ₃ containing gas is about 0.5 or more. At this time, the roughness of the surface of the polysilicon layer can be reduced.
[0012]
The first reactive gas may be NF ₃ gas alone or a mixed gas composed of NF ₃ gas and Cl ₂ gas, but the ratio is 20% to 100% for NF ₃ gas, Cl _2. The gas is preferably 80% to 0%.
[0013]
It is also effective to add NF ₃ gas to the second reactive gas. If NF ₃ gas is added when the metal layer is not over-etched and a skirt portion remains in the metal layer on the side of the wiring, the skirt portion on the side of the wiring can be effectively removed. .
[0014]
According to a third aspect of the present invention, a substrate to be processed having a polysilicon layer and a metal layer including a barrier metal layer and a tungsten layer formed thereon is disposed on a susceptor in a reaction vessel. A second step of reducing the pressure in the reaction vessel to a predetermined pressure, a third step of applying a negative bias power to the susceptor, and supplying a first reactive gas into the reaction vessel, A fourth step of forming plasma in the reaction vessel and etching the metal layer, and a second step of exhausting the gas in the reaction vessel and containing NF ₃ gas in the reaction vessel after completion of the fourth step And a fifth step of etching the polysilicon layer by supplying a reactive gas and forming plasma in the reaction vessel. Also in this method, as described above, since the NF ₃ gas is added to the second reactive gas , the metal layer is not over-etched, and the bottom portion remains in the metal layer beside the wiring. In addition, it is possible to effectively remove the skirting portion beside the wiring.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0016]
FIG. 1 is a cross-sectional view schematically showing a configuration of a silicon wafer (substrate to be processed) for explaining a dry etching method according to the present invention, wherein (a) to (d) are layers from etching start to etching completion. It is the figure which showed these states in order. The silicon wafer 1 is used for cutting out a gate electrode. A SiO ₂ film 2 as a gate oxide film is formed on the surface of the silicon wafer 1, and a poly electrode as a gate electrode layer is formed on the SiO ₂ film 2. A silicon layer 3 and a metal layer 4 are formed. The metal layer 4 is formed by a PVD process, and includes a barrier metal layer 4a made of TiN or WN and a W layer 4b thereon. On the W layer 4b, a mask 5 made of an organic material or SiN is formed in a desired pattern.
[0017]
FIG. 2 is a schematic view showing an embodiment of a plasma type dry etching apparatus 10 according to the present invention. In FIG. 2, the dry etching apparatus 10 includes a reaction vessel 12 whose inside is decompressed. The reaction vessel 12 includes a cylindrical vessel body 14 made of a material obtained by subjecting aluminum to an alumite treatment, and a lid 16 that is a discharge component attached to the upper portion of the vessel.
[0018]
A susceptor 18 on which the silicon wafer 1 is placed is disposed inside the reaction vessel 12. An electrostatic chuck 20 for fixing the silicon wafer 1 is provided on the upper surface of the susceptor 18. The susceptor 18 also functions as an electrode, and is grounded via the matching unit 22 and the high frequency bias power source 24. Therefore, when a high frequency bias voltage is applied to the grounded container body 14, the susceptor 18 functions as a cathode and the container body 14 functions as an anode.
[0019]
Further, the container body 14 is provided with an exhaust port 26 connected to a vacuum pump (not shown) for exhausting the inside of the reaction container 12, and further for introducing a reactive gas into the interior. A gas supply port 28 is provided.
[0020]
A gas mixing chamber 30 is connected to the gas supply port 28 via a pipe. The gas mixing chamber 30 is a device that uniformly mixes various gases. Various gas supply sources 32 to 38 are connected to the gas mixing chamber 30 through flow control valves 44 to 50, respectively. There are various gases that can be used for etching the metal layer 4 and the polysilicon layer 3. In this embodiment, NF ₃ , Cl ₂ , HBr, and O ₂ are used, and gas supply sources 32 to 38 are provided. Yes.
[0021]
The flow rate adjusting valves 44 to 50 are controlled to be opened and closed by a control device 56 formed of a microcomputer or the like to adjust the flow rate of each gas. Accordingly, it is possible to set the mixing ratio of the reactive gas to a predetermined value.
[0022]
The lid 16 which is a part of the reaction vessel 12 is made of a dielectric material. A coil antenna 58 is disposed on the outer periphery of the lid body 16, and an electromagnetic field is induced inside the reaction vessel 12 via the lid body 16 by the coil antenna 58, and plasma is generated. Further, electrons in the plasma are generated. Is supplied with energy, and the plasma is maintained at a high density. A high frequency power source 62 is connected to the coil antenna 58 via a matching unit 60. Further, a shield 64 is provided outside the lid body 16 to prevent the generated high frequency from leaking outside.
[0023]
Further, a transparent window 66 is provided at an appropriate position of the container body 14 so that the inside can be observed. A monochromator 70 is connected to the transparent window 66 through an optical fiber 68. The monochromator 70 is set so as to be able to detect light in a wavelength band unique to Si that is generated when Si is emitted by plasma. The output of the monochromator 70 is sent to the control device 56.
[0024]
Next, a case where a gate electrode is formed by applying the dry etching method of the present invention to the silicon wafer 1 having the layer configuration shown in FIG. 1A using the dry etching apparatus 10 having the above configuration will be described. .
[0025]
First, the silicon wafer 1 is placed on the susceptor 18 in the reaction vessel 12 and fixed by the electrostatic chuck 20. Next, the inside of the reaction vessel 12 is depressurized by a vacuum pump to a predetermined degree of vacuum, for example, about 4 mTorr.
[0026]
Next, the flow rate adjusting valves 44 and 46 are opened at a required opening degree by a signal from the control device 56, and NF ₃ gas and Cl ₂ gas are derived from the gas supply sources 32 and 34, respectively. These gases are mixed in the gas mixing chamber 30 and supplied into the reaction vessel 12 from the gas supply port 28 as the first reactive gas. The ratio of each gas in the first reactive gas is set to 20% to 100% of NF ₃ gas and 80% to 0% of Cl ₂ gas with respect to the total gas flow rate for the reason described later. Is preferred. Note that the Cl ₂ gas is 0% means that the first reactive gas is composed of only NF ₃ gas.
[0027]
When the supply of the first reactive gas is started, the high frequency bias power supply 24 is turned on, and a high frequency bias power of 13.56 MHz, for example, is applied between the container body 14 and the susceptor 18. Since the container body 14 is grounded, the susceptor 18 has a negative potential and functions as a cathode. Further, when high frequency power of 12.56 MHz, for example, is applied to the coil antenna 58 from the high frequency power supply 62, plasma is generated in the reaction vessel 12 and is maintained at a high density. The first reactive gas is dissociated by the plasma, and F ions present in the plasma mainly contribute to the etching of the metal layer 4 and the etching proceeds. At this time, since the F ions travel toward the susceptor 18 having a negative potential, anisotropic etching in the vertical direction is performed.
[0028]
As the etching of the metal layer 4 proceeds, a part of the polysilicon layer 3 is eventually exposed (see FIG. 1B). In the state shown in FIG. 1B, the polysilicon layer 3 is also etched, and the removed layer material floats in the reaction vessel 12 and is dissociated by plasma. Therefore, Si that is a component of the polysilicon layer 3 is contained in the plasma. The presence of Si is detected by the monochromator 70 which is set to detect the wavelength band unique to Si from the emission of the plasma, and the control device 56 enters the state shown in FIG. 1B from the output signal of the monochromator 70. As well as grasping this, the time when Si is detected is determined as the etching end point of the methane layer 4.
[0029]
As is clear from FIG. 1B, since the barrier metal layer 4a in the metal layer 4 still remains in a large amount at this end point, the first time until a predetermined time elapses from the end point. Etching of the metal layer 4 is continued using this reactive gas. At this time, conventionally, the exposed surface of the polysilicon layer 3 becomes significantly rough due to the influence of SF ₆ in the reactive gas. However, in the etching according to the present invention, the etching on the polysilicon layer proceeds gently, and the surface of the polysilicon layer Is etched while maintaining a smooth state. As a condition for performing etching in such a state, it is necessary that at least the selective ratio of W of the first reactive gas to polysilicon is 0.5 or more. This is because the roughness appearing on the surface of the polysilicon layer becomes significant when the selection ratio is less than 0.5. The optimum reactive gas having a selectivity of 0.5 or more is the aforementioned mixed gas of NF ₃ gas 20% to 100% and Cl ₂ gas 80% to 0%.
[0030]
When the set over-etching time has elapsed, as shown in FIG. 1 (c), the bottom of the metal layer beside the wiring is substantially removed, and the surface of the polysilicon layer is exposed in a smooth state. To do. The skirt portion on the side of the wiring of the barrier metal layer causes a residue caused by the subsequent etching of the polysilicon layer and also causes the vertical shape of the gate electrode to be damaged. Since it is removed by over-etching without adversely affecting the silicon layer, the residue is greatly reduced and the desired vertical shape is obtained.
[0031]
Thereafter, the flow rate adjusting valves 44 and 46 are closed, and the gas in the reaction vessel 12 is exhausted. Then, after adjusting the pressure in the reaction vessel 12, the flow rate adjusting valves 46, 48, 50 are opened, and Cl ₂ gas, HBr gas, and O ₂ gas are supplied from the gas supply sources 34, 36, 38 to the gas mixing chamber 30. And supplied into the reaction vessel 12 as a second reactive gas. The composition of the second reactive gas is conventionally known. Using this gas, the polysilicon layer 3 is etched, and finally the mask is removed by ashing or the like (d) in FIG. A gate electrode having a shape as shown in FIG.
[0032]
It is also effective to add NF ₃ gas to the second reactive gas. The Cl ₂ gas, HBr gas, and O ₂ gas described above contribute to the etching of the polysilicon layer, but hardly etch the metal layer. For this reason, when there is little over-etching with respect to the said metal layer, a tailing part will remain in a metal layer. In such a case, if the NF ₃ gas is added, this tailing portion can be effectively removed. As a result, even if the accuracy of setting the time for over-etching is slightly reduced, the etching result is good.
[0033]
As mentioned above, although preferred embodiment of this invention was described in detail, it cannot be overemphasized that this invention is not limited to the said embodiment. For example, the compositions of the first and second reactive gases are not limited to those described above, and other gases can be added as long as the same action can be obtained.
[0034]
Further, since the metal layer 4 of the above embodiment is formed by the PVD method, it has a two-layer structure of the barrier metal layer 4a and the W layer 4b. However, in the case of the CVD method, it is between the barrier metal layer and the W layer. It has a three-layer structure having a W new creation layer. The W nucleation layer is formed using SiH ₄ and WF ₆ as process gases, and is a porous layer. When a metal layer having such a porous W nucleation layer is etched, the surface roughness of the polysilicon layer becomes more prominent. Therefore, the present invention for avoiding the rough surface of the polysilicon layer is particularly effective for the metal layer having such a three-layer structure.
[0035]
【Example】
Next, an example in which the effect of the dry etching method according to the present invention is verified will be described.
[0036]
In this embodiment, a silicon wafer is used as a substrate to be processed, a 5 nm SiO ₂ film is formed on the surface, a 10 nm polysilicon layer is formed thereon, and a 10 nm TiN layer is formed thereon as a barrier metal layer. Has been. Further, a tungsten layer having a thickness of 100 nm is formed on the barrier metal layer, and an SiN mask having a thickness of 160 nm and a width of 0.25 μm is formed thereon with a gap width of 0.25 μm.
[0037]
The dry etching apparatus used in the examples is shown in FIG. 2, and the gas types used are also those shown in the above embodiment. The high frequency power applied between the susceptor and the container body was 13.56 Mhz, and the high frequency power applied to the coil antenna was 12.56 Mhz.
[0038]
In the etching of the metal layer, the pressure in the reaction vessel was 4 mTorr. As the first reactive gas for etching the metal layer, NF ₃ gas has a gas flow rate of 40 sccm (about 33.3% with respect to the total gas flow rate), and Cl ₂ gas has 80 sccm (with respect to the total gas flow rate). About 66.7%) to the reaction vessel. About 34 seconds after the etching of the metal layer was started, Si in the plasma was detected by a monochromator. Further, from the time of detecting Si (end point), overetching of the metal layer was continued for 8 seconds under the same conditions.
[0039]
Thereafter, the pressure in the reaction vessel is maintained at 4 mTorr, and Cl ₂ gas, HBr gas, NF ₃ gas, and O ₂ gas are respectively 60 sccm (about 33.3%), 100 sccm (about 55.6%), and 15 sccm ( About 8.3%) was introduced into the reaction vessel as a second reactive gas at a flow rate of 5 sccm (about 2.8%). Etching of the polysilicon layer with the second reactive gas was performed for about 20 seconds.
[0040]
FIG. 3 shows an etching pattern of a silicon wafer obtained through the above steps. 3A is an SEM micrograph showing the cross-sectional shape of the silicon wafer, and FIG. 3B is an SEM micrograph of the surface of the silicon wafer taken in an overhead view. These photographs are taken of a silicon wafer from which the SiN mask has been removed by ashing and HF cleaning.
[0041]
Comparing FIG. 3 with FIG. 4 used in the description of the prior art, according to the method of the present invention, it is easy for the surface of the polysilicon layer to be etched while maintaining a smooth state. Will be understood. FIG. 3 also shows that the vertical shape of the obtained gate electrode is good.
[0042]
【The invention's effect】
As described above, according to the present invention, by performing dry etching on the polysilicon layer and the metal layer having the W layer as a main layer, the etching is advanced while keeping the surface of the polysilicon layer in a smooth state. be able to. Therefore, adverse effects on the lower layer of the polysilicon layer, such as pitching, can be prevented.
[0043]
Further, since a state where a skirted portion remains on the wiring side of the metal layer can be avoided, the cross-sectional shape obtained after the etching of the metal layer and the polysilicon layer is excellent in a vertical shape.
[0044]
Therefore, the present invention can cope with future miniaturization and higher performance of the semiconductor integrated circuit.
[Brief description of the drawings]
BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic explanatory view showing an embodiment in which a dry etching method of the present invention is applied to a silicon wafer having a polysilicon layer and a W metal layer, and FIGS. It is a figure which shows the change of the cross-sectional shape from after a process to after a process.
FIG. 2 is a cross-sectional view schematically showing one embodiment of a dry etching apparatus according to the present invention.
FIGS. 3A and 3B are SEM micrographs showing an etching pattern of a silicon wafer obtained according to an embodiment of the present invention, where FIG. 3A shows its cross-sectional shape, and FIG. 3B shows the surface of the silicon wafer in an overhead view. It is a micrograph.
4 is an SEM micrograph similar to FIG. 4, showing an etching pattern of a silicon wafer obtained by a conventional dry etching method.
[Explanation of symbols]
1 ... silicon wafer (substrate to be processed), 2 ... SiO ₂ film, 3 ... polysilicon layer, 4 ... metal layer, 4a ... barrier metal layer, 4b ... tungsten layer, 5 ... mask, 10 ... dry etching apparatus, 12 ... reaction vessel, 18 ... susceptor, 24 ... high frequency bias power supply (bias means), 32 ... NF ₃ gas supply source, 34, 36, 38 ... gas supply source, 44 to 50 ... flow control valve, 56 ... controller, 62 ... High frequency power source (plasma generating means), 70... Monochromator (silicon detecting means).

Claims (3)

A first step of disposing a substrate to be processed having a polysilicon layer and a metal layer including a barrier metal layer and a tungsten layer formed thereon on a susceptor in a reaction vessel;
A second step of reducing the pressure in the reaction vessel to a predetermined pressure;
A third step of applying a negative bias power to the susceptor;
Supplying a first reactive gas containing NF ₃ gas into the reaction vessel, and forming a plasma in the reaction vessel to etch the metal layer;
After the completion of the fourth step, the gas in the reaction vessel is exhausted to supply a second reactive gas into the reaction vessel, and plasma is formed in the reaction vessel to form the polysilicon layer. the a dry etching method comprising a fifth step of etching,
A dry etching method, wherein NF ₃ gas is added to the second reactive gas . The first reactive gas is composed of NF ₃ gas or NF ₃ gas and Cl ₂ gas, wherein NF ₃ gas is 20% to 100% and Cl ₂ gas is 80% to 0%. The dry etching method according to claim 1. A first step of disposing a substrate to be processed having a polysilicon layer and a metal layer including a barrier metal layer and a tungsten layer formed thereon on a susceptor in a reaction vessel;
A second step of reducing the pressure in the reaction vessel to a predetermined pressure;
A third step of applying a negative bias power to the susceptor;
A fourth step of supplying a first reactive gas into the reaction vessel and forming a plasma in the reaction vessel to etch the metal layer;
After completion of the fourth step, the gas in the reaction vessel is exhausted to supply a second reactive gas containing NF ₃ gas into the reaction vessel, and plasma is formed in the reaction vessel. And a fifth step of etching the polysilicon layer.

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