JP4050091B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of repairing a data defect accompanying power saving.
[0002]
[Prior art]
With the miniaturization, large capacity, and power saving of semiconductor memory, it is difficult to ensure reliability of a memory cell having a fine structure, particularly in terms of process and transistor characteristics. Among semiconductor memories, SRAM is difficult to reduce in size and increase in capacity because a memory cell is composed of a plurality of transistors (6 transistors in a full CMOS type). On the other hand, a DRAM memory cell is composed of one transistor and one capacitor, which is suitable for downsizing and large capacity.
[0003]
Considering the characteristics of such SRAM and DRAM, for example, in a small portable electronic device or the like, a part of a memory system conventionally configured using SRAM is replaced with pseudo SRAM (Pseudo-SRAM; PSRAM) using DRAM cells. ) Is considered to be miniaturized. Normally, DRAM multiplexes row and column addresses, whereas SRAM does not multiplex addresses. Therefore, if the SRAM interface is used as it is, the PSRAM is used without address multiplexing. Further, since DRAM requires a data refresh operation, it is necessary to incorporate an automatic refresh circuit inside PSRAM.
[0004]
[Problems to be solved by the invention]
As described above, since the PSRAM uses DRAM cells, the data holding current is larger than that of the SRAM, but it is suitable for downsizing and increasing the capacity of the system. However, if the power saving is further promoted, the data retention characteristics of the memory cells deteriorate, and even if an automatic refresh circuit is incorporated, the generation of defective data becomes a problem due to the deterioration of the data retention characteristics.
Deterioration of data retention characteristics due to power saving is not unique to PSRAM, and similarly becomes a problem in ordinary DRAMs and even EEPROMs.
[0005]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having a preferable mode for relieving data failure.
[0006]
[Means for Solving the Invention]
  This inventionOne embodimentA semiconductor memory device according to the present invention includes a normal data portion used for normal data writing and reading, and a cell array including a parity data portion for storing inspection data for performing error detection of read data from the normal data portion, A data buffer for temporarily storing read data from the cell array and write data to the cell array; and generating test data to be stored in the parity data portion from the write data input at the time of data writing, and the normal data at the time of data reading Error detection and correction of data read based on the data read from the data section and the inspection data read from the parity data sectionAnd a syndrome generation circuit for generating a syndrome signal based on the read data and inspection data, and a syndrome decode / error correction circuit for decoding the generated syndrome signal and correcting an error bit.Error detection and correction circuitA timing signal generation circuit for detecting a change in output data in the data buffer and generating a timing signal; and the syndrome signal in the syndrome decode / error correction circuit controlled by the timing signal generated by the timing signal generation circuit And a correction timing adjustment circuit for adjusting the error bit correction timing or the error bit correction timingIt is characterized by
[0007]
The error detection / correction circuit performs, for example, single-bit error correction using a Hamming code, and the inspection data stored in the parity data portion is configured with the minimum number of bits necessary for error detection / correction of read data. The More preferably, the inspection data stored in the parity data portion is configured with a bit number one bit more than the minimum number of bits necessary for error detection and correction of the read data.
[0008]
The error detection and correction circuit does not perform error correction when there is an error in the m-bit data portion to be rewritten, and performs error correction when there is an error in other than the m-bit data portion to be rewritten.
The error detection / correction circuit does not correct the corresponding cell data in the normal data portion even if there is an error correction of the read data in the data read cycle. Further, when the cell array is a DRAM cell array in which data is refreshed at a predetermined cycle, the error detection / correction circuit is stopped during the refresh operation of the DRAM cell array.
[0010]
  Preferably,N-bit parallel data is exchanged between the data buffer and the normal data portion of the cell array, and m-bit parallel data (where m <n) is exchanged between the data buffer and the external input / output terminal. Yes, n-bit data including m-bit data to be rewritten is read in parallel in the first half of the data write cycle, and error detection and correction of the n-bit data is performed in the error detection and correction circuit. In the second half of the data write cycle, Of the n-bit parallel data corrected by the error detection and correction circuit, the m-bit data portion to be rewritten is replaced with the m-bit parallel data supplied from the external input / output terminal and transferred to the normal data portion.
[0011]
The error detection / correction circuit is preferably configured to be able to switch between the active state and the inactive state by controlling the active state and the inactive state of the timing signal generation circuit from the outside. Furthermore, it is preferable to provide a monitor terminal that outputs the output of the correction timing adjustment circuit as a monitor signal that informs the outside of the presence or absence of error correction.
[0012]
  In another embodiment of the invention, the syndrome decoding / errorThe correction circuit includes a first NAND gate for detecting a combination of “1” data of a syndrome signal, a NOR gate for detecting a combination of “0” data, and an inversion of the output of the first NAND gate. A second NAND gate for detecting coincidence of the signal and the NOR gate outputA syndrome decoding circuit is included.
[0013]
  In still another embodiment of the present invention, the syndrome decoding / errorThe correction circuit includes a NAND gate array in which NAND gates for detecting a combination of “1” data of the syndrome signal are arranged.A syndrome decoding circuit.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a basic configuration of a semiconductor memory according to an embodiment of the present invention. This semiconductor memory is a PSRAM configured using DRAM cells. In this embodiment, in order to relieve a data defect in the cell array 1, an error check of read data is performed between the cell array 1 and the I / O buffer 6 to perform error correction. correcting: ECC) The circuit 7 is interposed. The ECC circuit 7 performs single-bit error detection and correction using a Hamming code.
[0016]
The DRAM cell array 1 includes a normal data portion 1a for performing normal data storage, a parity data portion 1b for storing inspection data for ECC, specifically, parity data for determining odd / even of syndrome. Consists of. The word line WL that is selectively driven by the row decoder / word line driver 2 is arranged so as to continue from the normal data portion 1a to the parity data portion 1b, and a DRAM cell is located at the intersection of the word line WL and the bit line BL. MC is provided.
[0017]
A sense amplifier 3 is connected to the bit line BL of the cell array 1. The bit line BL is selected by the column gate 4 and data transfer is performed with the data line DQ. The data line DQ is provided with a DQ buffer 5, and an ECC circuit 7 is disposed between the DQ buffer 5 and the I / O buffer 6.
[0018]
The ECC circuit 7 includes a read / write driver 71 that relays read / write data between the DQ buffer 5 and the I / O buffer 6. The ECC circuit 7 also includes a check bit generation circuit 73 that generates check data for writing to the parity data portion 1b based on the write data WD supplied from the I / O terminal. In the case of single-bit error correction (single-error-correction), the check bit generation circuit 73 generates a correctable codeword (Hamming code) having a code length of N + M from N bits of data. M-bit inspection data is generated. Specifically, let hamming codeword be vector V, and check matrix H, which is an M-digit binary matrix, HV^TInspection data is generated so as to satisfy = 0.
[0019]
The ECC circuit 7 also includes a syndrome generation circuit 75 that generates a syndrome signal based on the inspection data PRWD read from the parity data portion 1b and the data RD read from the normal data portion 1a. The information bit generation circuit 74 is configured by an exclusive OR gate array, and generates M bits of information bits used for syndrome generation based on the read data RD and predetermined check matrix data. It is sent to the syndrome generation circuit 75. The syndrome generation circuit 75 is configured by an exclusive OR gate array, and receives M bits of information bits generated by the information bit generation circuit 74 and M bits of inspection data PRWD, and receives an M bit syndrome signal. Is generated.
[0020]
A syndrome decode / error correction circuit 72 is provided in the read / write driver 71. The syndrome decode / error correction circuit 72 decodes the syndrome signal generated by the syndrome generation circuit 75 to detect an error and correct an error bit. The syndrome decode circuit generates a syndrome signal S (= HV^T) Is a NAND / NOR gate array or a NAND gate array for detecting a column corresponding to an error bit in a check matrix that is not “0”.
[0021]
In FIG. 1, the read data RD and the write data WD are shown as if they are transferred through different data lines, but actually they are transferred at different timings on the same data bus. The same applies to I / O data between the read / write driver 71 and the I / O buffer 6. The same applies to the following embodiments.
[0022]
The operation of the semiconductor memory configured as described above will be described. At the time of data reading, the ECC circuit 7 compares the data RD read from the normal data portion 1a with the test data PRWD read from the parity data portion 1b by the syndrome generation circuit 75 to generate a syndrome signal. To do. By decoding, the syndrome signal is “0” at the address where there is no error in the Hamming code check matrix, and “1” is output at the address where the error has occurred. In the read / write driver 71, the syndrome decode / correction circuit 72 decodes the syndrome signal to detect an error, inverts the bit data at the address where the error is detected, and outputs the corrected data to the outside.
[0023]
At the time of data writing, inspection data is generated in the ECC circuit 7 from external write data WD. Then, the write data WD is simultaneously written in the normal data portion 1a, and the generated test data is simultaneously written in the parity data portion 1b.
[0024]
As described above, by incorporating the ECC circuit, correct data corrected based on the inspection data can be read even if the data retention characteristics of the memory cell array 1 are somewhat deteriorated due to power saving. Although not shown in the drawing, by using in combination with a redundant circuit system for replacing defective cells, high relief efficiency can be obtained when various cell defects are included. The redundant circuit method cannot cope with cell defects after packaging, but the ECC circuit can also cope with this.
[0025]
The same applies to the following embodiments. However, when data is read, the ECC circuit outputs correct data externally even if there is an error in the cell data. Data correction is not performed.
Further, the ECC circuit 7 can also detect an error bit of the inspection data in the parity data portion 1b in the case of 1-bit error correction using a Hamming code. However, the fact that there is an error bit in the parity data portion 1b means that the data in the normal data portion 1a is correct. Therefore, it is not necessary to correct the data in the parity data portion 1b.
[0026]
FIG. 2 is a more specific configuration example of the ECC circuit 7 in FIG. Here, a case where n-bit parallel data is transferred between the data buffer 5 and the cell array 1 and an m-bit parallel data is transferred between the data buffer 5 and the I / O terminal is handled. However, m and n are positive integers (preferably a power of 2), and m <n. Specifically, FIG. 2 shows an example in which m = 16 and n = 64.
[0027]
The parallel read / write data in the normal data portion 1a of the memory cell array 1 is n = 64 bit data. The ECC circuit 7 performs 1-bit error correction using a Hamming code. In general, for n data bits, the number of check bits k required for 1-bit error correction is 2^kIt is represented by ≧ n + k + 1. The minimum number of inspection bits k required for 1-bit error detection / correction of n = 64-bit data is k = 7. Accordingly, the parity data portion 1b is accessed simultaneously with the 64-bit parallel data area, and 7-bit test data is read / written.
[0028]
The ECC circuit 7 reads 64-bit data of the normal data portion 1a at the time of data reading, and simultaneously reads 7-bit inspection data from the parity data portion 1b. Based on these data, a syndrome calculation is performed by the syndrome generation circuit 75 to generate a 7-bit syndrome signal. The syndrome signal is transferred to the read / write driver 71 and decoded. Thereby, a 1-bit error is detected and corrected.
[0029]
The number of I / O terminals is m = 16. That is, the ECC circuit 7 exchanges 64-bit parallel data with the cell array 1 via the data buffer 5, but between the ECC circuit 7 and the I / O buffer 6 (and thus the I / O terminal), Transfer of 16-bit parallel data. This assumes a page mode, and the 64-bit data read by the ECC circuit 7 can be serially read out 16 bits at a time.
[0030]
In this embodiment, the data write cycle is divided into a first half and a second half. That is, data writing is performed in 16-bit units from the external terminal, but in the first half of the write cycle, 64-bit data including 16-bit data to be rewritten in the normal data portion 1a is first read in parallel. The ECC circuit 7 performs error detection and correction on the read data. In the latter half of the write cycle, 16 bits of the 64-bit data error-corrected in the ECC circuit 7 are replaced with 16-bit write data supplied from outside in the read / write driver 71. The partially overwritten 64-bit data is transferred and written to the normal data portion 1a. At the same time, test data is generated based on the partially overwritten 64-bit write data, and this is written into the parity data portion 1b.
[0031]
In this way, when 16 bits of 64-bit parallel read data are overwritten with external data, it is not necessary to perform error correction on the overwritten portion. Therefore, when an error bit position of 64-bit data is detected, it is determined whether or not it is within the address of the write data. If the error bit position is within the address of the write data, error correction is not performed. Since the normal write address is held in the chip during the write cycle, such an address determination can be performed. Then, only when the error bit is not the same address as the 16-bit data supplied from the outside, the error bit part is corrected by the correction circuit 72, and the remaining part is rewritten by the external data, and then the 64-bit part is converted to normal data. Write to the part in parallel.
[0032]
The ECC circuit 7 has a function of performing error detection and correction even if there is an error in the read data and outputting it to the outside as correct data. When new data is written, the ECC circuit 7 generates test data based on the written data and rewrites the parity data portion 1b. Therefore, if data exchange between the normal cell unit 1a and the read / write driver 71 and data exchange between the read / write driver 71 and the external terminal are performed with the same number of bits, error detection and correction are performed in the write cycle. There is no need to do it. Even if there is an error in the data held at the address to be written in the normal data part 1a, the erroneous data part is overwritten by the write data and rewritten with the correct data, and the inspection data in the parity data part 1b is also It is because it is updated.
[0033]
However, the memory chip has a page mode and the like, and data exchange with an external terminal is performed in units of 16 bits. However, there is a problem when 64 bits are accessed in parallel inside the chip. In such a mode, (64-16) bits other than 16 bits to be rewritten are normally rewritten while being read inside the chip. This is because incorrect bit data is rewritten as it is. Therefore, as described above, by performing error detection correction of read data in the first half of the write cycle, it is possible to prevent a situation where erroneous data is rewritten as it is. When the ECC circuit 7 performs 1-bit error correction, it is possible to make the ECC circuit function highly reliable by performing such data writing.
[0034]
FIG. 3 shows another configuration example of the ECC circuit 7 of FIG. In the memory cell array 1, the normal data portion 1a has 64 bits, and the parity data portion 1b has 8 bits, which is 1 bit more than the case of FIG. The ECC circuit 7 is a case of single bit error correction using a Hamming code.
[0035]
The ECC circuit 7 reads 64-bit data of the normal data portion 1a at the time of data reading, and simultaneously reads 8-bit inspection data from the parity data portion 1b. Based on these data, a syndrome calculation is performed by the syndrome generation circuit 75 to generate an 8-bit syndrome signal. The syndrome signal is transferred to the read / write driver 71 and decoded. Thereby, a 1-bit error is detected and corrected.
[0036]
Also in this embodiment, the data write cycle is divided into a first half and a second half as in the embodiment of FIG. That is, data writing is performed in units of 16 bits, but in the first half of the write cycle, the 64-bit data of the normal data portion 1a including the write address is read to the ECC circuit 7 via the DQ buffer 5 to perform error detection and correction. Do. In the second half, 16 bits of 64-bit data corrected by 1 bit are replaced with 16-bit data supplied from outside in the read / write driver 71, and the normal data portion 1a and parity data portion 1b are replaced. Write to.
[0037]
Thereby, the same effect as the embodiment of FIG. 2 can be obtained. Further, according to this embodiment, by setting the check data to 8 bits, the variation of the configuration of the syndrome decode circuit that decodes the syndrome signal and detects the correction address of the check matrix increases. This will be specifically described in comparison with the case of FIG. As in the embodiment of FIG. 2, when the check data is 7 bits, a combination of “1” for 3 bits and “0” for 4 bits is added to each 7-bit column constituting the check matrix of the Hamming code. Suppose you use it. At this time, there are a maximum of 35 combinations. In addition, there are a maximum of 35 combinations of “1” for 4 bits and “0” for 3 bits. Therefore, when the check bits are 7 bits, a check matrix in which all 64 bits of data are linearly independent cannot be formed.
[0038]
On the other hand, if the inspection data is 8 bits as in the embodiment of FIG. 3, there are a maximum of 70 combinations of “1” for 4 bits and “0” for 4 bits. Therefore, a check matrix that is all linearly independent of 64 bits can be formed. In this case, the syndrome decoding circuit can be constituted by a gate array that detects a 4-bit “1” or “0” data pattern. Therefore, the pattern layout is advantageous.
[0039]
When 7-bit test data is used as in the embodiment of FIG. 2, the check matrix and code of the Hamming code are given as 7-digit binary numbers other than 0. At this time, the syndrome signal is used to obtain the address of the 1-bit error in the check matrix, but the preferred configuration of the syndrome decoding circuit is a NOR / NAND configuration as shown in FIG. In this case, when an error of 2 bits or more occurs, a syndrome in which all 7 bits are “1” may be generated. At this time, only “1” or “0” of the syndrome is detected and decoded. This is because a situation occurs in which a plurality of correct data is rewritten.
[0040]
That is, the syndrome decoder has a 3-input NAND gate G1 for detecting that all “1” bits of the 7-digit syndrome signal are “1”, and all “0” bits are “0”. 4 input NOR gate G2 is also provided. An NAND gate G4 for inverting the output of the NAND gate G1 by the inverter gate G3 and detecting that both the output of the NAND gate G1 and the output of the NOR gate G2 are “1” is arranged. Specifically, this is for a data bit in which the syndrome is composed of a combination of 3-bit “1” and 4-bit “0”. As described above, when the check bits are 7 bits, all 64 bits cannot be a primary independent check matrix, and in order to form a 64-bit decoder, the combination of the NAND gate G1 and the NOR gate G2 It is necessary to change the number of inputs. As a result, when there is no error in the read data, the decode outputs are all “0”, and when there is an error, the output of the corresponding address of the check matrix is “1”.
[0041]
Even when 8-bit test data is used as in the embodiment of FIG. 3, a syndrome decode circuit having a NOR / NAND configuration can be used as shown in FIG. On the other hand, when the test data is 8 bits, and therefore the syndrome signal is 8 bits, a syndrome decode circuit can be configured by inputting only 4 bits. That is, as shown in FIG. 9, a decoding circuit can be configured using only a 4-input NAND gate that detects coincidence of 4-bit “1” data. This is because, when the test data is 8 bits, a syndrome of 64 bits of data bits can be generated by a combination of 4 bits “1” and 4 bits “0”, and only 4 bits “1” coincidence detection This is because the error address can be detected.
[0042]
FIG. 4 shows a modified embodiment of the ECC circuit 7 of FIG. The basic configuration and operation of the ECC circuit 7 are the same as those in FIG. 3 except that a timing signal TC for setting the error correction timing to the syndrome decode / correction circuit 72 in the read / write driver 71 is used. That is. The timing signal generation circuit 8 internally generates a timing signal TC in synchronization with data reading from the normal data portion 1a.
[0043]
FIG. 5 shows a configuration example of the timing signal generation circuit 8 in relation to the DQ buffer 5. The data lines DQ and / DQ connected to the cell array 1 are provided with a write circuit 51 that converts and supplies write data WD into a complementary signal, and a buffer amplifier 52 such as a current mirror amplifier that amplifies read data. . A read data line RD is connected to the drain of the NMOS transistor QN1 driven by the output of the buffer amplifier 52.
[0044]
The read data from the DQ buffer 5 is not usually a complementary signal, but in the configuration of FIG. 5, the buffer amplifier 52 which is a current mirror type differential amplifier is a differential output type. An NMOS transistor QN2 driven in a complementary manner to the NMOS transistor QN1 in the output stage driven by the buffer amplifier 52 is added, and the data line / RD is connected to the drain thereof. An exclusive OR gate (EXOR gate) 81 is provided which receives the outputs of these complementary data lines RD and / RD. The output of the EXOR gate 81 is input to the NAND gate 82 together with the control signal CNT. Thereby, the correction timing signal TC that becomes “L” only when the control signal CNT is “H” and data is read can be obtained from the NAND gate 82.
[0045]
For example, the syndrome decode / correction circuit 72 may be controlled by the timing signal TC as follows. As shown in FIG. 6A, the syndrome decode / correction circuit 72 includes a syndrome decode circuit 72a and an error correction circuit 72b. Before this syndrome decode circuit 72a, a correction timing adjustment circuit (transfer switch circuit) 72c for controlling the transfer of the syndrome signal output from the syndrome generation circuit 75 to the decode circuit 72a by the timing signal TC is provided. Alternatively, as shown in FIG. 6B, a correction timing adjustment circuit 72c is provided between the decode circuit 72a and the error correction circuit 72b to turn on transfer of the decode signal with the timing signal TC.
[0046]
In this way, if the control is performed such that the syndrome decode / correction circuit 72 is activated only when data is read using the timing signal TC, a situation in which the syndrome decode / correction circuit 72 malfunctions due to noise or the like is prevented. can do.
[0047]
FIG. 10 is based on the ECC circuit 7 of FIG. 3 and outputs an error monitor signal MT to the external monitor terminal when an error is detected and corrected by the syndrome decode / correction circuit 72. . Thereby, the operation of the ECC circuit 7 can be confirmed. The correction monitor signal MT may be 1 bit in order to notify only the presence or absence of correction. It is also effective to output a correction monitor signal MT of a plurality of bits so that the correction position can be confirmed.
[0048]
Specifically, such an error correction monitor signal MT may correspond to FIG. 6A or 6B, and the output of the correction timing adjustment circuit 72c may be the monitor signal MT as shown in FIG. 11A or FIG. 11B.
[0049]
In each of the above embodiments, it is preferable for the ECC circuit function check to enable the ECC circuit 7 to be turned on and off. As shown in FIG. 5, this is possible by enabling the control signal CNT of the output stage NAND gate 82 of the timing signal generation circuit 8 to be turned on and off from the outside. For example, the ECC circuit 7 is turned on, and test data is written by the write operation described in the previous embodiment. Then, the ECC circuit 7 is turned off, and the previously written test data is rewritten with data different only in certain bits. This means that an error state is forcibly created because the parity data portion has not been updated. Then, the ECC circuit 7 is turned on again to read test data. Thereby, it is possible to confirm whether or not the ECC circuit 7 operates normally.
[0050]
The DRAM cell array needs to be refreshed at a certain cycle. For this reason, the DRAM chip incorporates, for example, a refresh circuit that automatically performs a refresh operation, but data is not read into the DQ buffer 5 during the refresh operation. Therefore, in the embodiment of FIG. 4, the correction timing signal generation circuit 8 does not operate during the refresh cycle, and the operation of the ECC circuit 7 stops. Thereby, useless power consumption can be reduced.
[0051]
【The invention's effect】
As described above, the semiconductor memory according to the present invention can remedy a data defect especially due to power saving by incorporating an ECC circuit.
[Brief description of the drawings]
1 is a diagram showing a configuration of a semiconductor memory according to an embodiment of the present invention;
FIG. 2 is a diagram showing a configuration of an ECC circuit in a semiconductor memory according to another embodiment.
FIG. 3 is a diagram showing a configuration of an ECC circuit in a semiconductor memory according to another embodiment.
FIG. 4 is a diagram showing a configuration of an ECC circuit in a semiconductor memory according to another embodiment.
FIG. 5 is a diagram showing a configuration of a correction timing signal generation circuit unit of the same embodiment;
FIG. 6A is a diagram showing a configuration of an error detection / correction circuit unit according to the embodiment;
FIG. 6B is a diagram showing another configuration of the error detection / correction circuit unit according to the embodiment;
FIG. 7 is a diagram illustrating a configuration of a syndrome signal decoding circuit.
FIG. 8 is a diagram showing another configuration of a syndrome signal decoding circuit.
FIG. 9 is a diagram showing another configuration of a syndrome signal decoding circuit.
FIG. 10 is a diagram showing a configuration of an ECC circuit of a semiconductor memory according to another embodiment.
FIG. 11A is a diagram showing a configuration of a correction monitor signal generation unit of the same embodiment;
FIG. 11B is a diagram showing another configuration of the correction monitor signal generation unit of the same embodiment;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 1a ... Normal data part, 1b ... Parity data part, 2 ... Row decoder / word line driver, 3 ... Sense amplifier, 4 ... Column gate, 5 ... DQ buffer, 6 ... I / O buffer, 7 ... ECC circuit, 8 ... correction timing adjustment signal generation circuit, 71 ... read / write driver, 72 ... syndrome decode / error correction circuit, 72a ... decode circuit, 72b ... error correction circuit, 72c ... correction timing adjustment circuit, 73 ... inspection Data generation circuit, 74... Information data generation circuit, 75.

Claims (11)

A cell array including a normal data portion used for normal data writing and reading, and a parity data portion for storing inspection data for performing error detection of read data from the normal data portion;
A data buffer for temporarily storing read data from the cell array and write data to the cell array;
Data for inspection to be stored in the parity data portion is generated from write data input at the time of data writing, and data read from the normal data portion and data for inspection read from the parity data portion at the time of data reading A syndrome generation circuit for generating a syndrome signal based on the read data and inspection data and an error bit by decoding the generated syndrome signal for performing error detection and correction of the data read based on An error detection / correction circuit having a syndrome decode / error correction circuit for correcting
A timing signal generation circuit that detects a change in output data in the data buffer and generates a timing signal;
A correction timing adjustment circuit that is controlled by the timing signal generated by the timing signal generation circuit and adjusts the decoding timing of the syndrome signal or the correction timing of the error bit in the syndrome decoding / error correction circuit ;
A semiconductor memory device comprising: Said error checking and correcting circuit, the activity of the timing signal generating circuit from the outside, by controlling the inactive state, activity, according to claim 1, wherein the switching of the non-activated state can be characterized by being composed Semiconductor memory device. 3. The semiconductor memory device according to claim 1, further comprising: a monitor terminal that outputs an output of the correction timing adjustment circuit as a monitor signal that informs the outside of whether or not error correction is performed. The syndrome decode / error correction circuit includes a first NAND gate for detecting a combination of “1” data of a syndrome signal, a NOR gate for detecting a combination of “0” data, and the first NAND 4. The semiconductor memory device according to claim 1, further comprising: a syndrome decode circuit including a second NAND gate that detects a match between an inverted signal of a gate output and the NOR gate output. 5. . Wherein said syndrome decode / error correction circuit, characterized in <br/> have a syndrome decode circuit constituted by the NAND gate array and the NAND gate are arranged for detecting the combination of "1" data of the syndrome signals Item 4. The semiconductor memory device according to any one of Items 1 to 3 . The error detection and correction circuit performs single-bit error correction using a Hamming code, and the inspection data stored in the parity data portion is configured with a minimum number of bits necessary for error detection and correction of read data. and that it semiconductor memory device according to any one of claims 1 to 4, characterized in. The error detection / correction circuit performs single-bit error correction using a Hamming code, and the inspection data stored in the parity data portion is 1 bit from the minimum number of bits necessary for error detection / correction of read data. 6. The semiconductor memory device according to claim 1, wherein the semiconductor memory device has a large number of bits. N-bit parallel data is exchanged between the data buffer and the normal data portion of the cell array, and m-bit parallel data (m <n) is exchanged between the data buffer and the external input / output terminal. And
In the first half of the data write cycle, n-bit data including m-bit data to be rewritten is read in parallel, and the error detection and correction circuit performs error detection and correction of the n-bit data.
In the second half of the data write cycle, the m-bit data portion to be rewritten in the n-bit parallel data corrected by the error detection and correction circuit is replaced with the m-bit parallel data supplied from the external input / output terminal, and the normal data the semiconductor memory device of any one of claims 1 to 7, characterized in that it is transferred to the part. The error detection and correction circuit does not perform error correction when there is an error in the m-bit data portion to be rewritten, and performs error correction when there is an error in the portion other than the m-bit data portion to be rewritten. A semiconductor memory device according to claim 8 . Said error checking and correcting circuit, in the data read cycle, any one of claims 1 to 9, characterized in that even if error correction of the read data is not performed to correct the corresponding cell data of the normal data area A semiconductor memory device according to item . The cell array is a DRAM cell array in which data is refreshed at a predetermined cycle,
The semiconductor memory device according to claim 1, wherein the error detection / correction circuit is stopped during a refresh operation of the DRAM cell array.

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