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JP4042741B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP4042741B2
JP4042741B2 JP2004362117A JP2004362117A JP4042741B2 JP 4042741 B2 JP4042741 B2 JP 4042741B2 JP 2004362117 A JP2004362117 A JP 2004362117A JP 2004362117 A JP2004362117 A JP 2004362117A JP 4042741 B2 JP4042741 B2 JP 4042741B2
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base plate
forming
semiconductor
paste
forming sheet
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JP2006173285A (en
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一郎 三原
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Priority to JP2004362117A priority Critical patent/JP4042741B2/en
Priority to US11/302,592 priority patent/US7459340B2/en
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Publication of JP4042741B2 publication Critical patent/JP4042741B2/en
Priority to US12/262,481 priority patent/US20090065926A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

この発明は半導体装置の製造方法に関する。 The present invention relates to a method of manufacturing a semiconductor device.

従来の半導体装置には、ＣＳＰ(chip size package)と呼ばれる半導体構成体のサイズ外にも接続端子としての半田ボールを備えるため、上面側に複数の柱状電極を有する半導体構成体をベース板の上面に接着層を介して接着し、半導体構成体の周囲におけるベース板の上面に絶縁層を設け、半導体構成体および絶縁層の上面に上層絶縁膜を設け、半導体構成体の柱状電極上における上層絶縁膜に開口部を設け、上層絶縁膜の上面に上層配線を上層絶縁膜の開口部を介して半導体構成体の柱状電極に接続させて設け、上層配線の接続パッド部を除く部分をオーバーコート膜で覆い、上層配線の接続パッド部上に半田ボールを設けたものがある（例えば、特許文献１参照）。   Since the conventional semiconductor device includes solder balls as connection terminals in addition to the size of the semiconductor structure called CSP (chip size package), the semiconductor structure having a plurality of columnar electrodes on the upper surface side is provided on the upper surface of the base plate. The insulating layer is provided on the upper surface of the base plate around the semiconductor structure, the upper insulating film is provided on the upper surface of the semiconductor structure and the insulating layer, and the upper insulating layer on the columnar electrode of the semiconductor structure is provided. An opening is provided in the film, an upper layer wiring is provided on the upper surface of the upper insulating film by being connected to the columnar electrode of the semiconductor structure through the opening of the upper insulating film, and the portion other than the connection pad portion of the upper layer wiring is an overcoat film And a solder ball is provided on the connection pad portion of the upper wiring (see, for example, Patent Document 1).

特開２００４−２２１４１７号公報（図１）JP 2004-221417 A (FIG. 1)

ところで、上記従来の半導体装置では、上層配線を電解メッキにより形成しているが、上層配線の一部は、上層絶縁膜の開口部を介して半導体構成体の柱状電極に接続させるために、上層絶縁膜の開口部内に形成される。一方、ＣＳＰと呼ばれる半導体構成体の高密度化により柱状電極の径が小さくなると、これに伴い、柱状電極上における上層絶縁膜に形成される開口部の径も小さくなる。そして、上層配線を形成するための電解メッキ時に、上層絶縁膜の径の小さい開口部内に気泡などが入り込むと、この入り込んだ気泡などが排出されにくくなり、気泡などが入り込んだ開口部内にメッキ液が浸透せず、ボイドが発生し、断線や接触不良が発生するという問題がある。   By the way, in the conventional semiconductor device, the upper layer wiring is formed by electrolytic plating. However, a part of the upper layer wiring is connected to the columnar electrode of the semiconductor structure through the opening of the upper layer insulating film. It is formed in the opening of the insulating film. On the other hand, when the diameter of the columnar electrode is reduced by increasing the density of the semiconductor structure called CSP, the diameter of the opening formed in the upper insulating film on the columnar electrode is accordingly reduced. When electrolytic plating for forming the upper layer wiring is performed, if bubbles or the like enter into the opening having a small diameter of the upper insulating film, it becomes difficult for the bubbles to enter, and the plating solution enters the opening into which the bubbles enter. Does not penetrate, voids are generated, and disconnection and poor contact occur.

そこで、この発明は、絶縁膜などに形成される上下導通用の開口部の径が小さくなっても、配線を形成するための電解メッキ時に当該開口部内に気泡などが全く入り込まないようにすることができる半導体装置の製造方法を提供することを目的とする。 Therefore, the present invention prevents bubbles from entering the openings at the time of electrolytic plating for forming wiring even if the diameter of the opening for vertical conduction formed in the insulating film or the like is reduced. An object of the present invention is to provide a method for manufacturing a semiconductor device capable of performing

この発明の半導体装置の製造方法は、上記目的を達成するため、少なくとも半硬化状態の熱硬化性樹脂を含む絶縁材料からなるベース板形成用シートに上下導通用の開口部を形成する工程と、前記ベース板形成用シートの開口部内に導電性ペーストからなる上下導通部形成用ペーストを充填する工程と、前記上下導通部形成用ペーストを含む前記ベース板形成用シート上に、半導体基板、該半導体基板の一面に設けられた複数の外部接続用電極を有する複数の半導体構成体を相互に離間させて配置する工程と、前記ベース板形成用シート中の熱硬化性樹脂を硬化させてベース板を形成するとともに、前記上下導通部形成用ペーストを硬化させて上下導通部を形成し、且つ、前記ベース板上に前記半導体構成体を、前記外部接続用電極を前記上下導通部に食い込ませた状態で、固着する工程と、少なくとも前記半導体構成体の周囲における前記ベース板上に絶縁層を形成する工程と、前記半導体構成体間において前記絶縁層および前記ベース板を切断して、前記半導体構成体が少なくとも１つ含まれる半導体装置を複数個得る工程と、を含むことを特徴とするものである。
また、この発明は、少なくとも半硬化状態の熱硬化性樹脂を含む絶縁材料からなるベース板形成用シートに上下導通用の開口部を形成する工程と、前記ベース板形成用シートの開口部内およびその上方に導電性ペーストからなる上下導通部形成用ペーストを形成する工程と、前記上下導通部形成用ペーストを含む前記ベース板形成用シート上に、半導体基板および該半導体基板の一面に設けられた複数の再配線を有する複数の半導体構成体を相互に離間させて配置する工程と、前記ベース板形成用シート中の熱硬化性樹脂を硬化させてベース板を形成するとともに、前記上下導通部形成用ペーストを硬化させて上下導通部を形成し、且つ、前記ベース板上に前記半導体構成体を、前記再配線の接続パッド部を前記上下導通部に接続させ、且つ、前記再配線を前記ベース板に埋め込んだ状態で、固着する工程と、少なくとも前記半導体構成体の周囲における前記ベース板上に絶縁層を形成する工程と、前記半導体構成体間において前記絶縁層および前記ベース板を切断して、前記半導体構成体が少なくとも１つ含まれる半導体装置を複数個得る工程と、を含むことを特徴とするものである。
さらに、この発明は、少なくとも半硬化状態の熱硬化性樹脂を含む絶縁材料からなるベース板形成用シートに上下導通用の開口部を形成する工程と、前記ベース板形成用シートの開口部内およびその上方に導電性ペーストからなる上下導通部形成用ペーストを形成する工程と、前記上下導通部形成用ペーストを含む前記ベース板形成用シート上に、半導体基板、該半導体基板の一面に設けられた複数の再配線および該再配線の接続パッド部以外を覆うオーバーコート膜を有する複数の半導体構成体を相互に離間させて配置する工程と、前記ベース板形成用シート中の熱硬化性樹脂を硬化させてベース板を形成するとともに、前記上下導通部形成用ペーストを硬化させて上下導通部を形成し、且つ、前記ベース板上に前記半導体構成体を、前記上下導通部の前記開口部の上方に形成された部分を前記再配線の接続パッド部に接続させた状態で、固着する工程と、少なくとも前記半導体構成体の周囲における前記ベース板上に絶縁層を形成する工程と、前記半導体構成体間において前記絶縁層および前記ベース板を切断して、前記半導体構成体が少なくとも１つ含まれる半導体装置を複数個得る工程と、を含むことを特徴とするものである。 In order to achieve the above object, the semiconductor device manufacturing method of the present invention includes a step of forming an opening for vertical conduction in a base plate forming sheet made of an insulating material containing at least a semi-cured thermosetting resin, Filling the upper and lower conductive portion forming paste made of a conductive paste into the opening of the base plate forming sheet, and forming the semiconductor substrate and the semiconductor on the base plate forming sheet including the vertical conductive portion forming paste. A step of arranging a plurality of semiconductor structures having a plurality of external connection electrodes provided on one surface of the substrate so as to be spaced apart from each other; and curing the thermosetting resin in the base plate forming sheet to form a base plate Forming the vertical conduction part by curing the vertical conduction part forming paste, and forming the semiconductor structure on the base plate and the external connection electrode on the top. The step of fixing in a state where the conductive portion is bitten, the step of forming an insulating layer on the base plate around at least the semiconductor structure, and the insulating layer and the base plate are cut between the semiconductor structures And a step of obtaining a plurality of semiconductor devices including at least one semiconductor structure.
The present invention also includes a step of forming an opening for vertical conduction in a base plate forming sheet made of an insulating material containing at least a semi-cured thermosetting resin, and in the opening of the base plate forming sheet and the A step of forming an upper conductive portion forming paste made of an electrically conductive paste, and a plurality of semiconductor substrates and a plurality of semiconductor substrate provided on one surface of the semiconductor substrate on the base plate forming sheet including the vertical conductive portion forming paste A plurality of semiconductor structures having rewirings are disposed apart from each other, a thermosetting resin in the base plate forming sheet is cured to form a base plate, and the upper and lower conductive portions are formed. The paste is cured to form a vertical conduction part, the semiconductor structure is connected to the base plate, the connection pad part of the rewiring is connected to the vertical conduction part, and The step of fixing the rewiring embedded in the base plate, the step of forming an insulating layer on the base plate at least around the semiconductor structure, the insulating layer and the gap between the semiconductor structures And cutting a base plate to obtain a plurality of semiconductor devices each including at least one semiconductor structure.
Further, the present invention provides a step of forming an opening for vertical conduction in a base plate forming sheet made of an insulating material containing at least a semi-cured thermosetting resin, and the inside of the opening of the base plate forming sheet and its A step of forming an upper conductive portion forming paste made of an electrically conductive paste on the upper side, and a plurality of semiconductor substrates provided on one surface of the semiconductor substrate on the base plate forming sheet including the upper and lower conductive portion forming paste A plurality of semiconductor constituents having an overcoat film covering other than the rewiring and the connection pad portion of the rewiring, and the thermosetting resin in the base plate forming sheet is cured. Forming the base plate, curing the vertical conduction portion forming paste to form the vertical conduction portion, and forming the semiconductor structure on the base plate, A step of fixing a portion formed above the opening of the lower conductive portion to the connection pad portion of the rewiring, and an insulating layer on the base plate at least around the semiconductor structure And a step of cutting the insulating layer and the base plate between the semiconductor structures to obtain a plurality of semiconductor devices including at least one semiconductor structure. It is.

この発明によれば、少なくとも熱硬化性樹脂を含む絶縁材料からなるベース板に設けられた開口部内に上下導通部を設けているので、ベース板に形成される上下導通用の開口部の径が小さくなっても、上下導通部を含むベース板下に下層配線を形成するための電解メッキ時に当該開口部内に気泡などが全く入り込まないようにすることができる。   According to this invention, since the vertical conduction portion is provided in the opening provided in the base plate made of an insulating material containing at least a thermosetting resin, the diameter of the vertical conduction opening formed in the base plate is Even if the size is reduced, bubbles or the like can be prevented from entering the opening at the time of electrolytic plating for forming the lower layer wiring under the base plate including the vertical conduction portion.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の断面図を示す。この半導体装置は、平面方形状のベース板１を備えている。ベース板１は、例えば、エポキシ系樹脂やポリイミド系樹脂などからなる熱硬化性樹脂中にガラス繊維やアラミド繊維などの補強材を混入したものからなっている。この場合、ベース板１の所定の複数箇所には上下導通用の第１、第２の開口部２、３が設けられ、第１、第２の開口部２、３内には未硬化状態において銅ペーストなどの導電性ペーストを硬化して形成された第１、第２の上下導通部４、５が設けられている。 (First embodiment)
FIG. 1 is a sectional view of a semiconductor device as a first embodiment of the present invention. This semiconductor device includes a base plate 1 having a planar square shape. The base plate 1 is formed by mixing a reinforcing material such as glass fiber or aramid fiber in a thermosetting resin made of, for example, an epoxy resin or a polyimide resin. In this case, first and second openings 2 and 3 for vertical conduction are provided in a plurality of predetermined locations on the base plate 1, and the first and second openings 2 and 3 are in an uncured state. First and second vertical conduction parts 4 and 5 formed by curing a conductive paste such as a copper paste are provided.

ベース板１の上面の所定の箇所には、ベース板１のサイズよりもある程度小さいサイズの平面方形状の半導体構成体６がフェイスダウンとされた状態で直接固着（搭載）されている。半導体構成体６はシリコン基板（半導体基板）７を備えている。シリコン基板７の下面には所定の機能の集積回路（図示せず）が設けられ、下面周辺部にはアルミニウム系金属などからなる複数の接続パッド８が集積回路に接続されて設けられている。接続パッド８の中央部を除くシリコン基板７の下面には酸化シリコンなどからなる絶縁膜９が設けられ、接続パッド８の中央部は絶縁膜９に設けられた開口部１０を介して露出されている。   A planar rectangular semiconductor structure 6 having a size somewhat smaller than the size of the base plate 1 is directly fixed (mounted) at a predetermined position on the upper surface of the base plate 1 in a face-down state. The semiconductor structure 6 includes a silicon substrate (semiconductor substrate) 7. An integrated circuit (not shown) having a predetermined function is provided on the lower surface of the silicon substrate 7, and a plurality of connection pads 8 made of an aluminum-based metal or the like are connected to the integrated circuit on the periphery of the lower surface. An insulating film 9 made of silicon oxide or the like is provided on the lower surface of the silicon substrate 7 excluding the central portion of the connection pad 8. The central portion of the connection pad 8 is exposed through an opening 10 provided in the insulating film 9. Yes.

絶縁膜９の下面にはエポキシ系樹脂やポリイミド系樹脂などからなる保護膜１１が設けられている。この場合、絶縁膜９の開口部１０に対応する部分における保護膜１１には開口部１２が設けられている。保護膜１１の下面には銅などからなる下地金属層１３が設けられている。下地金属層１３の下面全体には銅からなる配線（再配線）１４が設けられている。下地金属層１３を含む配線１４の一端部は、両開口部１０、１２を介して接続パッド８に接続されている。配線１４の接続パッド部下面には銅からなる柱状電極（外部接続用電極）１５が設けられている。   A protective film 11 made of an epoxy resin or a polyimide resin is provided on the lower surface of the insulating film 9. In this case, an opening 12 is provided in the protective film 11 in a portion corresponding to the opening 10 of the insulating film 9. A base metal layer 13 made of copper or the like is provided on the lower surface of the protective film 11. A wiring (rewiring) 14 made of copper is provided on the entire lower surface of the base metal layer 13. One end of the wiring 14 including the base metal layer 13 is connected to the connection pad 8 through both openings 10 and 12. A columnar electrode (external connection electrode) 15 made of copper is provided on the lower surface of the connection pad portion of the wiring 14.

ここで、第１の上下導通部４は半導体構成体６搭載領域に配置され、第２の上下導通部５は半導体構成体６搭載領域以外の領域に配置されている。また、第１の上下導通部４（第１の開口部２）の径は柱状電極１５の径よりもある程度大きくなっている。そして、半導体構成体６は、柱状電極１５のすべてが第１の上下導通部４の上面ほぼ中央部に食い込まされ、下地金属層１３を含む配線１４のすべてがベース板１の上面に埋め込まれ、保護膜１１の下面がベース板１の上面に直接固着された状態で、ベース板１上に搭載されている。   Here, the first vertical conduction part 4 is arranged in the semiconductor structure 6 mounting area, and the second vertical conduction part 5 is arranged in an area other than the semiconductor structure 6 mounting area. In addition, the diameter of the first vertical conduction part 4 (first opening 2) is somewhat larger than the diameter of the columnar electrode 15. In the semiconductor structure 6, all of the columnar electrodes 15 are bitten into substantially the center of the upper surface of the first vertical conduction part 4, and all of the wirings 14 including the base metal layer 13 are embedded in the upper surface of the base plate 1, The protective film 11 is mounted on the base plate 1 in a state where the lower surface of the protective film 11 is directly fixed to the upper surface of the base plate 1.

半導体構成体６の周囲におけるベース板１の上面にはエポキシ系樹脂やポリイミド系樹脂などからなる絶縁層２１がその上面が半導体構成体６の上面とほぼほぼ面一となるように設けられている。ベース板１の第２の上下導通部５に対応する部分における絶縁層２１には上下導通用の開口部２２が設けられ、開口部２２内には未硬化状態において銅ペーストなどの導電性ペーストを硬化して形成された上下導通部２３が第２の上下導通部５の上面に接続されて設けられている。この場合、上部導通部２３（開口部２２）の径は第２の上下導通部５（第２の開口部３）の径よりもやや小さくなっている。   An insulating layer 21 made of epoxy resin or polyimide resin is provided on the upper surface of the base plate 1 around the semiconductor structure 6 so that the upper surface is substantially flush with the upper surface of the semiconductor structure 6. . The insulating layer 21 in the portion corresponding to the second vertical conduction portion 5 of the base plate 1 is provided with an opening portion 22 for vertical conduction, and a conductive paste such as a copper paste is uncured in the opening portion 22. A vertical conduction part 23 formed by curing is provided connected to the upper surface of the second vertical conduction part 5. In this case, the diameter of the upper conduction part 23 (opening 22) is slightly smaller than the diameter of the second vertical conduction part 5 (second opening 3).

上下導通部２３を含む絶縁層２１の上面には銅などからなる第１の上層下地金属層２４が設けられている。第１の上層下地金属層２４の上面全体には銅からなる第１の上層配線２５が設けられている。第１の上層下地金属層２４を含む第１の上層配線２５の一端部は上下導通部２３の上面に接続されている。   A first upper base metal layer 24 made of copper or the like is provided on the upper surface of the insulating layer 21 including the vertical conduction portion 23. A first upper wiring 25 made of copper is provided on the entire upper surface of the first upper base metal layer 24. One end portion of the first upper layer wiring 25 including the first upper base metal layer 24 is connected to the upper surface of the vertical conduction portion 23.

半導体構成体６の上面および第１の上層配線２５を含む絶縁層２１の上面には、ベース板１と同様の材料からなる上層絶縁膜２６が設けられている。第１の上層配線２５の接続パッド部上面ほぼ中央部に対応する部分における上層絶縁膜２６には上下導通用の開口部２７が設けられ、開口部２７内には未硬化状態において銅ペーストなどの導電性ペーストを硬化して形成された上下導通部２８が第１の上層配線２５の接続パッド部上面ほぼ中央部に接続されて設けられている。   An upper insulating film 26 made of the same material as that of the base plate 1 is provided on the upper surface of the semiconductor structure 6 and the upper surface of the insulating layer 21 including the first upper wiring 25. An opening 27 for vertical conduction is provided in the upper insulating film 26 in a portion corresponding to the substantially central portion of the upper surface of the connection pad portion of the first upper wiring 25, and copper paste or the like is formed in the opening 27 in an uncured state. A vertical conduction portion 28 formed by curing the conductive paste is provided so as to be connected to a substantially central portion of the upper surface of the connection pad portion of the first upper layer wiring 25.

上下導通部２８を含む上層絶縁膜２６の上面には銅などからなる第２の上層下地金属層２９が設けられている。第２の上層下地金属層２９の上面全体には銅からなる第２の上層配線３０が設けられている。第２の上層下地金属層２９を含む第２の上層配線３０の一端部は上下導通部２８の上面に接続されている。   A second upper base metal layer 29 made of copper or the like is provided on the upper surface of the upper insulating film 26 including the vertical conductive portion 28. A second upper layer wiring 30 made of copper is provided on the entire upper surface of the second upper base metal layer 29. One end portion of the second upper layer wiring 30 including the second upper layer base metal layer 29 is connected to the upper surface of the vertical conduction portion 28.

第２の上層配線３０の接続パッド部上面には別の半導体構成体３１の柱状電極１５下に設けられた半田ボール３３が接合されている。別の半導体構成体３１は、その基本的な構成が半導体構成体６と同じであるが、配線１４を含む保護膜１４の下面にエポキシ系樹脂やポリイミド系樹脂などからなる封止膜３２がその下面が柱状電極１５の下面と面一となるように設けられている点で異なり、一般的にはＣＳＰと呼ばれるものである。   A solder ball 33 provided under the columnar electrode 15 of another semiconductor structure 31 is joined to the upper surface of the connection pad portion of the second upper layer wiring 30. Another semiconductor structure 31 has the same basic structure as the semiconductor structure 6, but a sealing film 32 made of epoxy resin, polyimide resin, or the like is formed on the lower surface of the protective film 14 including the wiring 14. This is different in that the lower surface is provided so as to be flush with the lower surface of the columnar electrode 15, and is generally called CSP.

第１、第２の上下導通部４、５を含むベース板１の下面には銅などからなる第１の下層下地金属層４１が設けられている。第１の下層下地金属層４１の下面全体には銅からなる第１の下層配線４２が設けられている。第１の下層下地金属層４１を含む第１の下層配線４２の一端部は第１、第２の上下導通部４、５の下面に接続されている。   A first lower base metal layer 41 made of copper or the like is provided on the lower surface of the base plate 1 including the first and second vertical conduction portions 4 and 5. A first lower layer wiring 42 made of copper is provided on the entire lower surface of the first lower layer underlying metal layer 41. One end portion of the first lower layer wiring 42 including the first lower layer metal layer 41 is connected to the lower surfaces of the first and second vertical conduction portions 4 and 5.

第１の下層配線４２を含むベース板１の下面には、ベース板１と同様の材料からなる下層絶縁膜４３が設けられている。第１の下層配線４２の接続パッド部に対応する部分における下層絶縁膜４３には上下導通用の開口部４４が設けられ、開口部４４内には未硬化状態において銅ペーストなどの導電性ペーストを硬化して形成された上下導通部４５が第１の下層配線４２の接続パッド部下面に接続されて設けられている。   A lower layer insulating film 43 made of the same material as that of the base plate 1 is provided on the lower surface of the base plate 1 including the first lower layer wiring 42. The lower insulating film 43 in the portion corresponding to the connection pad portion of the first lower layer wiring 42 is provided with an opening 44 for vertical conduction, and a conductive paste such as copper paste is uncured in the opening 44. A vertical conduction portion 45 formed by curing is provided connected to the lower surface of the connection pad portion of the first lower layer wiring 42.

上下導通部４５を含む下層絶縁膜４３の下面には銅などからなる第２の下層下地金属層４６が設けられている。第２の下層下地金属層４６の下面全体には銅からなる第２の下層配線４７が設けられている。第２の下層下地金属層４６を含む第２の下層配線４７の一端部は上下導通部４５の下面に接続されている。第２の下層配線４７の接続パッド部下面には半田ボール４８が設けられている。複数の半田ボール４８は、下層絶縁膜４３下のほぼ全域にマトリクス状に配置されている。   A second lower base metal layer 46 made of copper or the like is provided on the lower surface of the lower insulating film 43 including the vertical conductive portion 45. A second lower layer wiring 47 made of copper is provided on the entire lower surface of the second lower layer base metal layer 46. One end of the second lower wiring 47 including the second lower base metal layer 46 is connected to the lower surface of the vertical conduction portion 45. A solder ball 48 is provided on the lower surface of the connection pad portion of the second lower layer wiring 47. The plurality of solder balls 48 are arranged in a matrix form almost all over the lower insulating film 43.

次に、この半導体装置の製造方法の一例について説明する。まず、図２に示すように、図１に示す完成された半導体装置を複数個形成することが可能な面積を有し、限定する意味ではないが、補強材が含有された熱硬化性樹脂からなる平面方形状のベース板形成用シート１ａを用意する。この場合、ベース板形成用シート１ａを構成するエポキシ系樹脂などからなる熱硬化性樹脂は、半硬化状態となっている。次に、ＣＯ2レーザなどのレーザビームを照射するレーザ加工により、ベース板形成用シート１ａの所定の複数箇所に第１、第２の開口部２、３を形成する。 Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 2, it has an area where a plurality of completed semiconductor devices shown in FIG. 1 can be formed, and is not limited, but from a thermosetting resin containing a reinforcing material. A planar rectangular base plate forming sheet 1a is prepared. In this case, the thermosetting resin made of an epoxy resin or the like constituting the base plate forming sheet 1a is in a semi-cured state. Next, the first and second openings 2 and 3 are formed in a predetermined plurality of locations of the base plate forming sheet 1a by laser processing that irradiates a laser beam such as a CO 2 laser.

次に、図３に示すように、保護シート５１を用意し、この保護シート５１の上面にベース板形成用シート１ａを載置する。次に、スクリーン印刷法などにより、ベース板形成用シート１ａの第１、第２の開口部２、３内に銅ペーストなどの導電性ペーストからなる第１、第２の上下導通部形成用ペースト４ａ、５ａを充填する。   Next, as shown in FIG. 3, a protective sheet 51 is prepared, and a base plate forming sheet 1 a is placed on the upper surface of the protective sheet 51. Next, first and second upper and lower conductive portion forming pastes made of a conductive paste such as copper paste in the first and second openings 2 and 3 of the base plate forming sheet 1a by screen printing or the like. Fill 4a, 5a.

次に、図４に示すように、第１の上下導通部形成用ペースト４ａの上面ほぼ中央部に半導体構成体６の柱状電極１５の下面を位置合わせして仮圧着（仮固着）する。すなわち、加熱機構付きのボンディングツール（図示せず）を用い、半導体構成体６の柱状電極１５の下面を、予め加熱した状態で比較的低い圧力をかけながら、上下導通部形成用ペースト４ａの上面ほぼ中央部に仮圧着する。この状態では、ベース板形成用シート１ａ上に複数の半導体構成体６が相互に離間されて仮固着されている。   Next, as shown in FIG. 4, the lower surface of the columnar electrode 15 of the semiconductor structure 6 is aligned with the upper surface of the first upper and lower conductive portion forming paste 4a and is temporarily pressure-bonded (temporarily fixed). That is, using a bonding tool (not shown) with a heating mechanism, while applying a relatively low pressure to the lower surface of the columnar electrode 15 of the semiconductor structure 6 in a preheated state, the upper surface of the upper and lower conductive portion forming paste 4a. Temporarily press-bond to the center. In this state, a plurality of semiconductor constructs 6 are temporarily fixed on the base plate forming sheet 1a while being separated from each other.

次に、一対の加熱加圧板（図示せず）を用いて上下から加熱加圧する。すると、図５に示すように、まず、柱状電極１５のすべてが第１の上下導通部形成用ペースト４ａの上面ほぼ中央部に食い込み、下地金属層１３を含む配線１４のすべてが上下導通部形成用ペースト４ａを圧縮しながらベース板形成用シート１ａの上面に埋め込まれ、保護膜１１の下面がベース板形成用シート１ａの上面に圧接する状態となり、次いで、ベース板形成用シート１ａ中のエポキシ系樹脂などからなる熱硬化性樹脂が硬化し、ベース板１が形成され、且つ、第１、第２の上下導通部形成用ペースト４ａ、５ａが硬化し、第１、第２の上下導通部４、５が形成される。   Next, heat and pressure are applied from above and below using a pair of heat and pressure plates (not shown). Then, as shown in FIG. 5, first, all of the columnar electrodes 15 bite into substantially the center of the upper surface of the first vertical conductive portion forming paste 4a, and all of the wirings 14 including the base metal layer 13 form the vertical conductive portions. The paste 4a is compressed while being embedded in the upper surface of the base plate forming sheet 1a, and the lower surface of the protective film 11 is in pressure contact with the upper surface of the base plate forming sheet 1a, and then the epoxy in the base plate forming sheet 1a The thermosetting resin made of a resin or the like is cured, the base plate 1 is formed, and the first and second vertical conduction portion forming pastes 4a and 5a are cured, so that the first and second vertical conduction portions are formed. 4, 5 are formed.

これにより、半導体構成体６は、柱状電極１５のすべてが第１の上下導通部４の上面ほぼ中央部に食い込まされ、下地金属層１３を含む配線１４のすべてがベース板１の上面に埋め込まれ、保護膜１１の下面がベース板１の上面に直接固着された状態で、ベース板１上に搭載される。   As a result, in the semiconductor structure 6, all the columnar electrodes 15 are bitten into the substantially central portion of the upper surface of the first vertical conduction portion 4, and all the wirings 14 including the base metal layer 13 are embedded in the upper surface of the base plate 1. The protective film 11 is mounted on the base plate 1 in a state where the lower surface of the protective film 11 is directly fixed to the upper surface of the base plate 1.

次に、図６に示すように、半導体構成体６の周囲における第２の上下導通部５を含むベース板１の上面に、スクリーン印刷法やスピンコート法などにより、エポキシ系樹脂などからなる液状の熱硬化性樹脂を塗布し、硬化させることにより、絶縁層２１をベース板１の上面に固着するとともに半導体構成体６の側面に固着する。この場合、絶縁層２１の上面は半導体構成体６の上面とほぼ面一となるようにすることが好ましい。   Next, as shown in FIG. 6, a liquid made of an epoxy resin or the like is formed on the upper surface of the base plate 1 including the second vertical conductive portion 5 around the semiconductor structure 6 by screen printing, spin coating, or the like. The insulating layer 21 is fixed to the upper surface of the base plate 1 and fixed to the side surface of the semiconductor structure 6 by applying and curing the thermosetting resin. In this case, it is preferable that the upper surface of the insulating layer 21 is substantially flush with the upper surface of the semiconductor structure 6.

次に、図７に示すように、ＣＯ2レーザなどのレーザビームを照射するレーザ加工により、第２の上下導通部５の上面ほぼ中央部上における絶縁層２１に開口部２２を形成する。次に、絶縁層２１の開口部２２内に、スクリーン印刷法などにより、銅ペーストなどの導電性ペーストからなる上部導通部形成用ペーストを充填し、硬化させることにより、上下導通部２３を第２の上下導通部５の上面に接続させて形成する。そして、この状態では、ベース板１および絶縁層２１は硬化しているので、次に、保護シート５１を剥離する。 Next, as shown in FIG. 7, an opening 22 is formed in the insulating layer 21 on the upper surface of the second vertical conduction part 5 substantially at the center by laser processing that irradiates a laser beam such as a CO 2 laser. Next, an upper conductive portion forming paste made of a conductive paste such as a copper paste is filled in the opening 22 of the insulating layer 21 by a screen printing method or the like, and cured, whereby the vertical conductive portion 23 is made to be the second conductive portion 23. The upper and lower conductive parts 5 are connected to the upper surface. And in this state, since the base board 1 and the insulating layer 21 are hardening, the protective sheet 51 is peeled next.

次に、図８に示すように、半導体構成体６の上面および上下導通部２３を含む絶縁層２１の下面全体に第１の上層下地金属層２４を形成し、また、第１、第２の上下導通部４、５を含むベース板１の下面全体に第１の下層下地金属層４１を形成する。この場合、第１の上層下地金属層２４および第１の下層下地金属層４１は、無電解メッキにより形成された銅層のみであってもよく、またスパッタにより形成された銅層のみであってもよく、さらにスパッタにより形成されたチタンなどの薄膜層上にスパッタにより銅層を形成したものであってもよい。   Next, as shown in FIG. 8, the first upper base metal layer 24 is formed on the entire upper surface of the semiconductor structure 6 and the entire lower surface of the insulating layer 21 including the upper and lower conductive portions 23. A first lower base metal layer 41 is formed on the entire lower surface of the base plate 1 including the vertical conduction portions 4 and 5. In this case, the first upper base metal layer 24 and the first lower base metal layer 41 may be only a copper layer formed by electroless plating, or only a copper layer formed by sputtering. In addition, a copper layer may be formed by sputtering on a thin film layer such as titanium formed by sputtering.

次に、第１の上層下地金属層２４の上面に上層メッキレジスト膜５２をパターン形成し、また、第１の下層下地金属層４１の下面に下層メッキレジスト膜５３をパターン形成する。この場合、第１の上層配線２５形成領域に対応する部分における上層メッキレジスト膜５２には開口部５４が形成されている。また、第１の下層配線４２形成領域に対応する部分における下層メッキレジスト膜５３には開口部５５が形成されている。   Next, the upper plating resist film 52 is patterned on the upper surface of the first upper lower metal layer 24, and the lower plating resist film 53 is patterned on the lower surface of the first lower base metal layer 41. In this case, an opening 54 is formed in the upper plating resist film 52 in a portion corresponding to the first upper wiring 25 formation region. Further, an opening 55 is formed in the lower plating resist film 53 in a portion corresponding to the first lower wiring 42 forming region.

次に、第１の上層下地金属層２４および第１の下層下地金属層４１をメッキ電流路として銅の電解メッキを行なうことにより、上層メッキレジスト膜５２の開口部５４内の第１の上層下地金属層２４の上面に第１の上層配線２５を形成し、また、下層メッキレジスト膜５３の開口部５５内の第１の下層下地金属層４１の下面に第１の下層配線４２を形成する。   Next, by performing copper electroplating using the first upper base metal layer 24 and the first lower base metal layer 41 as a plating current path, the first upper base base in the opening 54 of the upper plating resist film 52 is performed. A first upper wiring 25 is formed on the upper surface of the metal layer 24, and a first lower wiring 42 is formed on the lower surface of the first lower base metal layer 41 in the opening 55 of the lower plating resist film 53.

この場合、ベース板１の第１、第２の開口部２、３内には硬化した第１、第２の上下導通部４、５が形成されているため、第１、第２の上下導通部４、５を含むベース板１の下面は平坦となっている。この結果、第１、第２の上下導通部４、５を含むベース板１の下面全体に形成された第１の下層下地金属層４１の下面も平坦となる。また、絶縁膜２１の開口部２２内には硬化した上下導通部２３が形成されているため、上下導通部２３を含む絶縁膜２１の上面は平坦となっている。この結果、上下導通部２３を含む絶縁膜２１の上面全体に形成された第１の上層下地金属層２４の上面も平坦となる。   In this case, since the hardened first and second vertical conduction portions 4 and 5 are formed in the first and second openings 2 and 3 of the base plate 1, the first and second vertical conduction portions are formed. The lower surface of the base plate 1 including the parts 4 and 5 is flat. As a result, the lower surface of the first lower base metal layer 41 formed on the entire lower surface of the base plate 1 including the first and second vertical conduction portions 4 and 5 is also flat. Further, since the hardened vertical conduction part 23 is formed in the opening 22 of the insulating film 21, the upper surface of the insulating film 21 including the vertical conduction part 23 is flat. As a result, the upper surface of the first upper base metal layer 24 formed on the entire upper surface of the insulating film 21 including the vertical conduction portion 23 is also flat.

したがって、ベース板１の第１、第２の開口部２、３の径が小さくなっても、下層メッキレジスト膜５３の開口部５５内の第１の下層下地金属層４１の下面に第１の下層配線４２を電解メッキにより形成するとき、ベース板１の第１、第２の開口部２、３内に気泡などが全く入り込まないようにすることができる。また、絶縁層２１の開口部２２の径が小さくなっても、上層メッキレジスト膜５２の開口部５４内の第１の上層下地金属層２４の上面に第１の上層配線２５を電解メッキにより形成するとき、絶縁層２１の開口部２２内に気泡などが全く入り込まないようにすることができる。   Therefore, even if the diameters of the first and second openings 2 and 3 of the base plate 1 are reduced, the first lower base metal layer 41 in the opening 55 of the lower plating resist film 53 has a first surface on the lower surface. When the lower layer wiring 42 is formed by electrolytic plating, it is possible to prevent bubbles or the like from entering the first and second openings 2 and 3 of the base plate 1 at all. Further, even if the diameter of the opening 22 of the insulating layer 21 is reduced, the first upper wiring 25 is formed on the upper surface of the first upper base metal layer 24 in the opening 54 of the upper plating resist film 52 by electrolytic plating. When doing so, bubbles or the like can be prevented from entering the opening 22 of the insulating layer 21 at all.

次に、両メッキレジスト膜５２、５３を剥離し、次いで、第１の上層配線２５および第１の下層配線４２をマスクとして第１の上層下地金属層２４および第１の下層下地金属層４１の不要な部分をエッチングして除去すると、図９に示すように、第１の上層配線２５下にのみ第１の上層下地金属層２４が残存され、また、第１の下層配線４２上にのみ第１の下層下地金属層４１が残存される。この状態では、第１の上層下地金属層２４を含む第１の上層配線２５の一端部は上下導通部２３の上面に接続されている。また、第１の下層下地金属層４１を含む第１の下層配線４２の一端部は第１、第２の上下導通部４、５の下面に接続されている。   Next, the plating resist films 52 and 53 are peeled off, and then the first upper layer metal layer 24 and the first lower layer metal layer 41 are formed using the first upper layer wiring 25 and the first lower layer wiring 42 as a mask. When unnecessary portions are removed by etching, as shown in FIG. 9, the first upper base metal layer 24 remains only under the first upper layer wiring 25, and only on the first lower layer wiring 42. 1 lower base metal layer 41 remains. In this state, one end portion of the first upper layer wiring 25 including the first upper base metal layer 24 is connected to the upper surface of the vertical conduction portion 23. One end portion of the first lower layer wiring 42 including the first lower layer base metal layer 41 is connected to the lower surfaces of the first and second vertical conduction portions 4 and 5.

次に、図１０に示すように、補強材が含有された熱硬化性樹脂からなる平面方形状の上層絶縁膜形成用シート２６ａおよび下層絶縁膜形成用シート４３ａを用意する。この場合、両シート２６ａ、４３ａを構成するエポキシ系樹脂などからなる熱硬化性樹脂は、半硬化状態となっている。また、両シート２６ａ、４３ａの所定の複数箇所にレーザ加工により形成された開口部２７、４４内には、スクリーン印刷法などにより、銅ペーストなどの導電性ペーストからなる上下導通部形成用ペースト２８ａ、４５ａが充填されている。   Next, as shown in FIG. 10, a planar rectangular upper layer insulating film forming sheet 26a and a lower layer insulating film forming sheet 43a made of a thermosetting resin containing a reinforcing material are prepared. In this case, the thermosetting resin made of an epoxy resin or the like constituting both sheets 26a and 43a is in a semi-cured state. In addition, in the openings 27 and 44 formed by laser processing in a predetermined plurality of positions of both sheets 26a and 43a, the upper and lower conductive portion forming paste 28a made of a conductive paste such as a copper paste is formed by screen printing or the like. , 45a.

そして、下層絶縁膜形成用シート４３ａの上面にベース板１下に形成された第１の下層配線４２を位置合わせして配置し、絶縁層２１上に形成された第１の上層配線２５の上面に上層絶縁膜形成用シート２６ａを位置合わせして配置する。この状態では、第１の下層配線４２の接続パッド部下面ほぼ中央部は上下導通部形成用ペースト４５ａの上面に配置されている。また、上下導通部形成用ペースト２８ａの下面は第１の上層配線２５の接続パッド部上面ほぼ中央部に配置されている。   Then, the first lower layer wiring 42 formed under the base plate 1 is positioned and arranged on the upper surface of the lower insulating film forming sheet 43 a, and the upper surface of the first upper layer wiring 25 formed on the insulating layer 21. The upper insulating film forming sheet 26a is aligned and disposed. In this state, a substantially central portion of the lower surface of the connection pad portion of the first lower layer wiring 42 is disposed on the upper surface of the upper and lower conductive portion forming paste 45a. In addition, the lower surface of the upper and lower conductive portion forming paste 28 a is disposed substantially at the center of the upper surface of the connection pad portion of the first upper layer wiring 25.

次に、一対の加熱加圧板（図示せず）を用いて上下から加熱加圧する。すると、図１１に示すように、上層絶縁膜形成用シート２６ａ中のエポキシ系樹脂などからなる熱硬化性樹脂が硬化し、第１の上層配線２５を含む絶縁層２１の上面に上層絶縁膜２６が形成され、且つ、上下導通部形成用ペースト２８ａが硬化し、上下導通部２８が形成される。この状態では、上下導通部２８の下面は第１の上層配線２５の接続パッド部上面ほぼ中央部に接続されている。   Next, heat and pressure are applied from above and below using a pair of heat and pressure plates (not shown). Then, as shown in FIG. 11, the thermosetting resin made of epoxy resin or the like in the upper layer insulating film forming sheet 26 a is cured, and the upper layer insulating film 26 is formed on the upper surface of the insulating layer 21 including the first upper layer wiring 25. And the vertical conduction portion forming paste 28a is cured to form the vertical conduction portion 28. In this state, the lower surface of the vertical conductive portion 28 is connected to the substantially central portion of the upper surface of the connection pad portion of the first upper layer wiring 25.

また、下層絶縁膜形成用シート４３ａ中のエポキシ系樹脂などからなる熱硬化性樹脂が硬化し、第１の下層配線４２を含むベース板１の下面に下層絶縁膜４３が形成され、且つ、上下導通部形成用ペースト４５ａが硬化し、上下導通部４５が形成される。この状態では、上下導通部４５の上面は第１の下層配線４２の接続パッド部下面ほぼ中央部に接続されている。   In addition, the thermosetting resin made of epoxy resin or the like in the lower insulating film forming sheet 43a is cured, and the lower insulating film 43 is formed on the lower surface of the base plate 1 including the first lower wiring 42, and the upper and lower The conductive portion forming paste 45a is cured, and the vertical conductive portion 45 is formed. In this state, the upper surface of the vertical conductive portion 45 is connected to the substantially lower central portion of the lower surface of the connection pad portion of the first lower layer wiring 42.

次に、図１２に示すように、銅の無電解メッキなどにより、上下導通部２８を含む上層絶縁膜２６の下面全体に第２の上層下地金属層２９を形成し、また、上下導通部４５を含む下層絶縁膜４３の下面全体に第２の下層下地金属層４６を形成する。次に、第２の上層下地金属層２９の上面に上層メッキレジスト膜５６をパターン形成し、また、第２の下層下地金属層４６の下面に下層メッキレジスト膜５７をパターン形成する。この場合、第２の上層配線３０形成領域に対応する部分における上層メッキレジスト膜５６には開口部５８が形成されている。また、第２の下層配線４７形成領域に対応する部分における下層メッキレジスト膜５７には開口部５９が形成されている。   Next, as shown in FIG. 12, a second upper base metal layer 29 is formed on the entire lower surface of the upper insulating film 26 including the vertical conductive portion 28 by copper electroless plating or the like, and the vertical conductive portion 45 is formed. A second lower base metal layer 46 is formed on the entire lower surface of the lower insulating film 43 including Next, the upper plating resist film 56 is patterned on the upper surface of the second upper lower metal layer 29, and the lower plating resist film 57 is patterned on the lower surface of the second lower metal layer 46. In this case, an opening 58 is formed in the upper plating resist film 56 in a portion corresponding to the second upper wiring 30 formation region. An opening 59 is formed in the lower plating resist film 57 in a portion corresponding to the second lower wiring 47 formation region.

次に、第２の上層下地金属層２９および第２の下層下地金属層４６をメッキ電流路として銅の電解メッキを行なうことにより、上層メッキレジスト膜５６の開口部５８内の第２の上層下地金属層２９の上面に第２の上層配線３０を形成し、また、下層メッキレジスト膜５７の開口部５９内の第２の下層下地金属層４６の下面に第２の下層配線４７を形成する。   Next, copper is electroplated using the second upper base metal layer 29 and the second lower base metal layer 46 as a plating current path, so that the second upper base base in the opening 58 of the upper plating resist film 56 is obtained. A second upper layer wiring 30 is formed on the upper surface of the metal layer 29, and a second lower layer wiring 47 is formed on the lower surface of the second lower layer base metal layer 46 in the opening 59 of the lower layer plating resist film 57.

この場合も、上層絶縁膜２６の開口部２７内には硬化した上下導通部２８が形成されているため、上下導通部２８を含む上層絶縁膜２６の上面は平坦となっている。この結果、上下導通部２８を含む上層絶縁膜２６の上面全体に形成された第２の上層下地金属層２９の上面も平坦となる。また、下層絶縁膜４３の開口部４４内には硬化した上下導通部４５が形成されているため、上下導通部４５を含む下層絶縁膜４３の下面は平坦となっている。この結果、上下導通部４５を含む下層絶縁膜４３の下面全体に形成された第２の下層下地金属層４６の下面も平坦となる。   Also in this case, since the hardened vertical conduction part 28 is formed in the opening 27 of the upper insulation film 26, the upper surface of the upper insulation film 26 including the vertical conduction part 28 is flat. As a result, the upper surface of the second upper base metal layer 29 formed over the entire upper surface of the upper insulating film 26 including the vertical conductive portion 28 is also flat. Further, since the hardened vertical conduction part 45 is formed in the opening 44 of the lower insulating film 43, the lower surface of the lower insulating film 43 including the vertical conduction part 45 is flat. As a result, the lower surface of the second lower base metal layer 46 formed on the entire lower surface of the lower insulating film 43 including the vertical conduction portion 45 is also flat.

したがって、上層絶縁膜２６の開口部２７の径が小さくなっても、上層メッキレジスト膜５６の開口部５８内の第２の上層下地金属層２９の上面に第２の上層配線３０を電解メッキにより形成するとき、上層絶縁膜２６の開口部２７内に気泡などが全く入り込まないようにすることができる。また、下層絶縁膜４３の開口部４４の径が小さくなっても、下層メッキレジスト膜５７の開口部５９内の第２の下層下地金属層４６の下面に第２の下層配線４７を電解メッキにより形成するとき、下層絶縁膜４３の開口部４４内に気泡などが全く入り込まないようにすることができる。   Therefore, even if the diameter of the opening 27 of the upper insulating film 26 is reduced, the second upper wiring 30 is electrolytically plated on the upper surface of the second upper base metal layer 29 in the opening 58 of the upper plating resist film 56. When formed, bubbles or the like can be prevented from entering the opening 27 of the upper insulating film 26 at all. Even when the diameter of the opening 44 of the lower insulating film 43 is reduced, the second lower layer wiring 47 is electrolytically plated on the lower surface of the second lower base metal layer 46 in the opening 59 of the lower plating resist film 57. When formed, bubbles or the like can be prevented from entering the opening 44 of the lower insulating film 43 at all.

次に、両メッキレジスト膜５６、５８を剥離し、次いで、第２の上層配線３０および第２の下層配線４７をマスクとして第２の上層下地金属層２９および第２の下層下地金属層４６の不要な部分をエッチングして除去すると、図１３に示すように、第２の上層配線３０下にのみ第２の上層下地金属層２９が残存され、また、第２の下層配線４７上にのみ第２の下層下地金属層４６が残存される。この状態では、第２の上層下地金属層２９を含む第２の上層配線３０の一端部は上下導通部２８の上面に接続されている。また、第２の下層下地金属層４６を含む第２の下層配線４７の一端部は上下導通部４５の下面に接続されている。   Next, the plating resist films 56 and 58 are peeled off, and then the second upper layer metal layer 29 and the second lower layer metal layer 46 are formed using the second upper layer wiring 30 and the second lower layer wiring 47 as a mask. When unnecessary portions are removed by etching, as shown in FIG. 13, the second upper layer underlying metal layer 29 remains only under the second upper layer wiring 30 and only on the second lower layer wiring 47. The second lower base metal layer 46 remains. In this state, one end portion of the second upper layer wiring 30 including the second upper base metal layer 29 is connected to the upper surface of the vertical conduction portion 28. One end portion of the second lower layer wiring 47 including the second lower layer base metal layer 46 is connected to the lower surface of the vertical conduction portion 45.

次に、図１４に示すように、第２の下層配線４７の接続パッド部下面に半田ボール４８を形成する。次に、第２の上層配線３０の接続パッド部上面に、別途、製造しておいた半導体構成体３１の柱状電極１５下の半田ボール３３を接合する。次に、互いに隣接する半導体構成体６間において、上層絶縁膜２６、絶縁層２１、ベース板１および下層絶縁膜４３を切断すると、図１に示す半導体装置が複数個得られる。なお、半導体構成体３１を搭載する前に、上層絶縁膜２６、絶縁層２１、ベース板１および下層絶縁膜４３を切断し、この後、半導体構成体３１を搭載するようにしてもよい。   Next, as shown in FIG. 14, a solder ball 48 is formed on the lower surface of the connection pad portion of the second lower layer wiring 47. Next, a solder ball 33 under the columnar electrode 15 of the semiconductor structure 31 that has been separately manufactured is joined to the upper surface of the connection pad portion of the second upper layer wiring 30. Next, when the upper insulating film 26, the insulating layer 21, the base plate 1 and the lower insulating film 43 are cut between adjacent semiconductor structures 6, a plurality of semiconductor devices shown in FIG. 1 are obtained. Note that the upper insulating film 26, the insulating layer 21, the base plate 1, and the lower insulating film 43 may be cut before mounting the semiconductor structure 31, and then the semiconductor structure 31 may be mounted.

ところで、上記従来の半導体装置では、上面側に複数の柱状電極を有する半導体構成体をベース板の上面に接着層を介して接着し、半導体構成体の周囲におけるベース板の上面に絶縁層を設け、半導体構成体および絶縁層の上面に上層絶縁膜を設け、上層絶縁膜の上面に上層配線を上層絶縁膜の開口部を介して半導体構成体の柱状電極に接続させて設け、上層配線の接続パッド部を除く部分をオーバーコート膜で覆い、上層配線の接続パッド部上に半田ボールを設けているので、別の半導体構成体を搭載することができる構造とはなっていない。   By the way, in the conventional semiconductor device, a semiconductor structure having a plurality of columnar electrodes on the upper surface side is bonded to the upper surface of the base plate via an adhesive layer, and an insulating layer is provided on the upper surface of the base plate around the semiconductor structure. An upper layer insulating film is provided on the upper surface of the semiconductor structure and the insulating layer, and an upper layer wiring is provided on the upper surface of the upper layer insulating film by being connected to the columnar electrode of the semiconductor structure through the opening of the upper layer insulating film. Since the portion excluding the pad portion is covered with the overcoat film and the solder ball is provided on the connection pad portion of the upper wiring, the structure is not capable of mounting another semiconductor structure.

これに対し、図１に示す半導体装置では、上層絶縁膜２６の上面に第２の上層配線３０を設け、この第２の上層配線３０を上下導通部２７、第１の上層配線２５および上下導通部２３、５を介して第１の下層配線４２に電気的に接続しているので、第２の上層配線３０上に別の半導体構成体３１を搭載することができる。   On the other hand, in the semiconductor device shown in FIG. 1, the second upper layer wiring 30 is provided on the upper surface of the upper layer insulating film 26, and the second upper layer wiring 30 is connected to the vertical conduction portion 27, the first upper layer wiring 25, and the vertical conduction. Since it is electrically connected to the first lower layer wiring 42 via the parts 23, 5, another semiconductor structure 31 can be mounted on the second upper layer wiring 30.

（第２実施形態）
図１５はこの発明の第２実施形態としての半導体装置の断面図を示す。この半導体装置において、図１に示す半導体装置と異なる点は、半導体構成体６を、配線１４の接続パッド部下面に柱状電極１５が設けられていない構造とした点である。この場合、下地金属層１３を含む配線（再配線）１４のすべては、その接続パッド部下面が第１の上下導通部４の上面に接続された状態で、ベース板１の上面に埋め込まれ、保護膜１１の下面はベース板１の上面に直接固着されている。また、第２の上下導通部５の上部はベース板１の上面から突出され、絶縁層２１内に配置されている。 (Second Embodiment)
FIG. 15 is a sectional view of a semiconductor device as a second embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 1 in that the semiconductor structure 6 has a structure in which the columnar electrode 15 is not provided on the lower surface of the connection pad portion of the wiring 14. In this case, all of the wiring (rewiring) 14 including the base metal layer 13 is embedded in the upper surface of the base plate 1 with the lower surface of the connection pad portion connected to the upper surface of the first vertical conduction portion 4. The lower surface of the protective film 11 is directly fixed to the upper surface of the base plate 1. The upper part of the second vertical conduction part 5 protrudes from the upper surface of the base plate 1 and is disposed in the insulating layer 21.

次に、この半導体装置の製造方法の一例について説明する。まず、図１６に示すように、図１５に示す完成された半導体装置を複数個形成することが可能な面積を有し、限定する意味ではないが、補強材が含有された熱硬化性樹脂からなる平面方形状のベース板形成用シート１ａを用意する。この場合も、ベース板形成用シート１ａを構成するエポキシ系樹脂などからなる熱硬化性樹脂は、半硬化状態となっている。次に、ベース板形成用シート１ａの上面に、後述する突出部を形成するための突出部形成用シート６１を貼り付ける（積層する）。   Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 16, it has an area where a plurality of completed semiconductor devices shown in FIG. 15 can be formed, and is not limited, but from a thermosetting resin containing a reinforcing material. A planar rectangular base plate forming sheet 1a is prepared. Also in this case, the thermosetting resin made of an epoxy resin or the like constituting the base plate forming sheet 1a is in a semi-cured state. Next, the protrusion part formation sheet 61 for forming the protrusion part mentioned later is affixed on the upper surface of the sheet | seat 1a for base board formation (lamination | stacking).

次に、図１７に示すように、ＣＯ2レーザなどのレーザビームを照射するレーザ加工により、ベース板形成用シート１ａおよび突出部形成用シート６１の所定の複数箇所に第１、第２の開口部２、３を形成する。次に、図１８に示すように、保護シート６２を用意し、この保護シート６２の上面にベース板形成用シート１ａを載置する。次に、スクリーン印刷法などにより、ベース板形成用シート１ａおよび突出部形成用シート６１の第１、第２の開口部２、３内に銅ペーストなどの導電性ペーストからなる第１、第２の上下導通部形成用ペースト４ａ、５ａを充填する。次に、突出部形成用シート６１を剥離すると、図１９に示すように、第１、第２の上下導通部形成用ペースト４ａ、５ａの上部がベース板形成用シート１ａの上面から突出部形成用シート６１の厚さに相当する分だけ突出された状態となる。 Next, as shown in FIG. 17, first and second openings are formed at predetermined locations on the base plate forming sheet 1 a and the protrusion forming sheet 61 by laser processing that irradiates a laser beam such as a CO 2 laser. Parts 2 and 3 are formed. Next, as shown in FIG. 18, a protective sheet 62 is prepared, and the base plate forming sheet 1 a is placed on the upper surface of the protective sheet 62. Next, the first and second made of a conductive paste such as copper paste in the first and second openings 2 and 3 of the base plate forming sheet 1a and the protrusion forming sheet 61 by screen printing or the like. The upper and lower conductive portion forming pastes 4a and 5a are filled. Next, when the protruding portion forming sheet 61 is peeled off, as shown in FIG. 19, the upper portions of the first and second upper and lower conductive portion forming pastes 4a and 5a form protruding portions from the upper surface of the base plate forming sheet 1a. It will be in the state protruded by the part corresponding to the thickness of the sheet | seat 61 for use.

次に、図２０に示すように、ベース板形成用シート１ａの上面から突出された第１の上下導通部形成用ペースト４ａの上面に半導体構成体６の配線１４の接続パッド部下面を位置合わせして仮圧着（仮固着）する。すなわち、加熱機構付きのボンディングツール（図示せず）を用い、半導体構成体６の配線１４の接続パッド部下面を、予め加熱した状態で比較的低い圧力をかけながら、第１の上下導通部形成用ペースト４ａの上面に仮圧着する。この状態では、ベース板形成用シート１ａ上に複数の半導体構成体６が相互に離間されて仮固着されている。   Next, as shown in FIG. 20, the lower surface of the connection pad portion of the wiring 14 of the semiconductor structure 6 is aligned with the upper surface of the first vertical conductive portion forming paste 4a protruding from the upper surface of the base plate forming sheet 1a. And temporarily press-bonded (temporarily fixed). That is, using a bonding tool (not shown) with a heating mechanism, the first lower conductive portion is formed while applying a relatively low pressure to the lower surface of the connection pad portion of the wiring 14 of the semiconductor structure 6 in a preheated state. Temporary pressure bonding is performed on the upper surface of the paste 4a. In this state, a plurality of semiconductor constructs 6 are temporarily fixed on the base plate forming sheet 1a while being separated from each other.

次に、一対の加熱加圧板（図示せず）を用いて上下から加熱加圧する。すると、図２１に示すように、まず、半導体構成体６の配線１４の接続パッド部下面で第１の上下導通部形成用ペースト４ａのベース板形成用シート１ａの上面から突出された突出部をベース板形成用シート１ａの第１の開口部２内に完全に押し込み、次いで、下地金属層１３を含む配線１４のすべてが上下導通部形成用ペースト４ａを圧縮しながらベース板形成用シート１ａの上面に埋め込まれ、保護膜１１の下面がベース板形成用シート１ａの上面に圧接する状態となり、次いで、ベース板形成用シート１ａ中のエポキシ系樹脂などからなる熱硬化性樹脂が硬化し、ベース板１が形成され、且つ、第１、第２の上下導通部形成用ペースト４ａ、５ａが硬化し、第１、第２の上下導通部４、５が形成される。この場合、第２の上下導通部５は加熱されるだけで加圧されないので、その上部はベース板１の上面から突出されたままである。   Next, heat and pressure are applied from above and below using a pair of heat and pressure plates (not shown). Then, as shown in FIG. 21, first, a protruding portion protruding from the upper surface of the base plate forming sheet 1 a of the first vertical conduction portion forming paste 4 a on the lower surface of the connection pad portion of the wiring 14 of the semiconductor structure 6 is formed. The base plate forming sheet 1a is completely pushed into the first opening 2, and then all of the wirings 14 including the base metal layer 13 compress the upper and lower conductive portion forming paste 4a while the base plate forming sheet 1a It is embedded in the upper surface, and the lower surface of the protective film 11 is in pressure contact with the upper surface of the base plate forming sheet 1a. Then, the thermosetting resin made of epoxy resin or the like in the base plate forming sheet 1a is cured, and the base The plate 1 is formed, and the first and second vertical conduction part forming pastes 4a and 5a are cured to form the first and second vertical conduction parts 4 and 5. In this case, the second vertical conduction part 5 is only heated and is not pressurized, so that the upper part thereof is projected from the upper surface of the base plate 1.

これにより、半導体構成体６は、ベース板１の上面の所定の箇所にフェイスダウンとされた状態で直接固着される。すなわち、下地金属層１３を含む配線１４のすべては、その接続パッド部下面が第１の上下導通部４の上面に接続された状態で、ベース板１の上面に埋め込まれ、保護膜１１の下面はベース板１の上面に直接固着される。ここで、図２０に示す状態において、第１の上下導通部形成用ペースト４ａの上部をベース板形成用シート１ａの上面から突出させているのは、下面全体が平坦な配線１４の接続パッド部下面を蛇１の上下導通部４の上面に確実に且つ強固に固着させるためである。   As a result, the semiconductor structure 6 is directly fixed to a predetermined location on the upper surface of the base plate 1 in a face-down state. That is, all of the wirings 14 including the base metal layer 13 are buried in the upper surface of the base plate 1 with the lower surface of the connection pad portion connected to the upper surface of the first vertical conduction portion 4, and the lower surface of the protective film 11. Is directly fixed to the upper surface of the base plate 1. Here, in the state shown in FIG. 20, the upper portion of the first vertical conductive portion forming paste 4a is protruded from the upper surface of the base plate forming sheet 1a because the entire lower surface of the connection pad portion of the wiring 14 is flat. This is because the lower surface is securely and firmly fixed to the upper surface of the vertical conduction portion 4 of the snake 1.

次に、図２２に示すように、半導体構成体６の周囲における第２の上下導通部５を含むベース板１の上面に、スクリーン印刷法やスピンコート法などにより、エポキシ系樹脂などからなる液状の熱硬化性樹脂を塗布し、硬化させることにより、絶縁層２１をその上面が半導体構成体６の上面とほぼ面一となるように形成する。   Next, as shown in FIG. 22, a liquid made of an epoxy resin or the like is formed on the upper surface of the base plate 1 including the second vertical conductive portion 5 around the semiconductor structure 6 by screen printing or spin coating. The insulating layer 21 is formed so that the upper surface thereof is substantially flush with the upper surface of the semiconductor structure 6 by applying and curing the thermosetting resin.

次に、ＣＯ2レーザなどのレーザビームを照射するレーザ加工により、第２の上下導通部５の上面ほぼ中央部上における絶縁層２１に開口部２２を形成する。次に、絶縁層２１の開口部２２内に、スクリーン印刷法などにより、銅ペーストなどの導電性ペーストからなる上部導通部形成用ペーストを充填し、硬化させることにより、上下導通部２３を第２の上下導通部５の上面に接続させて形成する。次に、保護シート６２を剥離する。以下の工程は、上記第１実施形態の場合と同じであるので、その説明を省略する。 Next, an opening 22 is formed in the insulating layer 21 on the upper surface of the second vertical conduction portion 5 substantially at the center by laser processing that irradiates a laser beam such as a CO 2 laser. Next, the upper conductive portion 23 is formed in the second conductive portion 23 by filling the opening 22 of the insulating layer 21 with a paste for forming an upper conductive portion made of a conductive paste such as a copper paste by screen printing or the like and curing the paste. The upper and lower conductive parts 5 are connected to the upper surface. Next, the protective sheet 62 is peeled off. Since the following steps are the same as those in the first embodiment, description thereof is omitted.

（第３実施形態）
図２３はこの発明の第３実施形態としての半導体装置の断面図を示す。この半導体装置において、図１５に示す半導体装置と異なる点は、半導体構成体６を、配線１４を含む保護膜１１の下面にソルダーレジストなどからなるオーバーコート膜１６を設け、配線１４の接続パッド部に対応する部分におけるオーバーコート膜１６に開口部１７を設けた構造とした点である。この場合、半導体構成体６は、第１の上下導通部４のベース板１の上面から突出された突出部がオーバーコート膜１６の開口部１７内に入り込んで配線１４の接続パッド部下面に接続され、オーバーコート膜１６の下面がベース板１の上面に直接固着された状態で、ベース板１上に搭載されている。 (Third embodiment)
FIG. 23 is a sectional view of a semiconductor device as a third embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 15 in that the semiconductor structure 6 is provided with an overcoat film 16 made of a solder resist or the like on the lower surface of the protective film 11 including the wiring 14, and the connection pad portion of the wiring 14. The overcoat film 16 has a structure in which an opening 17 is provided in a portion corresponding to the above. In this case, in the semiconductor structure 6, the protruding portion protruding from the upper surface of the base plate 1 of the first vertical conduction portion 4 enters the opening 17 of the overcoat film 16 and is connected to the lower surface of the connection pad portion of the wiring 14. The overcoat film 16 is mounted on the base plate 1 in a state where the lower surface of the overcoat film 16 is directly fixed to the upper surface of the base plate 1.

（第４実施形態）
図２４はこの発明の第４実施形態としての半導体装置の断面図を示す。この半導体装置において、図１に示す半導体装置と大きく異なる点は、下層配線および上層配線を共に１層とした点である。すなわち、下層配線４２を含むベース板１の下面には、スクリーン印刷法やスピンコート法などにより、ソルダーレジストなどからなる下層絶縁膜７１が形成されている。下層配線４２の接続パッド部に対応する部分における下層絶縁膜７１に形成された開口部７２内およびその下方には半田ボール４８が下層配線４２の接続パッド部下面に接続されて形成されている。 (Fourth embodiment)
FIG. 24 is a sectional view of a semiconductor device as a fourth embodiment of the present invention. This semiconductor device differs greatly from the semiconductor device shown in FIG. 1 in that both the lower layer wiring and the upper layer wiring are formed as one layer. That is, a lower insulating film 71 made of a solder resist or the like is formed on the lower surface of the base plate 1 including the lower wirings 42 by screen printing or spin coating. A solder ball 48 is connected to the lower surface of the connection pad portion of the lower layer wiring 42 in and below the opening 72 formed in the lower layer insulating film 71 in a portion corresponding to the connection pad portion of the lower layer wiring 42.

半導体構成体６の上面および半導体構成体６の周囲における第２の上下導通部５を含むベース板１の上面には絶縁層２１が形成されている。絶縁層２１の上面には上層下地金属層２４を含む上層配線２５が形成されている。上層配線２５の接続パッド部上面には別の半導体構成体３１の柱状電極１５下に設けられた半田ボール３３が接合されている。この場合、図６に示すような工程において、半導体構成体６の上面および半導体構成体６の周囲における第２の上下導通部５を含むベース板１の上面に絶縁層２１を形成する。   An insulating layer 21 is formed on the upper surface of the semiconductor structure 6 and the upper surface of the base plate 1 including the second vertical conduction portion 5 around the semiconductor structure 6. On the upper surface of the insulating layer 21, an upper wiring 25 including an upper base metal layer 24 is formed. A solder ball 33 provided under the columnar electrode 15 of another semiconductor structure 31 is joined to the upper surface of the connection pad portion of the upper layer wiring 25. In this case, in a process as shown in FIG. 6, the insulating layer 21 is formed on the upper surface of the semiconductor structure 6 and the upper surface of the base plate 1 including the second vertical conduction portion 5 around the semiconductor structure 6.

（その他の実施形態）
例えば、上記第１実施形態では、互いに隣接する半導体構成体６間において切断したが、これに限らず、２個またはそれ以上の半導体構成体６を１組として切断し、マルチチップモジュール型の半導体装置を得るようにしてもよい。また、ベース板１の下面に、上下導通部３に接続される第１の下層配線２３を設け、この第１の下層配線(配線）４２の接続パッド部に、上下導通部４５および第２の下層配線４７を介して半田ボール４８を接続しているが、上下導通部４下に、直接、半田ボールや電子部品を接合してもよい。また、例えば、上記第１実施形態では、第２の上層配線３０の接続パッド部上にＣＳＰと呼ばれる半導体構成体３１を搭載しているが、これに限らず、ベアチップなどの他の半導体構成体やコンデンサ、抵抗などのチップ部品などからなる電子部品を搭載するようにしてもよい。 (Other embodiments)
For example, in the first embodiment, the semiconductor structures 6 that are adjacent to each other are cut. However, the present invention is not limited to this, and two or more semiconductor structures 6 are cut as a set to form a multichip module type semiconductor. An apparatus may be obtained. Also, a first lower layer wiring 23 connected to the vertical conduction part 3 is provided on the lower surface of the base plate 1, and the vertical conduction part 45 and the second conduction line 45 are connected to the connection pad part of the first lower layer wiring (wiring) 42. Although the solder ball 48 is connected via the lower layer wiring 47, a solder ball or an electronic component may be directly joined under the vertical conduction part 4. Further, for example, in the first embodiment, the semiconductor structure 31 called CSP is mounted on the connection pad portion of the second upper layer wiring 30. However, the present invention is not limited to this, and other semiconductor structures such as a bare chip. Alternatively, an electronic component such as a chip component such as a capacitor or a resistor may be mounted.

この発明の第１実施形態としての半導体装置の断面図。1 is a cross-sectional view of a semiconductor device as a first embodiment of the present invention. 図１に示す半導体装置の製造方法の一例において、当初の工程の断面図。Sectional drawing of the initial process in an example of the manufacturing method of the semiconductor device shown in FIG. 図２に続く工程の断面図。Sectional drawing of the process following FIG. 図３に続く工程の断面図。Sectional drawing of the process following FIG. 図４に続く工程の断面図。Sectional drawing of the process following FIG. 図５に続く工程の断面図。Sectional drawing of the process following FIG. 図６に続く工程の断面図。Sectional drawing of the process following FIG. 図７に続く工程の断面図。Sectional drawing of the process following FIG. 図８に続く工程の断面図。FIG. 9 is a cross-sectional view of the process following FIG. 8. 図９に続く工程の断面図。Sectional drawing of the process following FIG. 図１０に続く工程の断面図。Sectional drawing of the process following FIG. 図１１に続く工程の断面図。Sectional drawing of the process following FIG. 図１２に続く工程の断面図。Sectional drawing of the process following FIG. 図１３に続く工程の断面図。Sectional drawing of the process following FIG. この発明の第２実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 2nd Embodiment of this invention. 図１５に示す半導体構成体の製造方法の一例において、所定の工程の断面 図。Sectional drawing of a predetermined | prescribed process in an example of the manufacturing method of the semiconductor structure shown in FIG. 図１９に続く工程の断面図。FIG. 20 is a cross-sectional view of the process following FIG. 19. 図１７に続く工程の断面図。FIG. 18 is a cross-sectional view of the process following FIG. 17. 図１８に続く工程の断面図。FIG. 19 is a cross-sectional view of the process following FIG. 18. 図１９に続く工程の断面図。FIG. 20 is a cross-sectional view of the process following FIG. 19. 図２０に続く工程の断面図。FIG. 21 is a cross-sectional view of the process following FIG. 20. 図２１に続く工程の断面図。FIG. 22 is a sectional view of a step following FIG. 21. この発明の第３実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 3rd Embodiment of this invention. この発明の第４実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 4th Embodiment of this invention.

符号の説明Explanation of symbols

１ ベース板
４ 第１の上下導通部
５ 第２の上下導通部
６ 半導体構成体
７ シリコン基板（半導体基板）
８ 接続パッド
１４ 配線（再配線）
１５ 柱状電極（外部接続用電極）
２１ 絶縁層
２３ 上下導通部
２５ 第１の上層配線
２６ 上層絶縁膜
３０ 第２の上層配線
３１ 別の半導体構成体
４２ 第１の下層配線（配線）
４３ 下層絶縁膜
４５ 上下導通部
４７ 第２の下層配線
４８ 半田ボール DESCRIPTION OF SYMBOLS 1 Base board 4 1st vertical conduction | electrical_connection part 5 2nd vertical conduction | electrical_connection part 6 Semiconductor structure 7 Silicon substrate (semiconductor substrate)
8 Connection pads 14 Wiring (rewiring)
15 Columnar electrode (external connection electrode)
DESCRIPTION OF SYMBOLS 21 Insulating layer 23 Vertical conduction | electrical_connection part 25 1st upper layer wiring 26 Upper layer insulating film 30 2nd upper layer wiring 31 Another semiconductor structure 42 1st lower layer wiring (wiring)
43 Lower layer insulating film 45 Vertical conduction part 47 Second lower layer wiring 48 Solder ball

Claims (11)

少なくとも半硬化状態の熱硬化性樹脂を含む絶縁材料からなるベース板形成用シートに上下導通用の開口部を形成する工程と、
前記ベース板形成用シートの開口部内に導電性ペーストからなる上下導通部形成用ペーストを充填する工程と、
前記上下導通部形成用ペーストを含む前記ベース板形成用シート上に、半導体基板、該半導体基板の一面に設けられた複数の外部接続用電極を有する複数の半導体構成体を相互に離間させて配置する工程と、
前記ベース板形成用シート中の熱硬化性樹脂を硬化させてベース板を形成するとともに、前記上下導通部形成用ペーストを硬化させて上下導通部を形成し、且つ、前記ベース板上に前記半導体構成体を、前記外部接続用電極を前記上下導通部に食い込ませた状態で、固着する工程と、
少なくとも前記半導体構成体の周囲における前記ベース板上に絶縁層を形成する工程と、
前記半導体構成体間において前記絶縁層および前記ベース板を切断して、前記半導体構成体が少なくとも１つ含まれる半導体装置を複数個得る工程と、
を含むことを特徴とする半導体装置の製造方法。 Forming an opening for vertical conduction in a base plate forming sheet made of an insulating material containing at least a semi-cured thermosetting resin;
Filling the upper and lower conductive portion forming paste made of a conductive paste into the opening of the base plate forming sheet;
A plurality of semiconductor structures having a semiconductor substrate and a plurality of external connection electrodes provided on one surface of the semiconductor substrate are arranged on the base plate forming sheet including the upper and lower conductive portion forming paste so as to be separated from each other. And the process of
The thermosetting resin in the base plate forming sheet is cured to form a base plate, the vertical conductive portion forming paste is cured to form a vertical conductive portion, and the semiconductor is formed on the base plate. Fixing the structure with the external connection electrode biting into the vertical conduction part; and
Forming an insulating layer on the base plate at least around the semiconductor structure;
Cutting the insulating layer and the base plate between the semiconductor structures to obtain a plurality of semiconductor devices including at least one semiconductor structure;
A method for manufacturing a semiconductor device, comprising: 請求項１に記載の発明において、前記半導体構成体は、再配線の接続パッド部上に設けられた前記外部接続用電極としての柱状電極を有するものであり、前記柱状電極を前記上下導通部に食い込ませるとともに前記再配線を前記ベース板に埋め込むことを特徴とする半導体装置の製造方法。 In the invention according to claim 1 , the semiconductor structure includes a columnar electrode as the external connection electrode provided on a connection pad portion of a rewiring, and the columnar electrode is used as the vertical conduction portion. A method of manufacturing a semiconductor device, wherein the rewiring is embedded in the base plate while biting in. 請求項１または２に記載の発明において、前記ベース板形成用シートの開口部内に上下導通部形成用ペーストを充填する工程は、前記ベース板形成用シート下に保護シートを配置し、前記ベース板形成用シートの開口部内に上下導通部形成用ペーストを充填する工程であることを特徴とする半導体装置の製造方法。 3. The process according to claim 1 , wherein the step of filling the base plate forming sheet with the upper and lower conductive portion forming paste includes a protective sheet disposed under the base plate forming sheet, and the base plate. A method of manufacturing a semiconductor device, comprising a step of filling an upper and lower conductive portion forming paste into an opening of a forming sheet. 請求項３に記載の発明において、前記上下導通部形成用ペーストを含む前記ベース板形成用シート上に前記半導体構成体を配置する工程は、前記半導体構成体を予め加熱しておき、加熱加圧により、前記半導体構成体の外部接続用電極を前記上下導通部形成用ペーストに仮固着する工程であることを特徴とする半導体装置の製造方法。 In the invention according to claim 3 , in the step of disposing the semiconductor structure on the base plate forming sheet including the vertical conduction part forming paste, the semiconductor structure is preheated and heated and pressed. The method of manufacturing a semiconductor device, characterized in that the step of temporarily fixing the external connection electrode of the semiconductor structure to the paste for forming the upper and lower conductive portions is provided. 請求項４に記載の発明において、前記ベース板上に前記半導体構成体を固着する工程後に、前記保護シートを剥離することを特徴とする半導体装置の製造方法。 5. The method of manufacturing a semiconductor device according to claim 4 , wherein the protective sheet is peeled after the step of fixing the semiconductor structure on the base plate. 少なくとも半硬化状態の熱硬化性樹脂を含む絶縁材料からなるベース板形成用シートに上下導通用の開口部を形成する工程と、
前記ベース板形成用シートの開口部内およびその上方に導電性ペーストからなる上下導通部形成用ペーストを形成する工程と、
前記上下導通部形成用ペーストを含む前記ベース板形成用シート上に、半導体基板および該半導体基板の一面に設けられた複数の再配線を有する複数の半導体構成体を相互に離間させて配置する工程と、
前記ベース板形成用シート中の熱硬化性樹脂を硬化させてベース板を形成するとともに、前記上下導通部形成用ペーストを硬化させて上下導通部を形成し、且つ、前記ベース板上に前記半導体構成体を、前記再配線の接続パッド部を前記上下導通部に接続させ、且つ、前記再配線を前記ベース板に埋め込んだ状態で、固着する工程と、
少なくとも前記半導体構成体の周囲における前記ベース板上に絶縁層を形成する工程と、
前記半導体構成体間において前記絶縁層および前記ベース板を切断して、前記半導体構成体が少なくとも１つ含まれる半導体装置を複数個得る工程と、
を含むことを特徴とする半導体装置の製造方法。 Forming an opening for vertical conduction in a base plate forming sheet made of an insulating material containing at least a semi-cured thermosetting resin;
Forming a vertical conductive part forming paste made of a conductive paste in and above the opening of the base plate forming sheet; and
A step of disposing a plurality of semiconductor structures having a semiconductor substrate and a plurality of rewirings provided on one surface of the semiconductor substrate on the base plate forming sheet including the upper and lower conductive portion forming paste. When,
The thermosetting resin in the base plate forming sheet is cured to form a base plate, the vertical conductive portion forming paste is cured to form a vertical conductive portion, and the semiconductor is formed on the base plate. Fixing the structure in a state where the connection pad portion of the rewiring is connected to the vertical conduction portion and the rewiring is embedded in the base plate;
Forming an insulating layer on the base plate at least around the semiconductor structure;
Cutting the insulating layer and the base plate between the semiconductor structures to obtain a plurality of semiconductor devices including at least one semiconductor structure;
A method for manufacturing a semiconductor device, comprising: 少なくとも半硬化状態の熱硬化性樹脂を含む絶縁材料からなるベース板形成用シートに上下導通用の開口部を形成する工程と、
前記ベース板形成用シートの開口部内およびその上方に導電性ペーストからなる上下導通部形成用ペーストを形成する工程と、
前記上下導通部形成用ペーストを含む前記ベース板形成用シート上に、半導体基板、該半導体基板の一面に設けられた複数の再配線および該再配線の接続パッド部以外を覆うオーバーコート膜を有する複数の半導体構成体を相互に離間させて配置する工程と、
前記ベース板形成用シート中の熱硬化性樹脂を硬化させてベース板を形成するとともに、前記上下導通部形成用ペーストを硬化させて上下導通部を形成し、且つ、前記ベース板上に前記半導体構成体を、前記上下導通部の前記開口部の上方に形成された部分を前記再配線の接続パッド部に接続させた状態で、固着する工程と、
少なくとも前記半導体構成体の周囲における前記ベース板上に絶縁層を形成する工程と、
前記半導体構成体間において前記絶縁層および前記ベース板を切断して、前記半導体構成体が少なくとも１つ含まれる半導体装置を複数個得る工程と、
を含むことを特徴とする半導体装置の製造方法。 Forming an opening for vertical conduction in a base plate forming sheet made of an insulating material containing at least a semi-cured thermosetting resin;
Forming a vertical conductive part forming paste made of a conductive paste in and above the opening of the base plate forming sheet; and
On the base plate forming sheet containing the upper and lower conductive portion forming paste, there is a semiconductor substrate, a plurality of rewirings provided on one surface of the semiconductor substrate, and an overcoat film covering other than the connection pad portions of the rewiring. A step of arranging a plurality of semiconductor structures separated from each other;
The thermosetting resin in the base plate forming sheet is cured to form a base plate, the vertical conductive portion forming paste is cured to form a vertical conductive portion, and the semiconductor is formed on the base plate. Fixing the structure in a state in which the portion formed above the opening of the vertical conduction portion is connected to the connection pad portion of the rewiring; and
Forming an insulating layer on the base plate at least around the semiconductor structure;
Cutting the insulating layer and the base plate between the semiconductor structures to obtain a plurality of semiconductor devices including at least one semiconductor structure;
A method for manufacturing a semiconductor device, comprising: 請求項６または７に記載の発明において、前記ベース板形成用シートに開口部を形成する工程は、前記ベース板形成用シート上に突出部形成用シートを積層し、前記ベース板形成用シートおよび前記突出部形成用シートに開口部を形成する工程であることを特徴とする半導体装置の製造方法。 The invention according to claim 6 or 7 , wherein the step of forming an opening in the base plate forming sheet includes laminating a protruding portion forming sheet on the base plate forming sheet, and the base plate forming sheet and A method of manufacturing a semiconductor device, comprising the step of forming an opening in the protrusion forming sheet. 請求項８に記載の発明において、前記ベース板形成用シートの開口部内およびその上方に上下導通部形成用ペーストを形成する工程は、前記ベース板形成用シート下に保護シートを配置し、前記ベース板形成用シートおよび前記突出部形成用シートの開口部内に上下導通部形成用ペーストを充填し、この後前記突出部形成用シートを剥離して、前記上下導通部形成用ペーストの上部を前記ベース板形成用シート上に突出させる工程であることを特徴とする半導体装置の製造方法。 In the invention according to claim 8 , the step of forming the upper and lower conductive portion forming paste in and above the opening of the base plate forming sheet includes disposing a protective sheet under the base plate forming sheet, and The upper and lower conductive portion forming paste is filled in the plate forming sheet and the opening of the protruding portion forming sheet, and then the protruding portion forming sheet is peeled off, and the upper portion of the vertical conductive portion forming paste is placed on the base. A method of manufacturing a semiconductor device, characterized by being a step of projecting on a plate forming sheet. 請求項９に記載の発明において、前記ベース板上に前記半導体構成体を固着する工程後に、前記保護シートを剥離することを特徴とする半導体装置の製造方法。 10. The method of manufacturing a semiconductor device according to claim 9 , wherein the protective sheet is peeled after the step of fixing the semiconductor structure onto the base plate. 請求項１、２、６、７のいずれかに記載の発明において、さらに、前記上下導通部を含む前記ベース板下に下層配線を前記上下導通部に接続させて形成する工程を備えていることを特徴とする半導体装置の製造方法。 The invention according to any one of claims 1 , 2 , 6 , and 7 , further comprising a step of forming a lower layer wiring connected to the vertical conduction portion under the base plate including the vertical conduction portion. A method of manufacturing a semiconductor device.
JP2004362117A 2004-12-14 2004-12-15 Manufacturing method of semiconductor device Expired - Fee Related JP4042741B2 (en)

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