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JP4040551B2 - Semiconductor device mounting method - Google Patents

Semiconductor device mounting method Download PDF

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Publication number
JP4040551B2
JP4040551B2 JP2003270782A JP2003270782A JP4040551B2 JP 4040551 B2 JP4040551 B2 JP 4040551B2 JP 2003270782 A JP2003270782 A JP 2003270782A JP 2003270782 A JP2003270782 A JP 2003270782A JP 4040551 B2 JP4040551 B2 JP 4040551B2
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semiconductor element
substrate
solder
mounting
bonding
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JP2005026628A (en
Inventor
智之 渡邊
晶紀 江田
武 森田
和俊 山口
隆雄 塩山
哲之 平島
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Mitsui High Tech Inc
Toyota Motor Corp
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Mitsui High Tech Inc
Toyota Motor Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/741Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L24/743Apparatus for manufacturing layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175Flow barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/743Apparatus for manufacturing layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Description

本発明は、半導体素子を、はんだ接合により基板に実装する半導体素子実装方法に関する。   The present invention relates to a semiconductor element mounting method for mounting a semiconductor element on a substrate by solder bonding.

従来、パワー素子等の半導体素子を、はんだ接合により基板に実装する場合には、基板に対する半導体素子の高い位置精度が要求されるため、治具にて基板に対する半導体素子の位置決めを行いつつ、半導体素子を基板へ実装していた。
例えば、図9に示すように、治具121は、基板101の外形寸法に合わせて形成される下凹部121aにて、基板101に対する治具121の位置決めを行いながら基板101にセットされている。
該治具121の上側には、半導体素子102の外形寸法に合わせて形成される上凹部121bが形成されており、該上凹部121bにはんだ箔103及び半導体素子102を嵌め込んで基板101上にセットすることで、基板101に対する半導体素子102の位置決めを行いつつ、半導体素子102を基板101へはんだ接合により実装することが可能となっている。
Conventionally, when a semiconductor element such as a power element is mounted on a substrate by solder bonding, a high positional accuracy of the semiconductor element with respect to the substrate is required. The element was mounted on the substrate.
For example, as shown in FIG. 9, the jig 121 is set on the substrate 101 while positioning the jig 121 with respect to the substrate 101 in a lower recess 121 a formed in accordance with the outer dimensions of the substrate 101.
On the upper side of the jig 121, an upper recess 121b is formed in accordance with the outer dimensions of the semiconductor element 102. The solder foil 103 and the semiconductor element 102 are fitted into the upper recess 121b and placed on the substrate 101. By setting, the semiconductor element 102 can be mounted on the substrate 101 by solder bonding while positioning the semiconductor element 102 with respect to the substrate 101.

しかし、このような治具121を用いて、半導体素子102と基板101とをはんだ接合するためには、それぞれの半導体素子102及び基板101の形状に合わせた治具121を作製しなくてはならず、多種の治具121を保有しておかなくてはならないため、コスト高となってしまう。
また、治具121の上凹部121bの寸法は、半導体素子102をセットする際の容易さや、半導体素子102及び治具121の構成部材の線膨張率や、半導体素子102及び治具121の寸法精度等を考慮して、半導体素子102の外形よりも若干大きめに形成する必要があるため、治具121と半導体素子102との間には所定のクリアランスdが生じることとなって、はんだ接合後における基板101に対する半導体素子102の実装位置を高精度に制御することができない。
さらに、接合後におけるはんだ厚みは、接合前のはんだ箔の厚みに依存しており、はんだ内に生じるボイドの有無やはんだの濡れ性・広がり性によってもはんだ厚みが変化する。特に、はんだ接合時には半導体素子102を支持するものがないため、図10に示すように、はんだが溶融している間に半導体素子102が傾き、そのままはんだが凝固してしまう恐れもある。
However, in order to solder-bond the semiconductor element 102 and the substrate 101 using such a jig 121, it is necessary to manufacture the jig 121 according to the shape of each semiconductor element 102 and the substrate 101. First, since various jigs 121 must be held, the cost increases.
Further, the dimensions of the upper recess 121b of the jig 121 are the ease of setting the semiconductor element 102, the linear expansion coefficient of the constituent elements of the semiconductor element 102 and the jig 121, and the dimensional accuracy of the semiconductor element 102 and the jig 121. In view of the above, since it is necessary to form the semiconductor element 102 slightly larger than the outer shape of the semiconductor element 102, a predetermined clearance d is generated between the jig 121 and the semiconductor element 102. The mounting position of the semiconductor element 102 with respect to the substrate 101 cannot be controlled with high accuracy.
Furthermore, the solder thickness after joining depends on the thickness of the solder foil before joining, and the solder thickness varies depending on the presence or absence of voids generated in the solder and the wettability / spreadability of the solder. In particular, since there is nothing to support the semiconductor element 102 at the time of soldering, as shown in FIG. 10, the semiconductor element 102 may tilt while the solder is melted, and the solder may solidify as it is.

このように、半導体素子を基板にはんだ接合する際に生ずる、はんだ厚みの変化や半導体素子の傾きを抑えるための技術として、特許文献1に記載されるような技術が知られている。
即ち、はんだバンプが形成された半導体素子を基板に実装する際、半導体素子と基板との間にペースト状の熱硬化性樹脂を供給し、該熱硬化性樹脂を熱硬化させて半導体素子の基板に対する位置及び間隔を一定に保持した後に、リフローによりはんだバンプを溶融させて接合を行う技術が、特許文献1に記載されている。
As described above, a technique described in Patent Document 1 is known as a technique for suppressing a change in solder thickness and a tilt of a semiconductor element that occur when a semiconductor element is soldered to a substrate.
That is, when a semiconductor element on which solder bumps are formed is mounted on a substrate, a paste-like thermosetting resin is supplied between the semiconductor element and the substrate, and the thermosetting resin is thermally cured to provide a substrate for the semiconductor element. Japanese Patent Application Laid-Open No. H10-228688 describes a technique in which solder bumps are melted by reflow and the bonding is performed after the position and interval with respect to is kept constant.

特開2000−58597号公報JP 2000-58597 A

前述の如くの、半導体素子と基板との間にペースト状の熱硬化性樹脂を供給して、該熱硬化樹脂をはんだ接合の前に熱硬化する技術を、半導体素子をはんだ接合により基板に実装する場合に適用すると、ペースト状の熱硬化性樹脂が半導体素子とはんだ箔との間、又ははんだ箔と基板との間に浸入して接合不良となる部分が発生する。
特に、半導体素子と基板とを接合するはんだ箔は、微小面積で基板に接するはんだバンプとは異なり、半導体素子と基板との接合面積が広いため、半導体素子と基板との間にはんだ箔を介装するとともに樹脂を供給した状態で、半導体素子に圧力をかけて熱圧着したとしても、半導体素子とはんだ箔との間又ははんだ箔と基板との間に浸入した熱硬化性樹脂を圧力により追い出すことは困難である。
As described above, the technology of supplying paste-like thermosetting resin between the semiconductor element and the substrate and thermosetting the thermosetting resin before solder bonding is mounted on the substrate by solder bonding. If it is applied, a paste-like thermosetting resin enters between the semiconductor element and the solder foil or between the solder foil and the substrate, resulting in a defective portion.
In particular, a solder foil that joins a semiconductor element and a substrate has a small area and, unlike a solder bump that touches the substrate, has a large joint area between the semiconductor element and the substrate. Therefore, the solder foil is interposed between the semiconductor element and the substrate. Even if pressure is applied to the semiconductor element while the resin is supplied and the resin is supplied, the thermosetting resin that has entered between the semiconductor element and the solder foil or between the solder foil and the substrate is expelled by the pressure. It is difficult.

上記課題を解決する本発明の半導体素子実装方法は、以下の特徴を有する。
即ち、請求項1においては、半導体素子を、はんだ接合により基板に実装する半導体素子実装方法であって、熱硬化性樹脂製のテープ部材が貼着された基板上に半導体素子をセットして、テープ部材により半導体素子の実装位置を仮固定する工程と、セットした半導体素子を基板に対して熱圧着することで、テープ部材をはんだ箔厚まで押しつぶすとともに熱硬化させる工程と、リフローにて半導体素子と基板とをはんだ接合する工程とを備える。
これにより、リフローを行う時には、既に半導体素子は基板に対して位置固定されていることとなるため、はんだが溶融することにより半導体素子が位置ズレしたり、傾いたりすることはない。
従って、治具を用いることなくリフロー処理しても、高い位置精度ではんだ接合を行って半導体素子を実装することができる。
また、半導体素子と基板との間隔は熱圧着時に固定されるので、はんだ接合後のはんだ膜厚も一定厚に制御することが可能である。
さらに、低コスト化を図ることもできる。
The semiconductor element mounting method of the present invention that solves the above problems has the following characteristics.
That is, in claim 1, a semiconductor element mounting method for mounting a semiconductor element on a substrate by solder bonding, wherein the semiconductor element is set on a substrate on which a thermosetting resin tape member is adhered, The step of temporarily fixing the mounting position of the semiconductor element with the tape member, the step of crushing the tape member to the thickness of the solder foil and thermosetting it by thermocompression bonding the set semiconductor element to the substrate, and the semiconductor element by reflow And a step of soldering the substrate and the substrate.
Thereby, when performing reflow, since the position of the semiconductor element is already fixed with respect to the substrate, the position of the semiconductor element is not shifted or tilted by melting of the solder.
Therefore, even if the reflow process is performed without using a jig, the semiconductor element can be mounted by performing solder bonding with high positional accuracy.
In addition, since the distance between the semiconductor element and the substrate is fixed at the time of thermocompression bonding, it is possible to control the solder film thickness after soldering to a constant thickness.
Furthermore, cost reduction can be achieved.

また、請求項2においては、半導体素子を、はんだ接合により基板に実装する半導体素子実装方法であって、熱硬化性樹脂製のテープ部材が貼着された基板上に半導体素子をセットして、テープ部材により半導体素子の実装位置を仮固定する工程と、基板上における半導体素子の近接位置に固形はんだを載置する工程と、リフローにて半導体素子と基板とをはんだ接合する工程とを備える。
これにより、半導体素子の基板に対する位置決め用の治具を用いたり、基板と半導体素子との間のはんだ注入用の空間を保持するための機構を特別に設けたりすることなく、半導体素子の実装位置・傾き、及びはんだ厚を高い精度で制御しながらはんだ接合を行って半導体素子を実装するとともに、低コスト化を図ることができる。
Further, in claim 2, a semiconductor element mounting method for mounting a semiconductor element on a substrate by solder bonding, wherein the semiconductor element is set on a substrate to which a thermosetting resin tape member is attached, A step of temporarily fixing a mounting position of the semiconductor element with a tape member; a step of placing solid solder on a position close to the semiconductor element on the substrate; and a step of soldering the semiconductor element and the substrate by reflow.
As a result, the mounting position of the semiconductor element can be obtained without using a jig for positioning the semiconductor element with respect to the substrate and without providing a special mechanism for maintaining a space for solder injection between the substrate and the semiconductor element. -It is possible to reduce the cost while mounting the semiconductor element by performing solder joining while controlling the tilt and the solder thickness with high accuracy.

また、請求項3においては、前記基板表面には、リフロー時に溶融したはんだの流れ方向を制御するための凹凸部が形成されている。
これにより、溶融したはんだの濡れ広がり性を向上することができる。
はんだの濡れ広がり性が向上することで、はんだが半導体素子の下面全体に容易に広がることが可能となり、凝固したはんだ内にボイドが生じたり、はんだ接合が不十分である箇所が生じたりすることを防ぐことができ、半導体素子から基板への熱伝導性が低下することを防止できる。
According to a third aspect of the present invention, an uneven portion for controlling the flow direction of solder melted during reflow is formed on the substrate surface.
Thereby, the wet spreading property of the melted solder can be improved.
Improved solder wettability allows the solder to spread easily over the entire lower surface of the semiconductor element, resulting in voids in the solidified solder and places where solder joints are insufficient. It is possible to prevent the thermal conductivity from the semiconductor element to the substrate from being lowered.

本発明によれば、
治具を用いることなくリフロー処理しても、高い位置精度ではんだ接合を行って半導体素子を実装することができる。また、はんだ接合後のはんだ膜厚も一定厚に制御することが可能であり、低コスト化を図ることもできる。
また、溶融したはんだの濡れ広がり性を向上することができ、凝固したはんだ内にボイドが生じたり、はんだ接合が不十分である箇所が生じたりすることを防ぐことができて、半導体素子から基板への熱伝導性が低下することを防止できる。
According to the present invention,
Even if the reflow process is performed without using a jig, the semiconductor element can be mounted by soldering with high positional accuracy. In addition, the solder film thickness after soldering can be controlled to a constant thickness, and the cost can be reduced.
In addition, the wet spreadability of the molten solder can be improved, and voids in the solidified solder can be prevented, and inadequate solder joints can be generated. It is possible to prevent the heat conductivity from being lowered.

本発明を実施するための最良の形態を、添付の図面を用いて説明する。   The best mode for carrying out the present invention will be described with reference to the accompanying drawings.

まず、本発明の半導体素子実装方法における第一の実施形態について説明する。
図1、図2に示すように、半導体素子2が接合される基板1の上面に、半導体素子2の接合位置に合わせてはんだ箔3及び固定テープ5をセットする(図1(a)、S01)。
はんだ箔3は、半導体素子2の底面と略同じ大きさの箔状に形成されている。また、固定テープ5は、例えば、基材にポリイミド等の耐熱樹脂を用いて、熱硬化性樹脂をテープ状に形成したものであり、はんだ箔3の周囲における複数箇所に配置されている。図1では、固定テープ5をはんだ箔3周囲の4箇所に配置しているが、固定テープ5上に半導体素子2を載置した際に半導体素子2が安定してセットできればよく、3箇所以上に配置していればよい。
First, a first embodiment of the semiconductor element mounting method of the present invention will be described.
As shown in FIGS. 1 and 2, the solder foil 3 and the fixing tape 5 are set on the upper surface of the substrate 1 to which the semiconductor element 2 is bonded in accordance with the bonding position of the semiconductor element 2 (FIG. 1A, S01). ).
The solder foil 3 is formed in a foil shape having substantially the same size as the bottom surface of the semiconductor element 2. The fixing tape 5 is formed by forming a thermosetting resin in a tape shape using a heat-resistant resin such as polyimide as a base material, and is disposed at a plurality of locations around the solder foil 3. In FIG. 1, the fixing tape 5 is arranged at four locations around the solder foil 3, but it is sufficient that the semiconductor element 2 can be stably set when the semiconductor element 2 is placed on the fixing tape 5. It only has to be arranged in.

その後、セットした複数の固定テープ5上に半導体素子2を載置し(S02)、図1(b)に示すように、半導体素子2の上方から圧力及び熱を加えて熱圧着する(S03)。
熱圧着では、基板1と半導体素子2との間隔がはんだ箔3の厚みと略同じになるまで固定テープ5を押し潰すとともに、固定テープ5を加熱して該固定テープ5の熱硬化性樹脂を硬化させる。
Thereafter, the semiconductor element 2 is placed on the plurality of fixed tapes 5 set (S02), and as shown in FIG. 1B, pressure and heat are applied from above the semiconductor element 2 to perform thermocompression bonding (S03). .
In the thermocompression bonding, the fixing tape 5 is crushed until the distance between the substrate 1 and the semiconductor element 2 becomes substantially the same as the thickness of the solder foil 3, and the fixing tape 5 is heated to remove the thermosetting resin of the fixing tape 5. Harden.

固定テープ5の熱硬化性樹脂が硬化することで、半導体素子2の基板1に対する位置、及び半導体素子2と基板1との間隔が保持される。
なお、熱圧着工程ではんだ箔3が溶融することを防止するために、固定テープ5には硬化温度がはんだ箔の溶融温度以下の熱硬化性樹脂を用いており、熱圧着により加熱される固定テープ5の加熱温度は、はんだ箔の溶融温度以下となっている。
また、圧着後の固定テープ5の厚みは、例えば数十μmから数百μm程度となっている。
As the thermosetting resin of the fixing tape 5 is cured, the position of the semiconductor element 2 relative to the substrate 1 and the distance between the semiconductor element 2 and the substrate 1 are maintained.
In order to prevent the solder foil 3 from melting in the thermocompression bonding process, the fixing tape 5 uses a thermosetting resin having a curing temperature equal to or lower than the melting temperature of the solder foil, and is fixed by heating by thermocompression bonding. The heating temperature of the tape 5 is not higher than the melting temperature of the solder foil.
Further, the thickness of the fixing tape 5 after the pressure bonding is, for example, about several tens μm to several hundreds μm.

図1(c)に示すように、半導体素子2の位置決めがなされた後にリフローを行い、はんだ箔3を溶融させて半導体素子2と基板1とをはんだ接合する(S04)。
リフロー時には、既に半導体素子2は基板1に対して位置固定されているため、はんだ溶融により半導体素子2が位置ズレしたり、傾いたりすることはない。
従って、半導体素子2を基板1にセットする際に、半導体素子2を位置精度良く固定テープ5上に載置して熱圧着すれば、治具を用いることなくリフロー処理しても、高い位置精度ではんだ接合して実装することができる。
また、半導体素子2と基板1との間隔は熱圧着時に固定されるので、はんだ接合後のはんだ膜厚も一定厚に制御することが可能である。
As shown in FIG. 1C, after the semiconductor element 2 is positioned, reflow is performed to melt the solder foil 3 and solder the semiconductor element 2 and the substrate 1 (S04).
At the time of reflow, since the position of the semiconductor element 2 is already fixed with respect to the substrate 1, the position of the semiconductor element 2 is not shifted or tilted due to melting of the solder.
Accordingly, when the semiconductor element 2 is set on the substrate 1, if the semiconductor element 2 is placed on the fixing tape 5 with high positional accuracy and thermocompression bonded, high positional accuracy can be achieved even if reflow processing is performed without using a jig. Can be soldered and mounted.
Moreover, since the space | interval of the semiconductor element 2 and the board | substrate 1 is fixed at the time of thermocompression bonding, it is possible to control the solder film thickness after solder joining to fixed thickness.

半導体素子2が、作動時に発熱するパワー素子に構成される場合は、半導体素子2を実装した基板1をさらに放熱板とはんだ接合して、放熱効率を高めることが行われる。
この基板1を放熱板とはんだ接合する際にも、前記固定テープ5により基板1を放熱板に位置固定することで、高精度のはんだ接合を行うことができる。
When the semiconductor element 2 is configured as a power element that generates heat during operation, the substrate 1 on which the semiconductor element 2 is mounted is further soldered to a heat radiating plate to increase heat dissipation efficiency.
Even when the substrate 1 is soldered to the heat radiating plate, the position of the substrate 1 is fixed to the heat radiating plate by the fixing tape 5 so that high-precision soldering can be performed.

例えば、まず図3(a)、図3(b)に示すように、放熱板6の上面に、基板1の接合位置に合わせてはんだ箔7及び固定テープ5をセットするとともに、熱圧着により基板1の放熱板6に対する位置決め固定を行う。はんだ箔7は、基板1の底面と略同じ大きさの箔状に形成されている。
次に、図3(c)、図3(d)に示すように、放熱板6に位置決め固定された基板1の上面にはんだ箔3及び固定テープ5をセットし、前述の如く半導体素子2を熱圧着することで、基板1に対する半導体素子2の位置決め固定を行う。
For example, first, as shown in FIGS. 3A and 3B, the solder foil 7 and the fixing tape 5 are set on the upper surface of the heat radiating plate 6 in accordance with the bonding position of the substrate 1, and the substrate is formed by thermocompression bonding. 1 is fixed to the heat sink 6. The solder foil 7 is formed in a foil shape having substantially the same size as the bottom surface of the substrate 1.
Next, as shown in FIGS. 3C and 3D, the solder foil 3 and the fixing tape 5 are set on the upper surface of the substrate 1 positioned and fixed to the heat sink 6, and the semiconductor element 2 is mounted as described above. The semiconductor element 2 is positioned and fixed with respect to the substrate 1 by thermocompression bonding.

その後、図3(e)に示すように、互いに固定テープ5で位置固定された放熱板6、基板1及び半導体素子2をリフローして、はんだ箔7にて放熱板6と基板1とをはんだ接合するとともに、はんだ箔3にて基板1と半導体素子2とをはんだ接合する。
この場合も、半導体素子2の基板1に対する位置決め固定、及び基板1の放熱板6に対する位置決め固定が、固定テープ5によりそれぞれなされているので、治具を用いることなく高精度で半導体素子2を実装することができ、低コスト化を図ることもできる。
Thereafter, as shown in FIG. 3 (e), the heat radiating plate 6, the substrate 1 and the semiconductor element 2 which are fixed to each other by the fixing tape 5 are reflowed, and the heat radiating plate 6 and the substrate 1 are soldered by the solder foil 7. While joining, the board | substrate 1 and the semiconductor element 2 are solder-joined with the solder foil 3. FIG.
Also in this case, the positioning and fixing of the semiconductor element 2 with respect to the substrate 1 and the positioning and fixing of the substrate 1 with respect to the heat radiating plate 6 are performed by the fixing tape 5, so that the semiconductor element 2 can be mounted with high accuracy without using a jig. It is possible to reduce the cost.

次に、本発明の半導体素子実装方法における第二の実施形態について説明する。
本実施形態では、図4(a)に示すように、半導体素子2が接合される基板1の上面に、複数の固定テープ5をセットする。固定テープ5は、半導体素子2の実装位置に合わせて、該半導体素子2の周縁部に位置するように配置されている。
次に、固定テープ5上に半導体素子2を載置するとともに、熱圧着して固定テープ5を熱硬化させ、該半導体素子2の基板1に対する位置、及び半導体素子2と基板1との間隔を固定する。この場合の、圧着後の固定テープ5の厚みは、例えば数十μmから数百μm程度となっている。
Next, a second embodiment in the semiconductor element mounting method of the present invention will be described.
In the present embodiment, as shown in FIG. 4A, a plurality of fixing tapes 5 are set on the upper surface of the substrate 1 to which the semiconductor element 2 is bonded. The fixing tape 5 is disposed so as to be positioned at the peripheral edge of the semiconductor element 2 in accordance with the mounting position of the semiconductor element 2.
Next, the semiconductor element 2 is placed on the fixing tape 5 and the fixing tape 5 is thermally cured by thermocompression bonding, and the position of the semiconductor element 2 relative to the substrate 1 and the distance between the semiconductor element 2 and the substrate 1 are determined. Fix it. In this case, the thickness of the fixing tape 5 after pressure bonding is, for example, about several tens of μm to several hundreds of μm.

次に、図4(b)に示すように、基板1上における半導体素子2の近接部に、糸ハンダやはんだペレット等の固形はんだ13を設置する。
図4(c)のように、固形はんだ13を設置した後にリフローを行うと、固形はんだ13が溶融して、基板1と半導体素子2との間に形成される、固定テープ5の厚み分だけの隙間に、毛細管現象によってはんだが流入し、基板1と半導体素子2とがはんだ接合される。
Next, as shown in FIG. 4B, solid solder 13 such as thread solder or solder pellets is installed in the vicinity of the semiconductor element 2 on the substrate 1.
As shown in FIG. 4C, when reflow is performed after the solid solder 13 is installed, the solid solder 13 is melted and is formed between the substrate 1 and the semiconductor element 2 by the thickness of the fixing tape 5. Solder flows into the gap by capillary action, and the substrate 1 and the semiconductor element 2 are soldered.

これにより、半導体素子2に近接して配置した固形はんだによりはんだ接合を行う場合でも、半導体素子2の基板1に対する位置決め用の治具を用いたり、基板1と半導体素子2との間のはんだ注入用の空間を保持するための機構を特別に設けたりすることなく、半導体素子2の位置・傾き、及びはんだ厚を高い精度で制御しながらはんだ接合を行って半導体素子2を実装できるとともに、低コスト化を図ることができる。   Thus, even when solder bonding is performed using solid solder arranged close to the semiconductor element 2, a jig for positioning the semiconductor element 2 with respect to the substrate 1 is used, or solder injection between the substrate 1 and the semiconductor element 2 is performed. The semiconductor element 2 can be mounted by performing solder bonding while controlling the position / inclination of the semiconductor element 2 and the solder thickness with high accuracy without providing a special mechanism for maintaining the space for Cost can be reduced.

また、半導体素子2の近接部に設置した固形はんだ13によりはんだ接合を行う場合、次のように、基板1の表面に凹凸を形成することで、はんだの基板1表面に対する濡れ性を向上することができる。   Further, when solder bonding is performed using the solid solder 13 installed in the vicinity of the semiconductor element 2, the wettability of the solder to the surface of the substrate 1 is improved by forming irregularities on the surface of the substrate 1 as follows. Can do.

つまり、例えば図5(a)に示すように、基板1表面における固形はんだ13を設置する部分にはんだ設置用凹部1aを形成するとともに、該はんだ設置用凹部1aから半導体素子2側(図5における基板1の中央側)へ、スリット状に延出する流れ用凹部1bを形成する。
この基板1のはんだ設置用凹部1aに固形はんだ13を載置するとともに、図5(b)に示す如く固定テープ5を介して半導体素子2を熱圧着し、リフローを行うと、図5(c)に示すように、溶融したはんだが流れ用凹部1bを通じて半導体素子2の下方へ濡れ広がり、はんだが半導体素子2の底面全体に行き渡る。
なお、流れ用凹部1bは、図5では一本のみ形成したが、複数本形成してもよい。
That is, for example, as shown in FIG. 5 (a), the solder placement recess 1a is formed in the portion where the solid solder 13 is placed on the surface of the substrate 1, and the solder placement recess 1a is connected to the semiconductor element 2 side (in FIG. 5). A flow recess 1b extending in a slit shape is formed on the center side of the substrate 1).
When the solid solder 13 is placed in the solder installation recess 1a of the substrate 1 and the semiconductor element 2 is thermocompression bonded via the fixing tape 5 as shown in FIG. 5B, reflow is performed. ), The molten solder wets and spreads below the semiconductor element 2 through the flow recess 1b, and the solder spreads over the entire bottom surface of the semiconductor element 2.
Note that although only one flow recess 1b is formed in FIG. 5, a plurality of flow recesses 1b may be formed.

はんだ設置用凹部1a及び流れ用凹部1bを形成せずに基板1表面が均一に平面状であった場合は、表面のはんだ濡れ性の違いによって、はんだが基板1表面の全体に均等に広がらず、基板1と半導体素子2とのはんだ接合が不十分な箇所が生じたり、はんだ内にボイドが発生したりする恐れがある。
しかし、このように、はんだ設置用凹部1a及び流れ用凹部1bを形成することで、溶融したはんだが、はんだ設置用凹部1aから流れ用凹部1bを通じて流れ易くなり、濡れ広がり性を向上することができる。
はんだの濡れ広がり性が向上することで、はんだが半導体素子2の下面全体に容易に広がることが可能となり、凝固したはんだ内にボイドが生じたり、はんだ接合が不十分である箇所が生じたりすることを防ぐことができ、半導体素子2から基板1への熱伝導性を低下させることがない。
If the surface of the substrate 1 is uniformly flat without forming the solder installation recess 1a and the flow recess 1b, the solder does not spread evenly over the entire surface of the substrate 1 due to the difference in solder wettability of the surface. There is a risk that a location where solder bonding between the substrate 1 and the semiconductor element 2 is insufficient will occur or a void will occur in the solder.
However, by forming the solder installation recess 1a and the flow recess 1b in this way, the molten solder can easily flow from the solder installation recess 1a through the flow recess 1b, thereby improving the wetting spreadability. it can.
By improving the wettability of the solder, it becomes possible for the solder to spread easily over the entire lower surface of the semiconductor element 2, resulting in voids in the solidified solder and places where solder bonding is insufficient. This can be prevented, and the thermal conductivity from the semiconductor element 2 to the substrate 1 is not lowered.

また、さらに溶融はんだの濡れ広がり性を向上させるために、基板1表面に形成される前記流れ用凹部1bを、半導体素子2の一側端部から他側端部まで(図6では半導体素子2の左側端部から右側端部まで)伸ばし、該流れ用凹部1bから斜め方向へ複数の枝凹部1cを形成してもよい。枝凹部1cは、流れ用凹部1bから半導体素子2の他側方向へ向かって延出しており、流れ用凹部1bと枝凹部1cとで、半導体素子2の底面面積の略全域をカバーしている。   Further, in order to further improve the wet spreading property of the molten solder, the flow recess 1b formed on the surface of the substrate 1 is extended from one end of the semiconductor element 2 to the other end (in FIG. 6, the semiconductor element 2). A plurality of branch recesses 1c may be formed obliquely from the flow recess 1b. The branch recess 1 c extends from the flow recess 1 b toward the other side of the semiconductor element 2, and the flow recess 1 b and the branch recess 1 c cover substantially the entire bottom surface area of the semiconductor element 2. .

このように、流れ用凹部1bに加えてさらに複数の枝凹部1cを形成することで、図7に示すように、はんだが半導体素子2の底面全域に濡れ広がることが、さらに容易となって、はんだ内におけるボイド発生を確実に抑えることができる。
なお、前記流れ用凹部1b及び枝凹部1cの底面高さを、場所によって変化させることで、はんだの流れ方向及び量を制御することが可能である。
また、流れ用凹部1b及び枝凹部1cは基板1表面に対して凹形状となっているが、基板1表面に凸形状のスリット部を形成しても、同様にはんだの濡れ広がり性を向上させることが可能である。
Thus, by forming a plurality of branch recesses 1c in addition to the flow recesses 1b, as shown in FIG. 7, it becomes even easier for the solder to spread over the entire bottom surface of the semiconductor element 2, Generation of voids in the solder can be reliably suppressed.
Note that the flow direction and amount of solder can be controlled by changing the bottom surface height of the flow recess 1b and the branch recess 1c depending on the location.
The flow recess 1b and the branch recess 1c have a concave shape with respect to the surface of the substrate 1, but even if a convex slit portion is formed on the surface of the substrate 1, the wettability of the solder is similarly improved. It is possible.

また、半導体素子2を固定テープ5を介して基板1に熱圧着し、固定テープ5の厚み分の隙間に、毛細管現象によってはんだを流入させる構成の場合、固形はんだ13を半導体素子2に近接させて配置する他、半導体素子2と基板1との間に、直接溶融はんだを注入することもできる。   Further, in the case of a configuration in which the semiconductor element 2 is thermocompression bonded to the substrate 1 via the fixing tape 5 and the solder flows into the gap corresponding to the thickness of the fixing tape 5 by capillary action, the solid solder 13 is brought close to the semiconductor element 2. In addition, the molten solder can be directly injected between the semiconductor element 2 and the substrate 1.

例えば、図8(a)に示すように、半導体素子2を、固定テープ5を介して基板1に熱圧着した後、図8(b)に示すように、半導体素子2と基板1との間の空間に溶融はんだ8を注入すると、図8(c)に示すように、溶融はんだが毛細管現象により空間全体に充填される。   For example, as shown in FIG. 8A, after the semiconductor element 2 is thermocompression bonded to the substrate 1 via the fixing tape 5, the gap between the semiconductor element 2 and the substrate 1 is obtained as shown in FIG. When the molten solder 8 is injected into this space, as shown in FIG. 8C, the molten solder is filled into the entire space by capillary action.

このように、溶融はんだを半導体素子2と基板1との間の空間に注入するようにした場合も、半導体素子2の基板1に対する位置決め用の治具を用いたり、基板1と半導体素子2との間のはんだ注入用の空間を保持するための機構を特別に設けたりすることなく、半導体素子2の位置・傾き、及びはんだ厚を高い精度で制御しながらはんだ接合を行って半導体素子2を実装することができるとともに、低コスト化を図ることができる。   As described above, even when molten solder is injected into the space between the semiconductor element 2 and the substrate 1, a jig for positioning the semiconductor element 2 with respect to the substrate 1 is used, or the substrate 1, the semiconductor element 2, The semiconductor element 2 is formed by performing solder bonding while controlling the position / inclination of the semiconductor element 2 and the solder thickness with high accuracy without providing a special mechanism for maintaining the space for solder injection between the two. While being able to mount, cost reduction can be achieved.

本発明の第一の実施形態における半導体素子実装方法を示す図である。It is a figure which shows the semiconductor element mounting method in 1st embodiment of this invention. 第一の実施形態における半導体素子実装方法のフローを示す図である。It is a figure which shows the flow of the semiconductor element mounting method in 1st embodiment. 第一の実施形態において、半導体素子と基板との接合に加えて基板と放熱板との接合をも行う際の半導体素子実装方法を示す図である。In 1st embodiment, in addition to joining of a semiconductor element and a board | substrate, it is a figure which shows the semiconductor element mounting method at the time of also joining a board | substrate and a heat sink. 本発明の第二の実施形態における半導体素子実装方法を示す図である。It is a figure which shows the semiconductor element mounting method in 2nd embodiment of this invention. 本発明の第二の実施形態において、はんだの流れを制御する凹部を形成した基板を示す図である。In 2nd embodiment of this invention, it is a figure which shows the board | substrate in which the recessed part which controls the flow of a solder was formed. 本発明の第二の実施形態において、はんだの流れを制御する凹部として流れ用凹部に加えて複数の枝凹部を形成した基板を示す平面図である。In 2nd embodiment of this invention, it is a top view which shows the board | substrate which formed the several branch recessed part in addition to the recessed part for flow as a recessed part which controls the flow of solder. 図7に示す基板における溶融はんだの流れを示す図である。It is a figure which shows the flow of the molten solder in the board | substrate shown in FIG. 基板と半導体素子との間に溶融はんだを注入する半導体素子実装方法を示す図である。It is a figure which shows the semiconductor element mounting method which inject | pours molten solder between a board | substrate and a semiconductor element. 従来の半導体素子実装方法に用いられていた治具を示す側面断面図である。It is side surface sectional drawing which shows the jig | tool used for the conventional semiconductor element mounting method. 半導体素子が傾いた状態で基板に実装された様子を示す側面断面図である。It is side surface sectional drawing which shows a mode that the semiconductor element was mounted in the board | substrate in the inclined state.

符号の説明Explanation of symbols

1 基板
2 半導体素子
3 はんだ箔
5 固定テープ
6 放熱板
DESCRIPTION OF SYMBOLS 1 Board | substrate 2 Semiconductor element 3 Solder foil 5 Fixing tape 6 Heat sink

Claims (3)

半導体素子を、はんだ接合により基板に実装する半導体素子実装方法であって、
熱硬化性樹脂製のテープ部材が貼着された基板上にはんだ箔を介して半導体素子をセットし、テープ部材により半導体素子の実装位置を仮固定する工程と、
セットした半導体素子を基板に対して熱圧着することで、テープ部材をはんだ箔厚まで押しつぶすとともに熱硬化させる工程と、
リフローにて半導体素子と基板とをはんだ接合する工程と、
を備えることを特徴とする半導体素子実装方法。
A semiconductor element mounting method for mounting a semiconductor element on a substrate by solder bonding,
Setting a semiconductor element via a solder foil on a substrate on which a thermosetting resin tape member is adhered, temporarily fixing the mounting position of the semiconductor element by the tape member;
By thermocompression bonding the set semiconductor element to the substrate, the process of crushing the tape member to the thickness of the solder foil and thermosetting,
A step of soldering the semiconductor element and the substrate by reflow;
A method for mounting a semiconductor element, comprising:
半導体素子を、はんだ接合により基板に実装する半導体素子実装方法であって、
熱硬化性樹脂製のテープ部材が貼着された基板上に半導体素子をセットして、テープ部材により半導体素子の実装位置を仮固定する工程と、
基板上における半導体素子の近接位置に固形はんだを載置する工程と、
リフローにて半導体素子と基板とをはんだ接合する工程と、
を備えることを特徴とする半導体素子実装方法。
A semiconductor element mounting method for mounting a semiconductor element on a substrate by solder bonding,
Setting a semiconductor element on a substrate to which a tape member made of a thermosetting resin is attached, and temporarily fixing the mounting position of the semiconductor element by the tape member;
A step of placing solid solder on the substrate in the vicinity of the semiconductor element;
A step of soldering the semiconductor element and the substrate by reflow;
A method for mounting a semiconductor element, comprising:
前記基板表面には、リフロー時に溶融したはんだの流れ方向を制御するための凹凸部が形成されていることを特徴とする請求項2に記載の半導体素子実装方法。
3. The semiconductor element mounting method according to claim 2, wherein an uneven portion for controlling a flow direction of solder melted during reflow is formed on the surface of the substrate.
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