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JP4039490B2 - Ｉ／ｃチップ上にボンディング・パッドを形成する方法および得られる構造 - Google Patents

Ｉ／ｃチップ上にボンディング・パッドを形成する方法および得られる構造 Download PDF

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JP4039490B2
JP4039490B2 JP2004269142A JP2004269142A JP4039490B2 JP 4039490 B2 JP4039490 B2 JP 4039490B2 JP 2004269142 A JP2004269142 A JP 2004269142A JP 2004269142 A JP2004269142 A JP 2004269142A JP 4039490 B2 JP4039490 B2 JP 4039490B2
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Japan
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layer
forming
chip
opening
gold
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JP2004269142A
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JP2005094013A (ja
Inventor
ジュリー・シー・ビッグズ
テンジャン・チェン
デビッド・イー・エイシュタッド
リサ・エー・ファンチ
ジョナサン・エイチ・グリフィス
ランドルフ・エフ・ナー
サラ・エイチ・ニッカーボッカー
ケビン・エス・ペトラーカ
ロジャー・エー・クオン
ウォフルガング・ソーター
カマレシュ・ケー・スリバスタバ
リチャード・ピー・ボラント
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International Business Machines Corp
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International Business Machines Corp
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Description

本発明は、一般に集積回路（Ｉ／Ｃ）チップの製造に関し、より詳細には、ワイヤ・ボンディングされたＩ／Ｃチップを形成する技術および得られる構造に関する。
当技術分野ではワイヤ・ボンディングはよく知られており、チップとチップ・キャリアを相互接続するのに広く用いられている。従来より、金ワイヤがアルミニウム・パッドにボンディングされる。この方法にはいくつかの制限がある。金とアルミニウムの間に形成された合金により、ボンディング部の信頼性が低くなることがある。さらに、異種金属をボンディングすることによって、ボンディング・プロセスの堅固さが損なわれる。最新のＣＭＯＳ技術では、銅メタライゼーションおよび低誘電率誘電体、例えば、ＦＳＧ（フッ化石英ガラス）、ＳｉＬＫ（米国ダウ・ケミカル社（Dow Chemical）のポリアリーレンエーテル）が用いられ、さらに進んだ応用例では、多孔質の極めて脆弱な材料が用いられる。この段階をバック・エンド・ライン（ＢＥＯＬ）と称することがある。ＢＥＯＬ回路構造は弾性率が小さく、圧力による損傷を受けやすい。通常は酸化物層で覆われている上部アルミニウム表面は、テスト・プローブとパッド金属との間で良好な接点を形成するために除去しなければならない。このプローブの動きを、「スクラビング」または「プラウイング（plowing）」と呼ぶ。
米国特許第５，４８６，２８２号 米国特許第５，５３６，３８８号 ＵＳＰ５８８５８９１ ＵＳＰ６０７７７６６ 米国特許出願公開６３７６３７１ 米国特許出願公開６３８７７９３
したがって、このチップは、機械的な損傷を受ける可能性がある。テスト・プローブとの接触抵抗を小さくするためにスクラブする必要がないＩ／Ｏパッドを設けることが極めて望ましい。現在、上部アルミニウムに「強く当てる（plow）」必要があるので、パッド・サイズは極めて大きくしなければならない。このため、比較的Ｉ／Ｏ数が多いチップ設計は制約を受けるか、あるいはチップ・サイズが大きくなる。プローブ区域が大きな損傷を受けてボンディングに使用できなくなることがあるので、しばしば、パッド・サイズは、ボンディングに必要なサイズの倍になる。
集積回路（Ｉ／Ｃ）チップ内にワイヤ・ボンド構造を形成する方法は、ワイヤ・ボンドに取り付ける導電パッドを有し、かつこのワイヤ・ボンド用のパッドの上にある少なくとも１つの誘電体材料層を備えたＩ／Ｃチップを提供するステップと、次いで、前記少なくとも１つの誘電体材料層を貫通する開口を形成して、前記ワイヤ・ボンド用の前記パッドの一部を露出させるステップと、その後、前記ワイヤ・ボンド用の前記パッドの前記露出表面上および前記誘電体材料層中の前記開口の表面上に少なくとも第１導電層を形成するステップと、次いで、前記第１導電層上にシード層を形成するステップと、その後、前記シード層の上にフォトレジスト材料を塗布するステップと、前記フォトレジスト層を露光し現像して、前記誘電体材料中の前記開口を取り囲む前記シード層の表面を露出させるステップと、この露出したシード層を除去するステップと、前記開口内の前記フォトレジスト材料を除去して、その下のシード層を露出させるステップと、次いで、前記開口内の前記シード層上に少なくとも１つの導電材料層をメッキするステップと、前記開口の周りの前記誘電体層上の導電材料からなる前記第１導電層の残りの部分を除去するステップとを含む。本発明は、これによって得られた構造も含む。
次に、図面を参照する。まず図１では、ワイヤ・ボンド用パッドを形成する製造段階におけるＩ／Ｃチップ１０の一部が示されている。図には、チップのいくつかの最上部層およびパッド区域の半分だけを示す。また、本明細書で説明する方法は、ウエハ・レベルで実施される。この段階をバック・エンド・ライン（ＢＥＯＬ）と称することがある。チップ１０は、一般に厚さ約０．５μｍのＳｉＯ２またはその他の誘電体層１２と、その上に、一般に厚さ約０．５μｍのＳｉ３Ｎ４層１４を含む。層１４上に、一般に厚さ１〜２μｍのアルミニウム層１６を被着させる。このアルミニウム層１６は、ＳｉＯ２層１２およびＳｉ３Ｎ４層１４中の開口２０を貫通して延びる延長部１８を有する。Ｓｉ３Ｎ４層およびアルミニウム層１６上に、一般に厚さ約０．５μｍのＳｉＯ２またはその他の別の誘電体材料層２２を被着させ、ＳｉＯ２層２２上に、一般に厚さ約０．５μｍの別のＳｉ３Ｎ４層２４を被着させる。Ｓｉ３Ｎ４層２４の上に、一般に厚さ約６μｍの誘電体材料層、好ましくはポリイミド、より好ましくは感光性ポリイミド３０を被着させ、ポリイミド３０、Ｓｉ３Ｎ４層２４、およびＳｉＯ２層２２を貫通して開口３２を形成する。このポリイミド３０が感光性である場合、好ましくは、従来方式の露光および現像技術で開口３２を形成する。このポリイミドが感光性でない場合、好ましくは、レーザおよびマスクを使用する方法で開口３２を形成する。前に示したように、上記は、Ｉ／Ｃチップ１０の一部の形成段階を示し、この時点で、本発明に従って形成するワイヤ・ボンド用パッドを設ける準備が整っている。この時点までのチップのプロセスは従来方式で行うことができるので、このようなプロセスを詳細に説明する必要はない。
図２〜図８に、本発明によるワイヤ・ボンド用パッドを形成する様々なステップを示す。次に図２を参照すると、当業者には周知の技術によって、ポリイミド層３０上、ならびにアルミニウム層１６の露出表面および開口３２の側壁上を含む開口３２内に、ＴａＮ／Ｔａ層３６および銅層３８をスパッタにより被着させる。このスパッタリング・プロセスは従来方式のものであり、ＴａＮを約１００Å〜８００Åで最初に被着させ、次いで、Ｔａをやはり約１００Å〜８００Åで被着させてＴａＮ／Ｔａ層３６を形成し、次いで、（約１５００Å〜５０００Åで）銅層３８を形成する。これから説明するように、この銅は、金属を電着するためのシード層として働くことになる。また、ＴａＮ／Ｔａのスパッタ被着プロセス中に、ポリイミド３０の上面を炭化処理して、炭素質材料の薄い層４０を形成すると考えられる。この炭素質材料は、（ポリイミド自体とは逆に）導電性なので、これから説明するように、電流を印加すると、この炭素質材料により、層３６および３８に導電性が付与されることになる。
次に図３を参照すると、銅層３８の上に一般に厚さ約０．５〜３μｍのフォトレジスト４４が塗布され、従来方式で光によるパターン形成および現像が行われて、開口３２内にあるものを除きすべての銅層３８が露出する。ポジ型またはネガ型のいずれのフォトレジストも使用することができるが、シード層である銅と良好に機能するので、ポジ型が好ましい。
次に図４を参照すると、好ましくは電気エッチングによって、露出した銅のシード層が除去される。これは従来方式のプロセスであり、このための技術が、例えば、ダッタ（Datta）らの米国特許第５，４８６，２８２号およびディナン（Dinan）らの米国特許第５，５３６，３８８号などの米国特許に示されている。
強塩基など従来方式のプロセスによって開口３２中のフォトレジストを除去して、図５に示す構造を生成する。この構造では、銅のシード層３８が開口３２内にのみ残されている。
次に図６を参照すると、開口３２内の露出した銅のシード層３８上にニッケル層４８、次いで金層５０を電気メッキする。この電気メッキ・プロセスは従来方式のものであり、ＴａＮ／Ｔａ層３６、炭素質層４０、および導電体として存在する銅層３８を利用する。このように、ポリイミド３０の表面を炭化処理すると、電気メッキするのに有益なプラスの効果が得られる。電気メッキ法または電気化学付着法は、ウエハまたは基板上に金属を被着させるのにこの業界で広く用いられている。ニッケルまたは金のメッキ漕内でウエハ表面にカソード電流を印加する。メッキ時間および印加電流に基づいて、メッキする金属の量を制御する。ニッケルは、厚さ約０．２〜２ミクロンでメッキし、金は、厚さ約０．２〜１ミクロンでメッキする。このメッキ処理は、銅層３８上でのみ行われ、ＴａＮ／Ｔａ層３６上では行われない。また、好ましくは、金のメッキ処理は、ニッケルのメッキ処理の直後に行い、それによって起こり得るニッケルの酸化を防ぐ。このメッキ処理は、この構成が図６に示すものに達した時点で終了する。こうすると、開口３２を取り囲むポリイミド３０の表面には最小限のメッキしか上にのらない。こうすると、図６でわかるように、開口３２の側壁ならびに底部を含む開口３２中に、ＴａＮ／Ｔａ／Ｃｕ／Ｎｉ／Ａｕからなる増大したボンディング・パッドが得られる。したがって、開口３２中で露出させた元のアルミニウム・ボンディング・パッド１６のサイズを９２ミクロン×４８ミクロンと仮定すると、この開口の側壁を利用することによって、元のボンド用パッドの導電面積が３０％以上、例えば３８％増える。
次に図７を参照すると、プラズマ・エッチングによって、残りのＴａＮ／Ｔａ層および残りの炭素質層４０を除去する。標準のエッチング装置を用いてＣＦ４ベースのプラズマ中でＴａＮ／Ｔａ層３６を除去し、酸素プラズマ中で炭素質層４０を除去する。この時点で、このチップは、図８に示すように、金ボール・ボンド５２およびワイヤ５４を受け入れる準備が整っている。この金ボンドは、当技術分野で一般に行われているように、金ワイヤ５４を加熱することによって形成される金ボール５２からなる。好ましくは、このボンディング処理は、ワイヤ５４およびボール５２をボンディング・パッドに押しつけながら、超音波技術によって行う。こうすると、図９および図１０に示すように、ワイヤ５４がニッケル／金層４８の金に、強力かつ電気的に効率よく結合する。この説明では、図１０からわかるように、一方の側壁しか金の金属で覆われていない。理想的には、ボンディング表面を最大にするためにすべての側壁を覆う。
本発明によるＩ／Ｃチップ上のワイヤ・ボンド接続部を形成するステップを示す概略図である。 本発明によるＩ／Ｃチップ上のワイヤ・ボンド接続部を形成するステップを示す概略図である。 本発明によるＩ／Ｃチップ上のワイヤ・ボンド接続部を形成するステップを示す概略図である。 本発明によるＩ／Ｃチップ上のワイヤ・ボンド接続部を形成するステップを示す概略図である。 本発明によるＩ／Ｃチップ上のワイヤ・ボンド接続部を形成するステップを示す概略図である。 本発明によるＩ／Ｃチップ上のワイヤ・ボンド接続部を形成するステップを示す概略図である。 本発明によるＩ／Ｃチップ上のワイヤ・ボンド接続部を形成するステップを示す概略図である。 本発明によるＩ／Ｃチップ上のワイヤ・ボンド接続部を形成するステップを示す概略図である。 メッキしたニッケル／金ワイヤ・ボンド用パッドを示す顕微鏡写真である。 ニッケル／金ワイヤ・ボンド用パッドの側壁を示す顕微鏡写真である。
符号の説明
１０ Ｉ／Ｃチップ
１２ ＳｉＯ２層
１４ Ｓｉ３Ｎ４層
１６ アルミニウム層
１８ 延長部
２０ 開口
２２ ＳｉＯ２層
２４ Ｓｉ３Ｎ４層
３０ 感光性ポリイミド層
３２ 開口
３６ ＴａＮ／Ｔａ層
３８ 銅層
４０ 炭素質材料層
４４ フォトレジスト
４８ ニッケル層
５０ 金層
５２ 金ボール・ボンド
５４ 金ワイヤ

Claims (11)

  1. Ｉ／Ｃチップ上にワイヤ・ボンド構造を形成する方法であって、
    （１）アルミニウム・パッドを設けるステップと、
    （２）前記アルミニウム・パッドを覆って誘電体材料層を備えるステップと、
    （３）前記誘電体材料層を貫通して、前記アルミニウム・パッドの表面の少なくとも一部が露出するように開口を形成するステップと、
    （４）露出されたアルミニウム・パッドの表面上、前記開口の内側面上、及び前記誘電体材料層上に第１導電材料層を形成するステップと、
    （５）前記第１導電材料層上にメッキ用のシード層を形成するステップと、
    （６）前記シード層の上にフォトレジスト材料を塗布し、該フォトレジスト材料を露光し、次いで現像して、前記誘電体材料層の上表面上の前記シード層を露出させるステップと、
    （７）露出されたシード層を除去するステップと、
    （８）前記フォトレジスト材料を除去して、該フォトレジスト材料の下のシード層を露出させるステップと、
    （９）前記露出されたシード層上に、ニッケルを０．２〜２ミクロンの厚さになるようにメッキし、得られたニッケル層上に、金を０．２〜１ミクロンの厚さになるようにめっきして、前記開口の内側面及び底部からなる凹形状のボンディング・パッドを形成するステップと、
    （１０）前記ボンディング・パッドに、金ワイヤのボールが、前記凹形状内部に収納されて、前記ボンディング・パッドの内側面及び底部に接し且つその上面が前記ボンディング・パッドの上端以下の位置になるように、金ワイヤをボンディングするステップと、
    を含む方法。
  2. 前記ステップ（２）がＳｉＯ２層を形成するステップ、該ＳｉＯ２層上にＳｉ３Ｎ４層を形成するステップ、及び該Ｓｉ３Ｎ４層上に感光性ポリイミド層を形成するステップを含む、請求項１記載の方法。
  3. 前記ステップ（３）が、前記感光性ポリイミドをパターニングするステップを含む、請求項１または２記載の方法。
  4. 前記ステップ（４）がＴａＮをスパッタするステップ、次いで、得られたＴａＮ層上にＴａをスパッタするステップを含む、請求項１〜３のいずれか１項記載の方法。
  5. 前記ＴａＮ及びＴａのスパッタプロセス中に、前記感光性ポリイミドの表面が炭化されて、炭素質材料の薄い層が形成される、請求項４記載の方法。
  6. 前記ステップ（５）が、銅をスパッタするステップを含む請求項１〜５のいずれか１項記載の方法。
  7. ワイヤ・ボンド接続部を備えるＩＣチップにおいて、ボンディングされた金ワイヤのボールが、誘電体層中の開口部であって、その内側壁及び底部に導電材料層を備え且つ該底部がその下部に備えられたアルミニウム・パッドと接している、開口部に収納されて、前記ボンディング・パッドの内側面及び底部に接し且つその上面が前記ボンディング・パッドの上端以下の位置に在ることを特徴とするＩ／Ｃチップ。
  8. 前記導電材料層が、０．２〜１ミクロンの厚さの金層及びその下の０．２〜２ミクロンの厚さのニッケル層を含む、請求項７に記載のＩ／Ｃチップ。
  9. 前記ニッケル層が、銅層、該銅層の下のＴａ層、及び該Ｔａ層の下のＴａＮ層を介して、前記アルミニウム・パッドに接続されている、請求項８に記載のＩ／Ｃチップ。
  10. 前記誘電体層が、ＳｉＯ２層、該ＳｉＯ２層上のＳｉ３Ｎ４層、及び該Ｓｉ３Ｎ４層上のポリイミド層からなる請求項９記載のＩ／Ｃチップ。
  11. 前記ポリイミド層と前記Ｔａ層の間に炭素質材料の薄い層をさらに備える請求項１０に記載のＩ／Ｃチップ。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6715663B2 (en) * 2002-01-16 2004-04-06 Intel Corporation Wire-bond process flow for copper metal-six, structures achieved thereby, and testing method
US7005752B2 (en) * 2003-10-20 2006-02-28 Texas Instruments Incorporated Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion
US20050167837A1 (en) * 2004-01-21 2005-08-04 International Business Machines Corporation Device with area array pads for test probing
DE102005035772A1 (de) * 2005-07-29 2007-02-01 Advanced Micro Devices, Inc., Sunnyvale Technik zum effizienten Strukturieren einer Höckerunterseitenmetallisierungsschicht unter Anwendung eines Trockenätzprozesses
US8308053B2 (en) * 2005-08-31 2012-11-13 Micron Technology, Inc. Microfeature workpieces having alloyed conductive structures, and associated methods
JP4793006B2 (ja) * 2006-02-09 2011-10-12 ソニー株式会社 半導体装置及びその製造方法
DE102006036798B4 (de) * 2006-08-07 2013-08-29 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zum Herstellen
JP2008198916A (ja) * 2007-02-15 2008-08-28 Spansion Llc 半導体装置及びその製造方法
US7939949B2 (en) * 2007-09-27 2011-05-10 Micron Technology, Inc. Semiconductor device with copper wirebond sites and methods of making same
DE102007063268A1 (de) * 2007-12-31 2009-07-09 Advanced Micro Devices, Inc., Sunnyvale Drahtverbindung mit aluminiumfreien Metallisierungsschichten durch Oberflächenkonditionierung
JP5401817B2 (ja) * 2008-03-25 2014-01-29 富士通セミコンダクター株式会社 半導体装置の製造方法及び半導体装置
EP2263078B1 (en) * 2008-03-31 2015-05-13 Nxp B.V. A sensor chip and a method of manufacturing the same
DE102017106410A1 (de) * 2017-03-24 2018-09-27 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines optoelektronischen Bauelements und optoelektronisches Bauelement

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0286138A (ja) 1988-09-22 1990-03-27 Hitachi Ltd 半導体装置
JPH08293522A (ja) 1995-04-24 1996-11-05 Mitsubishi Materials Corp 半導体装置の耐熱電極
JP3413020B2 (ja) * 1996-07-17 2003-06-03 株式会社東芝 半導体装置の製造方法
US6153519A (en) * 1997-03-31 2000-11-28 Motorola, Inc. Method of forming a barrier layer
JP2000091338A (ja) 1998-09-16 2000-03-31 Seiko Epson Corp 半導体装置及びその製造方法
JP2000299337A (ja) * 1999-04-13 2000-10-24 Fujitsu Ltd 半導体装置及びその製造方法
US6077766A (en) * 1999-06-25 2000-06-20 International Business Machines Corporation Variable thickness pads on a substrate surface
JP2001196414A (ja) 2000-01-12 2001-07-19 Seiko Epson Corp 半導体装置、その製造方法および回路基板並びに電子機器
US6387793B1 (en) * 2000-03-09 2002-05-14 Hrl Laboratories, Llc Method for manufacturing precision electroplated solder bumps
US6620720B1 (en) * 2000-04-10 2003-09-16 Agere Systems Inc Interconnections to copper IC's
US6534863B2 (en) * 2001-02-09 2003-03-18 International Business Machines Corporation Common ball-limiting metallurgy for I/O sites
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US6649507B1 (en) * 2001-06-18 2003-11-18 Taiwan Semiconductor Manufacturing Company Dual layer photoresist method for fabricating a mushroom bumping plating structure
US6706622B1 (en) * 2001-09-07 2004-03-16 Lsi Logic Corporation Bonding pad interface
US6762122B2 (en) * 2001-09-27 2004-07-13 Unitivie International Limited Methods of forming metallurgy structures for wire and solder bonding

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