JP4035804B2 - High frequency semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a high-frequency semiconductor integrated circuit device, and more particularly to a high-frequency semiconductor integrated circuit device characterized by a configuration of a ground plane for obtaining high-frequency characteristics of a semiconductor integrated circuit device used at a high frequency of 10 GHz or more with good reproducibility. .
[0002]
[Prior art]
In recent years, with the improvement in performance of compound semiconductor devices, three-terminal elements using compound semiconductors can be applied to oscillation, amplification, frequency conversion, etc., even in high frequency bands that were not possible in the past. became.
In order to further spread communication devices using such high-performance elements, further reduction in manufacturing cost is required.
[0003]
A conventional high-frequency semiconductor integrated circuit device will now be described with reference to FIGS.
FIG. 7 is a schematic plan view of a conventional high-frequency semiconductor integrated circuit device. For example, GaAs with HEMT (High Electron Mobility Transistor) and MESFET (Schottky Barrier Gate Field Effect Transistor) formed therein. A wiring layer 32 formed on the surface of a high-frequency semiconductor integrated circuit substrate 31 such as a substrate and an Au wire 35 connected to a microstrip line 34 formed on a ceramic substrate 33 by wire bonding are connected to an external circuit. ing.
[0004]
However, when the Au wire 35 used for such a connection is considered as a transmission line, the characteristic impedance changes depending on the shape requirements such as the length, diameter, and distance to the ground of the Au wire 35. There is a problem that characteristics cannot be obtained. In order to solve such problems, a flip chip bonding method using conductive pillars or bumps has been proposed. Such an improved high-frequency semiconductor integrated circuit device will be described with reference to FIG. To do.
[0005]
FIG. 8A is a schematic cross-sectional view of a conventional improved semiconductor integrated circuit device, and FIG. 8B is a diagram of a conventional improved semiconductor integrated circuit device. It is a schematic exploded perspective view.
As is apparent from the drawing, the metal pillar 42 formed on the high-frequency semiconductor integrated circuit substrate 41 is used for pressure bonding to the ceramic substrate 43 provided with an external circuit. In this case, the metal pillar 42 connects the wiring layer 45 formed on the high-frequency semiconductor integrated circuit device 41 and the external connection wiring layer 46 provided on the ceramic substrate 43, and a conductive ground plane provided on the surface of the ceramic substrate 43. 44 is connected.
[0006]
Thus, since the shape of the metal pillar 42 is more stable than that of the metal wire 35, the high-frequency transmission line using the metal pillar 42 instead of the Au wire 35 has good high-frequency characteristics and reproducibility. Good and good high frequency characteristics can be obtained.
[0007]
[Problems to be solved by the invention]
However, in the case of a high-frequency transmission line using such metal pillars, there is usually a circuit board that constitutes an external circuit above the high-frequency semiconductor integrated circuit board, and in particular, a ground plane on the surface of the circuit board. Is present, the high-frequency characteristics change depending on the distance d between the substrates facing each other. In order to obtain good high-frequency characteristics with good reproducibility, it is necessary to precisely control the distance d between the substrates. .
[0008]
However, since the distance d between the substrates in this case varies depending on the pressure when the substrates are pressure-bonded, the number of metal pillars, or the physical characteristics of the metal pillars such as diameter and rigidity, the distance d is reproducible. It was difficult to get well.
Note that the physical characteristics of the metal pillar change due to the influence of the grain boundary of the crystal constituting the metal pillar or the residual component of the plating solution.
[0009]
Therefore, even if the high frequency characteristic of the transmission line portion by the metal pillar is stable, it is difficult to precisely control the distance d between the substrates. Therefore, even if the flip chip bonding method is used, the high frequency characteristic is reproducible. It was difficult to get well. If the substrates are not bonded to each other, the high-frequency characteristics as originally designed cannot be realized. Therefore, it is impossible to test the high-frequency characteristics in the state before bonding, and the determination of non-defective / defective products is not possible. It was impossible only after the combining process.
[0010]
Accordingly, an object of the present invention is to obtain a good high frequency characteristic with good reproducibility regardless of a change in the distance between substrates when a conductive pillar is used in a transmission line.
[0011]
[Means for Solving the Problems]
FIG. 1 is an explanatory diagram of the principle configuration of the present invention. Means for solving the problems in the present invention will be described with reference to FIG.
FIG. 1 is a schematic cross-sectional view of a high-frequency semiconductor integrated circuit device.
Refer to FIG. 1. (1) In the high-frequency semiconductor integrated circuit device according to the present invention, a plurality of first high-frequency semiconductor integrated circuit substrates 1 are provided with a plurality of firsts having the same height in a part of the plurality of conductive pillars. A ground surface 3 is provided which is supported by the conductive pillar 2 and located at a level different from the facing surface of the circuit substrate 4 facing the high-frequency semiconductor integrated circuit substrate 1.
[0012]
In this manner, the ground surface 3 supported by the plurality of first conductive pillars 2 having the same height is provided above the surface of the high-frequency semiconductor integrated circuit substrate 1 independently of the opposing surface of the circuit substrate 4. As a result, the distance between the surface of the high-frequency semiconductor integrated circuit substrate 1 and the ground surface 3 is not affected by pressure contact or the like, so that high-frequency characteristics as designed can be realized with good reproducibility.
[0013]
(2) Further, the present invention is characterized in that, in the above (1), the ground surface 3 is opposed to the surface of the high-frequency semiconductor integrated circuit substrate 1 via a gap.
(3) Further, according to the present invention, in the above (1) or (2), the high-frequency semiconductor integrated circuit substrate 1 and the circuit substrate 4 are joined with the remaining second conductive pillar 5 among the conductive pillars. It is characterized by being used.
[0014]
As described above, the high-frequency semiconductor integrated circuit substrate 1 and the circuit substrate 4 are also bonded using the second conductive pillar 5, whereby the high-frequency characteristics of the transmission line portion can be well maintained with good reproducibility.
The second conductive pillar 5 is used for electrical connection, and part of the second conductive pillar 5 is used to stably support the bonding between the high-frequency semiconductor integrated circuit board 1 and the circuit board 4 in a balanced manner. .
[0015]
(4) Further, the present invention, the above (3) odor Te, height and the height of the second conductive pillar 5 of the first conductive pillar 2 are the same, and the ground plane 3 of the circuit board 4 A concave portion is formed in a region facing the surface.
[0016]
In this way, the first conductive pillar 2 and the second conductive pillar 5 can be simultaneously formed by making the first conductive pillar 2 and the second conductive pillar 5 the same height. This improves throughput.
In this case, in order to prevent structural interference between the facing surface of the circuit board 4 and the ground surface 3, it is necessary to form a recess in a region facing the ground surface 3 of the circuit board 4.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Here, the high-frequency semiconductor integrated circuit device according to the first embodiment of the present invention will be described with reference to FIGS. 2 to 4. First, the first embodiment of the present invention will be described with reference to FIGS. The manufacturing process of the high-frequency semiconductor integrated circuit device of the form will be described.
Referring to FIG. 2A, first, a high frequency semiconductor integrated circuit substrate in which HEMT, MESFET, etc. are formed inside, and a signal input / output pad portion (not shown) is provided on the surface via an insulating layer. After selectively forming an Au plating base layer (not shown) at a predetermined position including the 11 pad portions by vapor deposition, a photoresist having a thickness of, for example, 20 μm is applied to the entire surface, and exposure and development are performed. Thus, a resist pattern 12 having a support pillar opening 13 having a diameter of, for example, 20 μm is formed.
In this case, the number of support pillar openings 13 is provided at a density of about 10 to 50 / mm ² , for example.
[0018]
Next, referring to FIG. 2B, by performing Au plating using an electrolytic plating method, an Au plating layer is selectively provided in the support pillar opening 13 to form the support pillar 14.
In this case, since the deposition rate of the Au plating layer depends on the opening area of the support pillar opening 13, the support pillars 14 having substantially the same height, that is, 20 μm are formed at the same time.
[0019]
Next, after depositing a thin Au layer on the entire surface, a plating base layer (not shown) is formed by patterning the signal input / output pad portion so as not to cover it, and then again electrolytically An Au ground surface 15 having a thickness of several μm, for example, 5 μm, is formed on the plated base layer by performing Au plating using a plating method.
[0020]
Next, referring to FIG. 2D, by removing the resist pattern 12 using an organic solvent or the like, an Au ground surface 15 supported by a plurality of support pillars is obtained above the surface of the high-frequency semiconductor integrated circuit substrate 11. .
[0021]
Next, referring to FIG. 3E, a resist pattern having a bonding pillar opening 17 having a diameter of 40 μm, for example, is applied to the entire surface again by applying a photoresist having a thickness of 50 μm, for example, and exposing and developing. 16 is formed.
In this case, the number of the bonding pillar openings 17 depends on the number of signal input / output pads, but includes, for example, 10 to 10 including support-dedicated pillars for performing substrate bonding in a balanced manner. It is provided with a density of about 50 / mm ² .
[0022]
Next, referring to FIG. 3 (f), Au plating is again performed using the electrolytic plating method, thereby selectively providing an Au plating layer in the bonding pillar opening 17 to form the bonding pillar 18.
[0023]
Next, see FIG. 3G. Next, the ceramic substrate 19 and the high-frequency semiconductor are made of eutectic alloy with Au constituting the bonding pillar 18 by press-bonding and heating the ceramic substrate 19 on which an external circuit is formed using a metal such as Sn. A high-frequency semiconductor integrated circuit device is completed by electrically connecting the integrated circuit substrate 11 and mechanically bonding and bonding together.
[0024]
FIG. 4 is a schematic exploded perspective view of the high-frequency semiconductor integrated circuit device according to the first embodiment of the present invention formed as described above. The support pillar 14 is formed on the surface of the high-frequency semiconductor integrated circuit substrate 11. The Au ground surface 15 is located on the center side, and the shape of the Au ground surface 15 is such that it does not cover the bonding pillar 18 located on the center side.
[0025]
Thus, in the first embodiment of the present invention, Au plating is performed so that the Au ground surface 15 located above the surface of the high-frequency semiconductor integrated circuit substrate 11 is supported by the support pillar 14 formed by Au plating. Therefore, there is no fluctuation in height due to pressure bonding or the like. Therefore, the distance between the surface of the high-frequency semiconductor integrated circuit substrate 11 and the Au ground surface 15 can be precisely controlled. Even if the distance between the surface of the integrated circuit substrate 11 and the facing surface of the ceramic substrate 19 varies, the high frequency characteristics are not affected.
[0026]
In the first embodiment of the present invention, since the Au ground surface 15 is formed independently of the ceramic substrate 19, before the ceramic substrate 19 is bonded, the high-frequency characteristics after the bonding process are obtained. An opportunity to test the same high frequency characteristics can be obtained, whereby defective products can be removed before the bonding process, and the assembly cost of the high frequency semiconductor integrated circuit device can be reduced.
[0027]
In addition, since the signal input / output is performed using the junction pillar 18 as a transmission line, the transmission line characteristics are good as in the conventional improved high-frequency semiconductor integrated circuit device shown in FIG. It can be realized with good reproducibility.
[0028]
Next, with reference to FIG. 5, the manufacturing process of the high frequency semiconductor integrated circuit device of the 2nd Embodiment of this invention is demonstrated.
5A. First, a high-frequency semiconductor integrated circuit substrate in which HEMT, MESFET, and the like are formed inside, and a signal input / output pad portion (not shown) is provided on the surface via an insulating layer. After selectively forming an Au plating base layer (not shown) at a predetermined position including the 11 pad portions by vapor deposition, a photoresist having a thickness of, for example, 20 μm is applied to the entire surface, and exposure and development are performed. As a result, a resist pillar 12 having a support pillar opening 13 with a diameter of, for example, 20 μm and a bonding pillar opening 20 with a diameter of, for example, 20 μm is formed.
[0029]
Next, referring to FIG. 5B, by performing Au plating using an electrolytic plating method, an Au plating layer is selectively provided in the support pillar opening 13 and the bonding pillar opening 20, thereby providing the support pillar 14 and bonding. The pillar 21 is formed.
In this case, since the deposition rate of the Au plating layer depends on the opening area of the pillar forming opening, the diameters of the support pillar opening 13 and the bonding pillar opening 20 are substantially the same, and are substantially the same. The height supporting pillar 14 and the joining pillar 21 are formed at the same time.
[0030]
Next, after depositing a thin Au layer on the entire surface, a plating base layer (not shown) is formed by patterning the bonding pillar 21 so as not to cover it, and then the bonding pillar 21 is formed into a resist pattern. After selectively covering with (not shown), the Au ground surface 15 having a thickness of several μm, for example, 5 μm, is formed on the plated base layer by performing Au plating again using the electrolytic plating method.
[0031]
Next, referring to FIG. 5D, after removing the resist pattern 12 using an organic solvent or the like, an external circuit is formed using a metal such as Sn, and a recess is formed in a region facing the Au grant surface 15. By pressing and heating the ceramic substrate 22, the ceramic substrate 22 and the high-frequency semiconductor integrated circuit substrate 11 are electrically connected by a eutectic alloy with Au constituting the bonding pillar 21, and mechanically bonded and pasted. By combining them, a high frequency semiconductor integrated circuit device is completed.
[0032]
As described above, in the second embodiment of the present invention, since the support pillar 14 and the joint pillar 21 are formed at the same height at the same time, it is possible to reduce the plating process, thereby improving the throughput. Can be improved.
[0033]
Next, with reference to FIG. 6, the manufacturing process of the high frequency semiconductor integrated circuit device of the 3rd Embodiment of this invention is demonstrated.
6A. First, as in the first embodiment, HEMT, MESFET, and the like are formed inside, and a signal input / output pad portion (in a predetermined pattern) is formed on the surface via an insulating layer (see FIG. 6A). After selectively forming an Au plating base layer (not shown) at a predetermined position including the pad portion of the high-frequency semiconductor integrated circuit substrate 11 provided with a not-shown), the thickness of the entire surface is, for example, Then, a 20 μm photoresist is applied, exposed and developed to form a resist pattern (not shown) having a support pillar opening (not shown) having a diameter of 20 μm, for example.
[0034]
Next, by performing Au plating using an electrolytic plating method, an Au plating layer is selectively provided in the support pillar opening to form the support pillar 14, and then the resist pattern is removed using an organic solvent or the like.
[0035]
Next, referring to FIG. 6B, an Au ground surface 24 is provided on the surface, and a planar ceramic substrate 23 that does not cover the input / output pads (not shown) is crimped and heated using a metal such as Sn. Thus, the Au grant surface 24 is bonded together by a eutectic alloy with Au constituting the support pillar 14.
[0036]
Next, referring to FIG. 6C, again, as in the steps of FIGS. 3E and 3F, a new pillar pattern 25 is formed using a new photoresist pattern (not shown), and a metal such as Sn is formed. The ceramic substrate 19 on which the external circuit is formed is pressure-bonded and heated to electrically connect the ceramic substrate 19 and the high-frequency semiconductor integrated circuit substrate 11 with a eutectic alloy with Au constituting the bonding pillar 25. Then, the high frequency semiconductor integrated circuit device is completed by mechanically bonding and bonding.
[0037]
As described above, in the third embodiment of the present invention, the Au ground surface 24 is separately formed using the ceramic substrate 23. Therefore, before the high frequency semiconductor device is fully installed, the high frequency characteristics are obtained. It becomes possible to know and to improve the final yield.
[0038]
In this case, when the ceramic substrate 23 on which the Au ground surface 24 is formed is pressure-bonded, the height of the support pillar 14 can be adjusted by adjusting the pressure at the time of pressure-bonding. Since the distance between the surface 24 and the surface of the high-frequency semiconductor integrated circuit substrate 11 can be arbitrarily changed, the high-frequency characteristics can also be arbitrarily changed.
[0039]
As mentioned above, although each embodiment of the present invention has been described, the present invention is not limited to the configuration described in each embodiment, and various modifications can be made.
For example, in the above-described first embodiment, the support pillar 14 and the Au ground surface 15 are formed in separate steps, but they may be formed at the same time, thereby reducing the number of plating steps. can do.
[0040]
For example, in the process of FIG. 2A, after the support pillar opening 13 is formed, a thin Au layer serving as a plating base layer is mask-deposited in a predetermined shape on the entire surface including the bottom surface of the support pillar opening 13. Then, by performing Au plating using an electrolytic plating method, the support pillar 14 and the Au ground surface 15 can be formed simultaneously.
In this case, the thickness of the Au ground surface 15 is larger than that of the first embodiment.
[0041]
In the third embodiment, the ceramic substrate 23 is used as the substrate for supporting the Au ground plane 24. However, the ceramic substrate 23 is selected from the GaAs substrate constituting the high-frequency semiconductor integrated circuit substrate 11 such as a silicon substrate. An etchable substrate may be used.
In the third embodiment, since the ceramic substrate 23 supporting the Au ground surface 24 is left as it is, the height of the bonding pillar 25 is increased, but the second embodiment described above. As in this embodiment, a ceramic substrate provided with a recess in a region facing the Au ground surface 24 may be used as the substrate provided with an external circuit.
[0042]
In the third embodiment, the substrate that supports the Au ground surface 24 is left as it is. However, the substrate may be removed by wet etching after pressure bonding. The planar shape of the substrate supporting 24 is not restricted, and the height of the bonding pillar 25 can be made relatively low.
[0043]
Further, when removing the substrate that supports the Au ground surface 24, a thin resist layer or SiO ₂ film may be inserted between the support substrate and the Au ground surface 24, thereby reducing the thickness. Since the support substrate can be removed in a lift-off manner by removing the resist layer or the SiO ₂ film with an organic solvent or acid, the support substrate can be easily removed.
[0044]
In the third embodiment, since a thin ground surface of several μm is assumed, a support substrate is used. However, a relatively small substrate of about 0.1 mm is used without using a support substrate. A thick Au plate may be used for direct pressure bonding to the support pillar, thereby reducing the plating step and eliminating the need for the support substrate removal step.
[0045]
In addition, when using such a relatively thick Au plate, a hole having the same diameter as the support pillar is provided at a location facing the support pillar, and the fitting between the support pillar and the hole is used. May be joined together, thereby eliminating the need for a crimping step with heating.
[0046]
In the description of each of the above embodiments, the support pillar, the bonding pillar, and the ground surface are formed by Au plating or Au plate. However, it is not always necessary to be Au plating or Au plate, and Cu plating. It is easy to use an electroplating metal such as a metal having good conductivity.
[0047]
In the description of each of the above embodiments, the high-frequency semiconductor integrated circuit substrate is described on the premise of a GaAs substrate on which a HEMT or MESFET is formed, but the device is a PIN-PD or a semiconductor laser (LD) or the like. This optical device is also applied to a high-frequency semiconductor integrated circuit substrate integrated.
[0048]
【The invention's effect】
According to the present invention, when the high-frequency semiconductor integrated circuit substrate and the ceramic substrate on which the external circuit is formed are bonded together, the ground plane independent from the ceramic substrate is previously supported by the support pillar on the high-frequency semiconductor integrated circuit substrate side. In particular, since the first and second embodiments are formed by plating, the distance between the surface of the high-frequency semiconductor integrated circuit substrate and the ground plane can be precisely controlled. Therefore, even if the distance between the high-frequency semiconductor integrated circuit substrate and the ceramic substrate varies due to pressure bonding, good high-frequency characteristics can be realized with good reproducibility, which contributes to the improvement of the manufacturing yield of the high-frequency semiconductor integrated circuit device. Rolls are big.
[0049]
In addition, the high frequency characteristics are defined by the distance between the surface of the high frequency semiconductor integrated circuit board and the ground plane, so that it is possible to test the high frequency characteristics before bonding the ceramic substrates, and thereby the stage before the bonding process. Thus, it is possible to remove defective products, which in turn greatly contributes to a reduction in assembly cost of a high-frequency semiconductor integrated circuit device and an improvement in manufacturing yield.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a basic configuration of the present invention.
FIG. 2 is an explanatory diagram of the manufacturing process up to the middle of the first embodiment of the present invention.
FIG. 3 is an explanatory diagram of the manufacturing process from FIG. 2 onward according to the first embodiment of the present invention.
FIG. 4 is a schematic exploded perspective view of the high-frequency semiconductor integrated circuit device according to the first embodiment of the present invention.
FIG. 5 is an explanatory diagram of a manufacturing process according to the second embodiment of this invention.
FIG. 6 is an explanatory diagram of the manufacturing process of the third embodiment of the present invention.
FIG. 7 is a schematic plan view of a conventional high-frequency semiconductor integrated circuit device.
FIG. 8 is an explanatory diagram of a conventional improved high-frequency semiconductor integrated circuit device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 High frequency semiconductor integrated circuit board 2 1st electroconductive pillar 3 Ground surface 4 Circuit board 5 2nd electroconductive pillar 11 High frequency semiconductor integrated circuit board 12 Resist pattern 13 Support pillar opening part 14 Support pillar 15 Au ground surface 16 Resist Pattern 17 Bonding pillar opening 18 Bonding pillar 19 Ceramic substrate 20 Bonding pillar opening 21 Bonding pillar 22 Ceramic substrate 23 Ceramic substrate 24 Au ground plane 25 Bonding pillar 31 High-frequency semiconductor integrated circuit substrate 32 Wiring layer 33 Ceramic substrate 34 Microstrip Line 35 Au wire 41 High frequency semiconductor integrated circuit board 42 Metal pillar 43 Ceramic substrate 44 Ground plane 45 Wiring layer 46 External connection wiring layer

Claims (4)

Above the high-frequency semiconductor integrated circuit surface of the substrate is supported by a plurality of first conductive pillar part of the same height of the plurality of conductive pillars, and, facing the high-frequency semiconductor integrated circuit substrate A high-frequency semiconductor integrated circuit device comprising a ground plane located at a level different from a facing surface of a circuit board. 2. The high-frequency semiconductor integrated circuit device according to claim 1, wherein the ground plane is opposed to the surface of the high-frequency semiconductor integrated circuit substrate via a gap. 3. The high-frequency semiconductor integrated circuit according to claim 1, wherein the high-frequency semiconductor integrated circuit board and the circuit board are joined by using the remaining second conductive pillar of the conductive pillars. apparatus. The height of the first conductive pillar and the height of the second conductive pillar are the same, and a recess is formed in a region facing the ground surface of the circuit board. Item 4. The high-frequency semiconductor integrated circuit device according to Item 3 .

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