JP4033962B2 - Clock generation circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock generation circuit that can be controlled even under a low voltage and that can operate accurately and reliably with little influence on noise.
[0002]
[Prior art]
A phase-locked loop (PLL) is a circuit that outputs a period synchronized with an input clock or a multiplied clock, which has been conventionally used in a wide range of fields. The operating frequency of recent microprocessors is high, and for example, it operates with a high-speed clock of several hundred MHz, so that it is indispensable to incorporate a PLL in the microprocessor.
[0003]
The conventional PLL is an analog PLL that controls the oscillation frequency by controlling the voltage of a capacitor that holds the control voltage of a voltage controlled oscillator (VCO) by a charge pump. However, the conventional analog PLL is difficult to control under a low voltage, is vulnerable to noise, and has a long lock time until the operation is stabilized. When the supply of the input clock is stopped, the transmission of the PLL is stopped. There is a problem that it takes a long time to start the operation again.
[0004]
Conventionally, various proposals have been made to solve the above-described problems. For example, in the prior art of Document 1 described below, a frequency multiplier circuit using a digital delay line is disclosed.
Reference 1: “A Portable Clock Multiplier Generating Digital CMOS Standard Cells, Michel Comber et al., IEEE Journal of Solid-State Circuits, Vol. 31, Jul.
[0005]
FIG. 8 is a block diagram showing the configuration of a conventional frequency multiplier circuit 10. In FIG. 8, 1 is a flip-flop circuit (Flip-Flop), 2 is a divider, 3 is a comparator, and 4 is a control circuit. , 6 and 7 are delay circuits. FIG. 9 is a timing chart showing the operation of the conventional frequency multiplication circuit 10 shown in FIG.
[0006]
Next, the operation will be described.
In the operation of the conventional frequency multiplication circuit 10 shown in FIG. 8, depending on the initial state of the delay time of the delay circuits 6 and 7 which are digital delay lines, it is shown between the timing T1 and the timing T2 in the timing chart of FIG. As described above, there is a possibility that a pulse is not output from the flip-flop circuit 1.
[0007]
In this case, the delay time from the rising edge (timing T1) of the input clock to the negation of the output signal M of the frequency divider 2 and the fourth pulse of the multiplied clock output signal as the output signal A of the flip-flop circuit 1 Depending on the difference in delay time from the falling time (timing T1) until the output signal M is asserted, the output signal M is asserted for one period of the input clock as shown in FIG. 9 from the timing T1 to the timing T2. There has been a problem that a state in which an accurate multiplied output signal cannot be output continues.
[0008]
Further, in the frequency multiplication circuit 10 disclosed in the above-described prior art document 1, nothing is mentioned regarding the phase synchronization between the input clock and the output signal M of the frequency divider 2, and for this reason, the PLL The function of was insufficient.
[0009]
On the other hand, there is a combination of a conventional phase synchronization circuit using a digital delay line and a frequency multiplication circuit 10 shown in FIG. 8 using a digital delay line.
[0010]
FIG. 10 is a block diagram showing a conventional clock generation circuit 15 in which a phase synchronization circuit using a digital delay line and the frequency multiplication circuit 10 shown in FIG. 8 using a digital delay line are combined. Is a frequency multiplication circuit shown in FIG. 8, 11 is a phase synchronization circuit, 12 is a digital delay line constituting the phase synchronization circuit 11, 13 is a digital counter, and 14 is a comparator.
[0011]
Next, the operation will be described.
A multiplied clock output signal (output clock) output from the frequency multiplying circuit 10 is input to the digital delay line 12 in the phase synchronization circuit 11, and a PLL output signal is output from the digital delay line 12 to the outside. The comparator 14 compares the phase of the PLL output signal with the phase of the input clock, feeds back the comparison result to the digital delay line 12, adjusts the delay between the input clock and the PLL output signal, and the phase between the two. Are matched.
[0012]
However, in the configuration of the conventional clock generation circuit 15 shown in FIG. 10, for example, when the delay time of the digital delay line 12 becomes longer than the period of the input clock, the comparator 3 in the frequency multiplication circuit 10 or the phase synchronization circuit 11 It takes a lot of time until the period or phase correction performed by the comparison result in the comparator 14 is reflected in the PLL output signal. Therefore, the correction capability for the shift of the PLL output signal due to the voltage value, the temperature value, etc. is poor. There was a problem of becoming.
[0013]
FIG. 11 is a timing chart showing the operation of the clock generation circuit 15 shown in FIG. As shown in the timing chart of FIG. 11, when the delay time in the digital delay line 12 in the phase synchronization circuit 11 is locked with a delay time twice as long as the input clock, the frequency multiplication circuit 10 in the timing T4. The comparison result output from the comparator 3 is output from the phase synchronization circuit 11 as the PLL output signal after two cycles of the input clock, counting from the timing T4. In this case, not only does the correction capability deteriorate, but there is a risk that an inaccurate PLL output signal at the timing T5 may cause an inaccurate delay correction calculation process to cause a situation where locking cannot be performed correctly.
[0014]
FIG. 12 is a block diagram showing a conventional digital delay line 12. In the figure, 17 is a plurality of delay elements constituting the digital delay line 12, and 18 is a selector for selecting one of the plurality of delay elements. is there.
For example, Reference 1 and Reference 2 “Multifrequency Zero-Jitter Delay-Locked Loop” (Avener Efendovich et al., 3 names: IEEE Journal of Solid-State Circuits, Vol. In the digital delay line 12, the selector 18 selects one of the delay elements 17 and adjusts the delay time.
[0015]
However, in such a conventional digital delay line configuration, even when the delay of the digital delay line is short, it is necessary to switch all the delay elements 17 and there is a problem that power is unnecessarily consumed.
[0016]
FIG. 13 is a block diagram showing another conventional digital delay line. As shown in the figure, in the configuration of another conventional digital delay line, in order to suppress power consumption, each delay element is selectively activated by controlling the input capture position using the control signals a and b. A desired delay time is obtained. However, in the configuration of another conventional digital delay line shown in FIG. 13, when the counter value changes during the operation of the clock generation circuit, for example, when the input position shifts from node a to node b in FIG. There is a problem that an indefinite potential is applied to the output a at the timing T8 shown in the timing chart showing the operation of the digital delay line shown in FIG.
[0017]
[Problems to be solved by the invention]
As described above, in the conventional clock generation circuit, in the digital PLL using the digital delay line, in the initial state of the digital delay line, the multiplied clock output signal that is the output signal of the frequency multiplying circuit 10 is not output accurately. Depending on the initial state of the digital delay line 12 in the phase synchronization circuit 11, the digital delay line calculated based on the comparison result in the frequency multiplication circuit 10 or the comparators 3 and 14 in the phase synchronization circuit 11 may be used. Before the change in the delay time is reflected in the PLL output signal, the next phase comparison is performed, and there is a problem that the correction capability with respect to temperature and voltage fluctuations is reduced and phase locking becomes difficult.
[0018]
In addition, switching all the elements in the digital delay line consumes wasted power, or in order to prevent this wasted power consumption, the delay time is adjusted by controlling the input capture position of the digital delay line. Then, when the counter value changes during the operation, there is a problem that a hazard is placed on the output of the digital delay line and the phase cannot be accurately locked.
[0019]
The present invention has been made to solve the above-described problems. In the clock generation circuit, when the supply of the input clock is stopped, it can be easily controlled even at a low voltage, has little influence on noise, and has a short lock time. Even so, it is an object to obtain a clock generation circuit capable of accurately operating a digital PLL capable of generating a required clock and improving performance such as jitter and accuracy.
[0020]
[Means for Solving the Problems]
In the clock generation circuit according to the present invention, the multiplier circuit outputs a clock signal having a predetermined multiplication number of the input clock signal (hereinafter referred to as input clock) (hereinafter, the clock signal output from the multiplier circuit is referred to as output clock). ) , Enter When the number of pulses of the output clock is less than a predetermined multiplication number during one cycle of the power clock, the operation of the multiplication circuit is initialized and the output clock of the desired multiplication number is reliably locked even under a low voltage. Whatever the initial state is, the output clock having a desired multiplication number can be obtained with high accuracy and reliability.
[0021]
The clock generation circuit according to the present invention includes a first delay circuit in which the multiplier circuit delays the period or phase of the output clock in stages, and a first counter that sets and controls the delay time of the first delay circuit, The counter value in the first counter is set so that the delay time of the first delay circuit becomes the minimum value when the operation of the clock generation circuit is started or when a reset signal is input, and an output clock having a desired multiplication number is set. It is obtained with high accuracy and reliability.
[0022]
In the clock generation circuit according to the present invention, the counter value of the first counter is updated only to a value such that the change in the delay time of the first delay circuit becomes the minimum value, and the pulse width of the output clock is gradually increased. Thus, an output clock having a desired multiplication number can be obtained with high accuracy and accuracy.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below.
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a clock generation circuit 20 according to Embodiment 1 of the present invention. In the figure, 21 is a phase-locked loop (hereinafter referred to as PLL), 22 is a two-phase clock generation circuit, Reference numerals 23, 24 and 37 denote inverters, 27 denotes a clock driver composed of a gate-controlled inverter, and 34, 35 and 36 denote external circuits to which the clock signal generated by the clock generation circuit 20 of the first embodiment is supplied. The clock generation circuit 20 includes a PLL 21, a two-phase clock generation circuit 22, inverters 23 and 24, and a clock driver 27.
[0028]
Next, the operation will be described.
The PLL 21 in the clock generation circuit 20 according to the first embodiment of the present invention outputs a PLL output signal (hereinafter referred to as a PLL output) as a clock signal that is four times the input clock signal (hereinafter referred to as an input clock). . This PLL output signal becomes two-phase non-overlap signals P1G and P2G by the two-phase clock generation circuit 22. The two-phase non-overlap signals P1G and P2G are supplied to the external circuits 34, 35 and 36 via the clock driver 27 of each block. Output signals P1C and P2C of the clock driver 27 are output to the external circuit 34, output signals P1B and P2B of the clock driver 27 are output to the external circuit 35, and output signals P1A and P2A of the clock driver 27 are output to the external circuit 36. Is done.
[0029]
For example, when the output state of the external circuit 34 does not change (that is, when the external circuit 34 is not operating), the output signals P1C and P2C of the clock driver are always fixed to the low level (L level) and output to the external circuit 34 Is done. When the output state of the external circuit 35 does not change (that is, when the external circuit 35 is not operating), the output signals P1B and P2B of the clock driver are always fixed to the low level (L level) and output to the external circuit 35. Is done. Similarly, when the output state of the external circuit 36 does not change (that is, when the external circuit 36 is not operating), the output signals P1A and P2A of the clock driver are always fixed to the low level (L level) and output to the external circuit 36. Is done. The PLL 21 has a function of controlling its output (hereinafter referred to as PLL output) so that the phase of the clock input and the control signal P1P that is the output of the inverter 37 coincide.
[0030]
FIG. 2 is a block diagram showing the configuration of the PLL 21 in the clock generation circuit 20 shown in FIG. 1. The PLL 21 includes a multiplication circuit 40 (hereinafter referred to as a multiplication unit 40) and a phase synchronization circuit 41 (hereinafter referred to as a phase synchronization unit 41). 2).
[0031]
Hereinafter, the multiplication unit 40 and the phase synchronization unit 41 constituting the PLL 21 will be described in detail.
The multiplier 40 has a function of generating a quadruple clock of the input clock. In the first embodiment, the multiplication unit 40 generates a quadruple clock. However, the present invention is not limited to this, and for example, a predetermined multiple clock such as a double clock, a 6 clock, or an 8 clock is used. A PLL to be generated may be used.
[0032]
Next, the operation of the multiplier 40 will be described.
FIG. 3 is a timing chart showing the operation of the PLL 21.
In the multiplication unit 40 shown in FIG. 2, the loop indicated by the thick line indicates the ring oscillator 100. The multiplier 40 outputs the quadruple clock generated by the ring oscillator 100 indicated by the bold line to the phase synchronizer 41. However, the ring oscillator 100 is forcibly set to L level while the control signal DL-ACT is negated, and is forcibly set to H level while the control signal DL-STAT is asserted. Is done.
[0033]
As shown in the timing chart of FIG. 3, the control signal DL-ACT is asserted at the rising edge of the input clock (for example, timing T10) and negated at the falling edge of the fourth pulse of the quadruple output (for example, , Timing T11).
[0034]
The digital delay line (first delay circuit) 56 is configured by connecting 96 delay elements (for example, selectors) in series, and the delay time can be adjusted in 96 stages. For example, the upper 7 bits of a 10-bit counter (first counter) 52 controls the delay time of the digital delay line 56. The initial value of the counter 52 when the control signal PLL-reset is asserted is 1, which controls the delay time of the digital delay line 56 to the minimum value. The counter 52 is incremented by one every two cycles of the input clock.
[0035]
When the phase of the rising edge of the input clock matches the phase of the falling edge of DL-OUT (that is, the input clock rising timing T13 next to the timing T12), the counter 52 stops counting up. As described above, the counter 52 can set the delay time of the digital delay line 56 gradually and gradually from the minimum value, so that the frequency divider can be used as described in the prior art without erroneously locking by three or two times. Thus, it is possible to avoid a situation in which the output signal from is continuously asserted and an accurate multiplied output signal cannot be output.
[0036]
For example, when the control signal DL-ACT is continuously asserted at the rising edge of the input clock, the multiplication circuit 40 determines that four pulses of the quadruple output are not output during one cycle of the input clock, and the control signal PLL-rset. Is asserted, and the counter 52 is reset. Thereby, even when the operation of the PLL 21 is unstable in an initial state such as immediately after the power is turned on, the operation of the PLL 21 can be surely reset. The control signal PLL-reset can also be asserted by an external reset signal supplied from the outside. This external reset signal is generated from a reset input supplied from a device outside the chip, a power-on reset signal asserted when power is turned on, or the like.
[0037]
FIG. 4 is a circuit diagram showing the configuration of the delay fine adjustment circuit, in which 59 is a delay fine adjustment circuit (first delay circuit), and 75 and 76 are delay elements.
[0038]
Next, the operation of the delay fine adjustment circuit 59 will be described.
The delay fine adjustment circuit 59 adds a delay corresponding to one stage of the delay element 75 when the control signal DL-CNT output from the DL-CNT generation circuit 57 is at the H level. Thereby, the delay time in the digital delay line 56 is finely adjusted.
By switching the control signal DL-CNT output from the DL-CNT generation circuit 57 in the middle of the cycle of the input clock, a part of the pulse width of the quadruple output is expanded by one delay element within the same input clock cycle. be able to.
[0039]
The DL-CNT generation circuit 57 generates the control signal DL-CNT based on the lower 3 bits of the 10-bit counter 52 and the values of the outputs C1 to C7 of the pulse counter 400.
[0040]
FIG. 5 shows the relationship among the lower 3 bits of the counter 52 in the multiplier 40, various control signals DL-CNT, C1 to C8, DL-ACT, and the quadruple output output from the delay fine adjustment circuit 59. It is a timing chart.
As shown in the timing chart of FIG. 5, when the lower 3 bits of the 10-bit counter 52 are 0, all the quadruple output pulses output from the delay fine adjustment circuit 59 have the same pulse width. Yes. Then, as the lower 3 bit value of the counter 52 increases from, for example, 1 to 7, pulses having a delay time width of one delay element in the delay fine adjustment circuit 59 are changed from the delay fine adjustment circuit 59 to 4. Output as multiplied output.
[0041]
When the counter value of the counter 52 is counted by the number of input clocks and stopped for 20 cycles or more, the lock detection circuit (third counter) 60 outputs a lock detection signal. Even when the lock detection signal is asserted, if the phase of the rising edge of the input clock and the falling edge of the control signal DL-OUT are shifted due to the ambient temperature, voltage, or other factors, The counter value of the counter 52 is increased / decreased by one to eliminate the phase shift. However, once the lock detection signal is asserted, the lock detection signal is not negated unless the control signal PLL-reset is input to the counter 52.
[0042]
Next, the operation of the phase synchronization unit 41 in the PLL 21 will be described.
FIG. 6 is a timing chart showing the operation of the phase synchronization unit 41.
In the phase synchronization unit 41, the quadruple output output from the multiplication unit 40 is delayed for a predetermined time by two digital delay lines (second delay circuits) 69 and 71 incorporated in the phase synchronization unit 41, and input. An operation for matching the phase of the clock and the phase of the control signal P1P is performed. The phase synchronization unit 41 does not operate immediately after resetting, and starts its operation when a lock detection signal is asserted from the lock detection circuit 60 in the multiplication unit 40.
[0043]
A counter (second counter) 65 in the phase synchronization unit 41 controls the operation of the digital delay line 69 with the upper 5-bit value and the digital delay line 71 with the lower 3-bit value. The digital delay line 71 has a configuration in which eight delay elements used in the digital delay line 56 in the multiplier 40 are connected in series. The digital delay line 69 has 32 delay elements having a delay time approximately 6 to 8 times as long as each delay element in the digital delay line 71 (this range varies based on temperature, voltage, process variation, etc.). It has the structure connected to.
[0044]
In the phase synchronizer 41, the digital delay line 69 roughly matches the phase of the input clock and the phase of the control signal P1P, and then the digital delay line 71 adjusts both phases in detail.
[0045]
As an initial value of the counter 65, the counter value of the counter 52 in the multiplier 40 when the lock detection signal output from the lock detection circuit 60 is asserted is set.
Due to the phase difference between the rising edge of the input clock and the rising edge of the control signal P1P, the counter value of the counter 65 is incremented and decremented by one, and the counting operation of the counter 65 stops when the two phases coincide. However, even if the counting operation is once stopped, if the phase of the input clock and the phase of the control signal P1P shift due to temperature, voltage, or other influences, the counter value of the counter 65 is set to 1 according to the magnitude of the shift. Increase and decrease each time to make both phases coincide.
[0046]
The meaning of setting the counter value of the counter 52 in the multiplication unit 40 as an initial value is that when the operation of the phase synchronization unit 41 is started, the phase is advanced (the counter value is subtracted) and the phase is delayed ( In order to obtain an edge that can be surely synchronized regardless of the direction in which the counter value is added), it is possible to obtain a delay time corresponding to a half cycle in advance, or when the phase synchronization unit 41 is locked. This is because the delay time of the delay line 69 is set within one cycle of the input clock to ensure locking and obtain high locking performance. If the delay time of the digital delay line 69 of the phase synchronization unit 41 is locked for two cycles or more, a change in the value of the counter 52 in the multiplication unit 40 or the counter 65 in the phase synchronization unit 41 is put on the control signal P1P. Since the next phase comparison is executed before being performed, the lock operation becomes difficult and the lock performance is lowered.
[0047]
Next, the digital delay lines 56, 69, 71 incorporated in the multiplication unit 40 and the phase synchronization unit 41 will be described.
7 is a circuit diagram showing the configuration of each of the digital delay lines 56, 69, 71. In the figure, each delay element n (n = 0,... Y, y−1,. 1, n) has a configuration in which two sets of circuits obtained by connecting two PMOSTr connected in series and two NMOSTr connected in series are further connected in series. A series connection point connecting the PMOSTr group and the NMOSTr group in series is connected to an output inverter provided between the output node of each delay element and the delay element of the next stage. Each delay element has an input node for inputting an input pulse as an input. The digital delay line 56 in the multiplication unit 40 has a configuration in which 96 delay elements (that is, n = 95) are directly connected, and the digital delay line 71 in the phase synchronization unit 41 has 8 delay elements. The digital delay line 69 has a configuration in which 32 delay elements (n = 31) are connected in series (n = 7).
[0048]
Next, the operation of the digital delay line will be described.
Based on the counter values output from the counters 52 and 65, a predetermined delay element in each of the digital delay lines 56, 69 and 71 is selected by the control signal （WL (n), and an input node n (n of the selected delay element) = 0, ... y, y + 1, ..., n-1, n), input pulses as control signals are input.
[0049]
In this way, the delay time of the digital delay lines 56, 69, 71 is adjusted by changing the input position of the input pulse. This is because the method of changing the input position can reduce the number of transistors to be switched especially when using a high frequency as compared with the conventional method of changing the delay time of the digital delay line by changing the output position.
[0050]
When the counter values of the counters 52 and 65 are y, an input pulse is input into the delay element y via the input node y of the delay element y to which the control signal ￣WL (y) is input. Since two control signals, namely, control signal ￣WL (y) and control signal ￣WL (y + 1) are asserted, input pulses are taken in from two locations of delay element y and delay element y + 1. Thus, it is possible to reliably avoid a state where an indefinite potential is applied to the output a as shown between the timing T7 and the timing T8 in the timing chart of FIG.
[0051]
As described above, according to the first embodiment, the delay time of the digital delay line is set by the counter, and the multiplied output output from the multiplier circuit during one period of the reset signal or input clock supplied from the outside If the number of pulses is less than the desired multiplication number, reset the counter value of the counter that sets the delay time of the digital delay line, and set the counter value so that the delay time of the digital delay line immediately after reset becomes the minimum value. Then, since the delay time of the digital delay line is gradually increased, the control is easy even under low voltage, the output clock can be locked with the desired multiplication factor, and the counter is always in any initial state. An accurate multiplied clock can be supplied. In addition, the digital delay line supplies input pulses from the delay element specified by the counter and two adjacent delay elements, so that malfunctions can be prevented, power consumption is reduced, and the ability to correct fluctuations in temperature, voltage, etc. is reduced. It can be improved.
[0052]
【The invention's effect】
As described above, according to the present invention, the multiplier circuit outputs a clock signal having a predetermined multiple of the input clock signal (input clock) (output clock). , Enter Since the configuration is such that the operation of the multiplier circuit is initialized when the number of pulses of the output clock is less than a predetermined multiplication number during one cycle of the power clock, the desired multiplication number can be reliably ensured even under a low voltage. The output clock can be locked, and the output clock of the desired multiplication number can be obtained with high accuracy and reliability regardless of the initial state of the counter.
[0053]
According to the present invention, the multiplier circuit includes the first delay circuit that delays the cycle or phase of the output clock in stages, and the first counter that sets and controls the delay time of the first delay circuit, and generates the clock. Since the counter value in the first counter is set so that the delay time of the first delay circuit becomes the minimum value when the operation of the circuit is started or when the reset signal is input, the desired multiplication number The output clock can be obtained with high accuracy and reliability.
[0054]
According to the present invention, since the update of the counter value of the first counter is updated only to such a value that the change in the delay time of the first delay circuit becomes the minimum value, the pulse of the output clock There is an effect that an output clock having a desired multiplication number can be obtained with high accuracy and accuracy by gradually widening the width.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a clock generation circuit according to a first embodiment of the present invention.
2 is a block diagram showing a configuration of a PLL in the clock generation circuit shown in FIG.
FIG. 3 is a timing chart showing the operation of the PLL.
FIG. 4 is a circuit diagram showing a configuration of a delay fine adjustment circuit.
FIG. 5 is a timing chart showing the relationship between the lower 3 bit value of the counter in the multiplier, each control signal, and the quadruple output output from the delay fine adjustment circuit.
FIG. 6 is a timing chart showing the operation of the phase synchronization unit.
FIG. 7 is a circuit diagram showing a configuration of a digital delay line.
FIG. 8 is a block diagram showing a configuration of a conventional frequency multiplication circuit.
FIG. 9 is a timing chart showing an operation of the conventional frequency multiplication circuit shown in FIG. 8;
10 is a block diagram showing a conventional clock generation circuit in which a phase synchronization circuit using a digital delay line and a conventional frequency multiplication circuit shown in FIG. 8 using a digital delay line are combined.
11 is a timing chart showing the operation of the conventional clock generation circuit shown in FIG.
FIG. 12 is a block diagram showing a conventional digital delay line.
FIG. 13 is a configuration diagram showing another conventional digital delay line.
14 is a timing chart showing the operation of the conventional digital delay line shown in FIG.
[Explanation of symbols]
20 clock generation circuit, 40 multiplication unit (multiplication circuit), 41 phase synchronization unit (phase synchronization circuit), 52 counter (first counter), 56 digital delay line (first delay circuit), 59 delay fine adjustment circuit ( (First delay circuit), 60 lock detection circuit (third counter), 65 counter (second counter), 69, 71 digital delay line (second delay circuit).

Claims (3)

  A multiplication circuit for outputting a clock signal having a predetermined multiplication number of an input clock signal (hereinafter referred to as an input clock) (hereinafter, a clock signal output from the multiplication circuit is referred to as an output clock), and one cycle of the input clock A clock generation circuit comprising an initialization means for initializing the operation of the multiplication circuit when the number of pulses of the output clock is less than the predetermined multiplication number.   The multiplication circuit includes a first delay circuit that delays the cycle or phase of the output clock in stages, and a first counter that sets and controls a delay time of the first delay circuit, and operates the clock generation circuit. 2. The counter value in the first counter is set so that the delay time of the first delay circuit becomes a minimum value at the start or when a reset signal is input from the outside. Clock generation circuit.   3. The clock generation circuit according to claim 2, wherein the update of the counter value of the first counter is updated only to such a value that a change in the delay time of the first delay circuit becomes a minimum value.

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