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JP4031105B2 - Active matrix type liquid crystal display device - Google Patents

Active matrix type liquid crystal display device Download PDF

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Publication number
JP4031105B2
JP4031105B2 JP13512598A JP13512598A JP4031105B2 JP 4031105 B2 JP4031105 B2 JP 4031105B2 JP 13512598 A JP13512598 A JP 13512598A JP 13512598 A JP13512598 A JP 13512598A JP 4031105 B2 JP4031105 B2 JP 4031105B2
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electrode
liquid crystal
gate line
crystal display
insulating film
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JPH11326949A (en
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耕平 永山
康行 花澤
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東芝松下ディスプレイテクノロジー株式会社
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Description

【0001】
【発明の属する技術分野】
本発明は、電極基板間に液晶組成物を保持して成る液晶表示素子において、マトリクス状に配列されたスイッチング素子にて画素電極を駆動するアクティブマトリクス型液晶表示素子に関する。
【0002】
【従来の技術】
近年、薄型軽量且つ高密度大容量でありながら高機能更には高精細を得る液晶表示素子の開発が図られ、特に高開口率化のために、透明な画素電極を、薄膜トランジスタ(以下TFTと称する。)や金属・絶縁膜・金属(MIM)素子等のスイッチング素子を覆うように配置して成る、画素上置き構造の液晶表示素子が注目されている。更にカラーフィルタとのずれを考慮する必要が無く製造歩留まりの向上を得られるため、画素電極下に有機樹脂絶縁膜を形成して成るカラーフィルター一体型のアレイ基板を用いて成るアクティブマトリクス型液晶表示素子の開発が成されていた。
【0003】
このようなカラーフィルター一体型のアレイ基板を用いて成るアクティブマトリクス型液晶表示素子は、従来図7及び図8に示す様に形成されていた。即ち液晶表示素子1のアレイ基板2は、カラーフィルタである有機樹脂絶縁膜11と一体的に形成され、アレイ基板2上の信号線3とゲート線4の交差部には、画素電極6のスイッチング素子であるTFT7が形成されている。TFT7のソース電極8及び前段の画素電極6aは、透明絶縁膜10と有機樹脂絶縁膜11を貫通する第1のスルーホール12を介して電気的に接続され、ゲート線4と補助容量を形成する補助容量電極13及び次段の画素電極6bは、透明絶縁膜10と有機樹脂絶縁膜11を貫通する第2のスルーホール14を介して電気的に接続されている。
【0004】
又ー般的に、カラー表示を得るための十分な色純度のカラーフィルターを得るためには、カラーフィルタを構成する有機樹脂絶縁膜の膜厚を約3μmと厚くする必要がある。
【0005】
【発明が解決しようとする課題】
従来画素電極上置きタイプのカラーフィルター一体型のアレイ基板にあっては、有機樹脂絶縁膜を貫通する2個のスルーホールを介して前段の画素電極及びソース電極或いは次段の画素電極及び補助容量電極を夫々電気的に接続していた。一方カラーフィルタを構成する有機樹脂絶縁膜の膜厚は、良好なカラー表示を行うための十分な色純度のカラーフィルターを得るためには、約3μmと厚くする必要がある。
【0006】
このため厚膜の有機樹脂絶縁膜を貫通して成るスルーホールは、その加工が難しく、貫通穴を完全に形成できずに形成不良を発生し、点欠陥などの表示不良を発生し易く、液晶表示素子の表示品位の低下を来たすという問題を生じていた。しかも、従来のアレイ基板にあっては加工の難しい厚膜の有機樹脂絶縁膜におけるスルーホールを1画素電極当たり2個必要とすることから、スルーホールの形成不良によるアレイ基板の歩留まりを一層低下していた。
【0007】
又有機樹脂絶縁膜が厚膜であることからスルーホール径の最小加工寸法は10μm以上と大きく、このようなアレイ基板を用いた液晶表示素子は開口率が低下し、明るさ及びコントラストの低下により表示品位が著しく低下するという問題も生じていた。
【0008】
このため本発明は上記課題を解決するもので、有機樹脂絶縁膜を貫通するスルーホールを介して前段の画素電極とソース電極或いは次段の画素電極と補助容量電極とを電気的に接続する際に、スルーホールの形成不良を防止し、点欠陥などの表示不良による表示品位の低下を防止しすると共に、スルーホールにより、液晶表示領域の開口率が低下するのを防止し、表示画像の明るさ及びコントラストの向上を図り高品位の表示を行う事が出来るアクティブマトリクス型液晶表示素子を提供する事を目的とする。
【0009】
【課題を解決するための手段】
本発明は上記課題を解決する為、絶縁基板上にゲート線と、このゲート線と交差するよう配線される信号線と、前記ゲート線及び前記信号線の交点に配列され少なくとも、チャネル領域を挟みソース領域及びドレイン領域を有する半導体層、前記ゲート線と一体のゲート電極、前記ソース領域に接続されるソース電極並びに前記ドレイン領域に接続されるドレイン電極を有するスイッチング素子と、前記ゲート線と補助容量を形成する補助容量電極と、前記スイッチング素子及び前記補助容量電極を被覆する有機樹脂絶縁膜と、この有機樹脂絶縁膜上の前記ゲート線及び前記信号線に囲まれる領域にマトリクス状に配置され前記有機樹脂絶縁膜に形成されたスルーホールを介して前記ソース電極に接続される複数の画素電極を有するアレイ基板と、前記アレイ基板に間隙を隔てて対向配置される対向基板と、前記アレイ基板及び前記対向基板間に封入される液晶組成物とを具備する液晶表示装置において、前記補助容量電極が前記ソース電極と共通のスルーホールを介して前記有機樹脂絶縁膜より露出され、かつ前記ソース電極に接続された画素電極と前記ゲート線を挟んで隣接する他の画素電極に対し前記スルーホールを介して接続されているものである。
【0010】
上記構成により本発明は、有機樹脂絶縁膜を貫通してソース電極から補助容量電極に達する単一のスルーホールを形成して、この単一スルーホールを介して前段の画素電極とソース電極或いは次段の画素電極と補助容量電極との電気的な接続を行い、厚膜の有機樹脂絶縁膜に形成する1画素電極当たりのスルーホールの数を1個にして加工数を低減し、しかも単一のスルーホールの加工寸法の拡大により加工性を良くする事により、製造歩留まりの向上を図り、スルーホール形成不良による点欠陥を防止して液晶表示素子の表示品位の向上を図るものである。又スルーホールをゲート線上に配置する事により、液晶表示素子の開口率を拡大し、表示画像の明るさ及びコントラストを向上して表示品位の向上を図るものである。
【0011】
【発明の実施の形態】
以下、本発明の実施の形態を図1乃至図4を参照して説明する。17はアクティブマトリクス型の液晶表示素子であり、画素電極44のスイッチング素子として画素TFT18を用いるアレイ基板20と、対向基板21との間に、配向膜22、23を介して液晶組成物であるネマティック液晶24を封入して成っている。又、26、27は、アレイ基板20及び対向基板21の外側に夫々貼着される偏光板である。
【0012】
アレイ基板20は、透明なガラス等からなる透明絶縁基板28上に多結晶シリコンからなるチャネル領域30a、多結晶シリコンを低抵抗化して成るソース領域30b及びドレイン領域30cを有する半導体層30がパターン形成され、その上に膜厚100nmの酸化シリコン(SiOx)等からなるゲート絶縁膜31を介し、厚さ400nmのタンタル(Ta)、クロム(Cr)、アルミニウム(Al)、モリブデン(Mo)、タングステン(W)、銅(Cu)等金属あるいはこれ等金属の単体又はその積層膜或いは合金膜からなりゲート電極32を一体的に形成して成るゲート線33がパターン形成されている。
【0013】
これ等の上に成膜される膜厚500nmの酸化シリコン(SiOx)等の絶縁膜からなる層間絶縁膜34上には、厚さ500nmのタンタル(Ta)、クロム(Cr)、アルミニウム(Al)、モリブデン(Mo)、タングステン(W)、銅(Cu)等金属あるいはこれ等金属の単体又はその積層膜或いは合金膜からなるドレイン電極36aと一体の信号線36、ソース電極37、補助容量電極38がパターン形成されている。ドレイン電極36a及びソース電極37は、コンタクトホール40、41を介しドレイン領域30c及びソース領域30bに電気的に接続され、画素電極44を駆動する画素TFT18を形成している。尚ソース電極37は、このタクトホール41からゲート線33上方に達する様パターン形成されている。
【0014】
これ等の上には、窒化シリコン(SiNx)等の絶縁膜からなる無機絶縁膜である透明保護絶縁膜42及び有機樹脂絶縁膜である膜厚3μmの緑(G)、青(B)、赤(R)の着色絶縁層43が形成され、更に厚さ100nmのインジウム錫酸化物(以下ITOと略称する。)からなる画素電極44がパターン形成されている。そして前段の画素電極44aは、着色絶縁層43及び透明保護絶縁膜42を貫通してソース電極37及び補助容量電極38に達するスルーホール47を介しソース電極37に接続し、次段の画素電極44bも、スルーホール47を介し補助容量電極38に接続している。
【0015】
一方対向基板21は、透明なガラス等からなる透明絶縁基板48上にITOからなる対向電極50を有している。
【0016】
次に図4を参照してアレイ基板20の製造方法について述べる。先ず透明絶縁基板28上にCVD法などによりアモルファスシリコン膜を50nm被着して450℃で1時間炉アニールを行った後、XeC1エキシマレーザを照射し、アモルファスシリコン膜を多結晶化して多結晶シリコン膜を形成する。その後に、多結晶シリコン膜をフォトエッチング法によりパターンニングして、表示領域内の画素TFT18の半導体層30をパターン形成する。
【0017】
次に、図4(a)に示すようにCVD法により透明絶縁基板28の全面にゲート絶縁膜31となる酸化シリコン(SiOx)膜を100nm成膜する。続いて図4(b)に示すようにゲート絶縁膜31上にタンタル(Ta)、クロム(Cr)、アルミニウム(Al)、モリブデン(Mo)、タングステン(W)、銅(Cu)等金属あるいはこれ等金属の単体又はその積層膜或いは合金膜を成膜し、フォトエッチング法によりゲート電極32及びゲート線33をパターン形成する。次いでゲート電極32をマスクとして半導体層30のチャネル領域30a両側にイオン注入やイオンドーピング法により不純物を注入して、ソース領域30b及びドレイン領域30cを形成する。不純物の注入は、例えば加速電圧80keVで5×1015atoms /cm2 のドーズ量で、PH3 /H2 (ホスフィン/水素)によりP(リン)を高濃度注入する。その後、透明絶縁基板28をアニールすることにより不純物を活性化する。
【0018】
更に図4(c)に示すように、例えばPECVD法を用いて透明絶縁基板28の全面に層間絶縁膜34を成膜し、フォトエッチング法により、層間絶縁膜34に画素TFT18のドレイン領域30cとソース領域30bに至るコンタクトホール40、41を形成する。次に、タンタル(Ta)、クロム(Cr)、アルミニウム(Al)、モリブデン(Mo)、タングステン(W)、銅(Cu)等金属あるいはこれ等金属の単体又はその積層膜或いは合金膜を500nm成膜し、図4(d)に示すようにフォトエッチング法により所定の形状にパターニングし、ドレイン電極36aと一体の信号線36、ソース電極37、補助容量電極38を形成する。これにより、コンタクトホール40、41を介し信号線36と一体のドレイン電極36aはドレイン領域30cに電気的に接続され、ソース電極37はソース領域30bに電気的に接続される。
【0019】
次にPECVD法により図4(e)に示すように、透明絶縁基板28の全面に窒化シリコン(SiNx)からなる透明保護絶縁膜42を成膜し、図4(f)に示すようにフォトエッチング法により透明保護絶縁膜42に、ゲート線33上にてソース電極37から補助容量電極38に達するスルーホール47の第1の部分47aを形成する。更にPECVD法により図4(g)に示すように着色絶縁層43を成膜し、図4(h)に示すようにフォトエッチング法により着色絶縁層43にソース電極37及び補助容量電極38に達するスルーホール47の第2の部分47bを形成してスルーホール47を貫通する。これ等の上にITOをスパッタ法により100nm成膜し、フォトエッチング法により所定の形状にパターンニングして、図4(i)に示すように画素電極44を形成する。これにより、スルーホール47を介し前段の画素電極44aはソース電極37に電気的に接続し、次段の画素電極44bは補助容量電極38に電気的に接続する。
【0020】
次に対向基板21にあっては、透明絶縁基板48上にスパッタ法によりITOから成る対向電極50を全面に形成する。そしてアレイ基板20及び対向基板21の対向面に、夫々低温キュア型のポリイミドからなる配向膜22、23を印刷塗布し、両基板22、23の対向時に配向軸が90゜となるようにラビング処理をした後、両基板20、21を対向して組み立て、セル化してその間隙にネマティック液晶24を注入し封止する。そして、両基板20、21の透明絶縁基板28、48側に偏光板26、27を貼り付けることにより液晶表示素子17を形成する。
【0021】
この様に構成すれば、前段の画素電極44aとソース電極37との接続及び、次段の画素電極44bと補助容量電極38との接続のための1画素当たりのスルーホール47が単一である事から、着色絶縁層43が厚膜であり、スルーホール47の加工が難しくても、その加工数を従来に比し半減する事により製造歩留まりを向上出来る。しかもスルーホール47は、ソース電極37及び補助容量電極38に共通であり、従来の様にソース電極及び補助容量電極夫々に個別に形成するものに比し加工寸法が拡大される事により加工性を向上出来る事からも、形成不良による点欠陥などの表示不良を生じる事もなく、歩留まりの向上を図れる。
【0022】
更にソース電極37を画素電極44内のソース領域30bからゲート線33上方に延在するよう配線して、加工面積の大きいスルーホール47を、画素電極44内では無くゲート線33上方に配置する事により、ゲート線33がスルーホール47の遮光を兼ねることとなり、画素電極44内にスルーホール47のための遮光領域を設ける必要が無い事から、液晶表示素子17の開口率を向上出来、より明るくコントラストの良い表示画像を得られ、表示品位を向上出来る。
【0023】
尚本発明は上記実施の形態に限られるものではなく、その趣旨を変えない範囲での変更は可能であって、例えば、着色絶縁層及び透明保護絶縁膜を貫通して成る単一のスルーホールの配置位置はゲート線上方に限られる事無く、画素電極内に配置されていても良い。又、スルーホールの形状も厚膜で加工し難い着色絶縁層の部分が単一であれば良く、図5及び図6に示す変形例の様に、信号線36、ソース電極37、補助容量電極38上の透明保護絶縁膜42にあっては、ゲート線33上方にてソース電極37に達する第1のスルーホール51及び補助容量電極38に達する第2のスルーホール52を夫々に形成する一方、着色絶縁層43にあっては、第1のスルーホール51及び第2のスルーホール52上方にてソース電極37及び補助容量電極38に達する単一の第3のスルーホール53を形成する事により、第1のスルーホール51及び第3のスルーホール53を介して前段の画素電極44aをソース電極37に接続し、第2のスルーホール52及び第3のスルーホール53を介して次段の画素電極44bを補助容量電極38に接続しても良い。この様に形成すれば、厚膜の着色絶縁層43に形成される第3のスルーホール53は1画素当たり1個であることから、従来の装置に比し製造歩留まり向上を図れる。
【0024】
又アレイ基板の構造も任意であり、画素TFTの半導体層をアモルファスシリコンで形成しても良いし、着色絶縁層が透明絶縁層を兼用し、ソース電極及び補助容量電極を絶縁するため、透明絶縁層を介する事無くソース電極及び補助容量電極上に着色絶縁層を直接成膜する等しても良い。
【0025】
【発明の効果】
以上説明したように本発明によれば、有機樹脂絶縁膜のスルーホールを1画素当たり1個とし、この単一のスルーホールを介して前段の画素電極とソース電極との接続及び、次段の画素電極と補助容量電極との接続を行う事により、厚膜で加工の難しい有機樹脂絶縁膜におけるスルーホールの加工数を従来に比し半減出来、アレイ基板の製造歩留まりを従来に比し向上出来る。更にスルーホールを個別に形成していた場合に比し、スルーホールの加工寸法を拡大出来るので、加工性が良くなり形成不良による点欠陥などの表示不良を低減出来る事からも製造歩留まりの向上を図れる。
【0026】
又ソース電極をゲート線上方迄延在して、ゲート線上方にてソース電極に対するスルーホールを形成する事により、画素電極内の遮光領域を縮小出来る。これにより液晶表示素子の開口率を向上出来、より明るくコントラストの良い表示画像を得られ、表示品位向上を図れる。
【図面の簡単な説明】
【図1】本発明の実施の形態のアレイ基板を示す一部概略平面図である。
【図2】本発明の実施の形態のアレイ基板に形成されるスルーホール部分を示す概略平面図である。
【図3】本発明の実施の形態の液晶表示素子を示す図2のA−A‘線における概略断面図である。
【図4】本発明の実施の形態のアレイ基板の製造工程を示し、(a)はそのゲート絶縁膜成膜時、(b)はそのゲート線形成時、(c)はその層間絶縁膜成膜時、(d)はそのソース電極、補助容量電極形成時、(e)はその透明保護絶縁膜成膜時、(f)はそのスルーホールの第1の部分形成時、(g)はその着色絶縁膜成膜時、(h)はそのスルーホールの第2の部分形成時、(i)はその画素電極形成時を示す概略説明図である。
【図5】本発明の他の変形例のアレイ基板に形成されるスルーホール部分を示す概略平面図である。
【図6】本発明の他の変形例の液晶表示素子を示す図5B−B‘線における概略断面図である。
【図7】従来のアレイ基板を示す一部概略平面図で有る。
【図8】従来の液晶表示素子を示す図7のC−C‘線における概略断面図である。
【符号の説明】
17…液晶表示素子
18…画素TFT
20…アレイ基板
21…対向基板
22、23…配向膜
24…ネマティック液晶
26、27…偏光板
28…透明絶縁基板
30…半導体層
31…ゲート絶縁膜
32…ゲート電極
33…ゲート線
34…層間絶縁膜
36…信号線
37…ソース電極
38…補助容量電極
40、41…コンタクトホール
42…透明保護絶縁膜
43…着色絶縁膜
44…画素電極
47…スルーホール
48…透明絶縁基板
50…対向基板
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an active matrix liquid crystal display element in which a pixel electrode is driven by switching elements arranged in a matrix in a liquid crystal display element in which a liquid crystal composition is held between electrode substrates.
[0002]
[Prior art]
In recent years, liquid crystal display elements that achieve high performance and high definition while being thin, light, high density, and large capacity have been developed. In particular, in order to increase the aperture ratio, a transparent pixel electrode is referred to as a thin film transistor (hereinafter referred to as TFT). ) And a liquid crystal display element having a pixel-top structure, which is arranged so as to cover a switching element such as a metal, an insulating film, or a metal (MIM) element. In addition, since there is no need to consider the deviation from the color filter and the production yield can be improved, an active matrix liquid crystal display using an array substrate integrated with a color filter formed by forming an organic resin insulating film under the pixel electrode. The device was being developed.
[0003]
An active matrix type liquid crystal display device using such an array substrate integrated with a color filter has been conventionally formed as shown in FIGS. That is, the array substrate 2 of the liquid crystal display element 1 is formed integrally with the organic resin insulating film 11 that is a color filter, and the pixel electrode 6 is switched at the intersection of the signal line 3 and the gate line 4 on the array substrate 2. A TFT 7 as an element is formed. The source electrode 8 of the TFT 7 and the previous pixel electrode 6a are electrically connected through the first through hole 12 penetrating the transparent insulating film 10 and the organic resin insulating film 11 to form the gate line 4 and the auxiliary capacitance. The auxiliary capacitance electrode 13 and the next pixel electrode 6 b are electrically connected via a second through hole 14 that penetrates the transparent insulating film 10 and the organic resin insulating film 11.
[0004]
In general, in order to obtain a color filter having sufficient color purity for obtaining a color display, it is necessary to increase the film thickness of the organic resin insulating film constituting the color filter to about 3 μm.
[0005]
[Problems to be solved by the invention]
In a conventional pixel electrode-mounted color filter-integrated array substrate, the previous pixel electrode and source electrode or the next pixel electrode and auxiliary capacitor are passed through two through holes penetrating the organic resin insulating film. Each electrode was electrically connected. On the other hand, the film thickness of the organic resin insulating film constituting the color filter needs to be as thick as about 3 μm in order to obtain a color filter having sufficient color purity for good color display.
[0006]
For this reason, a through-hole formed through a thick organic resin insulating film is difficult to process, and the through-hole cannot be completely formed, resulting in formation defects, and display defects such as point defects. There has been a problem that the display quality of the display element is lowered. In addition, since two through holes are required per pixel electrode in a thick organic resin insulating film that is difficult to process with conventional array substrates, the yield of the array substrate due to poor formation of through holes is further reduced. It was.
[0007]
In addition, since the organic resin insulating film is thick, the minimum processing size of the through-hole diameter is as large as 10 μm or more, and the liquid crystal display element using such an array substrate has a reduced aperture ratio, which decreases brightness and contrast. There has also been a problem that the display quality is significantly lowered.
[0008]
For this reason, the present invention solves the above-described problem, and when the previous pixel electrode and the source electrode or the subsequent pixel electrode and the auxiliary capacitance electrode are electrically connected through the through hole penetrating the organic resin insulating film. In addition, it prevents the formation of through-holes and prevents the display quality from deteriorating due to display defects such as point defects, and prevents the through-hole from decreasing the aperture ratio of the liquid crystal display area, thereby improving the brightness of the displayed image. An object of the present invention is to provide an active matrix type liquid crystal display device capable of improving display quality and contrast and capable of performing high-quality display.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a gate line on an insulating substrate, a signal line wired so as to cross the gate line, and an intersection of the gate line and the signal line, and at least sandwiching a channel region. A semiconductor layer having a source region and a drain region; a gate electrode integrated with the gate line; a source electrode connected to the source region; a switching element having a drain electrode connected to the drain region; and the gate line and auxiliary capacitance An auxiliary capacitor electrode for forming the switching element and the organic resin insulating film that covers the auxiliary capacitor electrode, and a region on the organic resin insulating film surrounded by the gate line and the signal line, and arranged in a matrix An array base having a plurality of pixel electrodes connected to the source electrode through through holes formed in an organic resin insulating film And a liquid crystal composition sealed between the array substrate and the counter substrate, wherein the auxiliary capacitance electrode is the source electrode The pixel electrode is exposed from the organic resin insulating film through a common through hole and is connected to the pixel electrode connected to the source electrode and the other pixel electrode adjacent to the gate line via the through hole. It is what.
[0010]
With the above configuration, the present invention forms a single through hole that penetrates the organic resin insulating film and reaches the storage capacitor electrode from the source electrode, and the previous pixel electrode and the source electrode or the next through the single through hole. The electrical connection between the pixel electrode of the stage and the auxiliary capacitance electrode is performed, the number of through holes per pixel electrode formed in the thick organic resin insulation film is reduced to one, and the number of processing is reduced. By improving the workability by increasing the through-hole processing dimensions, the manufacturing yield is improved, and point defects due to through-hole formation defects are prevented, thereby improving the display quality of the liquid crystal display element. Further, by arranging the through hole on the gate line, the aperture ratio of the liquid crystal display element is increased, the brightness and contrast of the display image are improved, and the display quality is improved.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIGS. Reference numeral 17 denotes an active matrix type liquid crystal display element, which is a nematic liquid crystal composition between the array substrate 20 using the pixel TFT 18 as a switching element of the pixel electrode 44 and the counter substrate 21 via the alignment films 22 and 23. The liquid crystal 24 is enclosed. Reference numerals 26 and 27 denote polarizing plates attached to the outside of the array substrate 20 and the counter substrate 21, respectively.
[0012]
The array substrate 20 is formed by patterning a semiconductor layer 30 having a channel region 30a made of polycrystalline silicon, a source region 30b and a drain region 30c made by reducing the resistance of polycrystalline silicon on a transparent insulating substrate 28 made of transparent glass or the like. 400 nm thick tantalum (Ta), chromium (Cr), aluminum (Al), molybdenum (Mo), tungsten (thickness) are formed on the gate insulating film 31 made of silicon oxide (SiOx) or the like having a thickness of 100 nm. W), a metal such as copper (Cu), a single body of these metals, or a laminated film or alloy film thereof, and a gate line 33 formed by integrally forming the gate electrode 32 is patterned.
[0013]
A 500 nm thick tantalum (Ta), chromium (Cr), and aluminum (Al) film are formed on the interlayer insulating film 34 made of an insulating film such as silicon oxide (SiOx) having a thickness of 500 nm. , Molybdenum (Mo), tungsten (W), copper (Cu) or the like, or a single electrode of these metals, or a drain electrode 36a made of a laminated film or alloy film thereof, a signal line 36 integrated with the source electrode 37, and an auxiliary capacitance electrode 38. Is patterned. The drain electrode 36 a and the source electrode 37 are electrically connected to the drain region 30 c and the source region 30 b through the contact holes 40 and 41, thereby forming the pixel TFT 18 that drives the pixel electrode 44. The source electrode 37 is formed in a pattern so as to reach the gate line 33 from the tact hole 41.
[0014]
On top of these, a transparent protective insulating film 42 that is an inorganic insulating film made of an insulating film such as silicon nitride (SiNx), and green (G), blue (B), red, and 3 μm thick organic resin insulating films. A colored insulating layer 43 of (R) is formed, and a pixel electrode 44 made of indium tin oxide (hereinafter abbreviated as ITO) having a thickness of 100 nm is patterned. The preceding pixel electrode 44a is connected to the source electrode 37 through the colored insulating layer 43 and the transparent protective insulating film 42 and through the through hole 47 reaching the source electrode 37 and the auxiliary capacitance electrode 38, and the next pixel electrode 44b. Is also connected to the auxiliary capacitance electrode 38 through the through hole 47.
[0015]
On the other hand, the counter substrate 21 has a counter electrode 50 made of ITO on a transparent insulating substrate 48 made of transparent glass or the like.
[0016]
Next, a method for manufacturing the array substrate 20 will be described with reference to FIG. First, an amorphous silicon film having a thickness of 50 nm is deposited on the transparent insulating substrate 28 by CVD or the like, and furnace annealing is performed at 450 ° C. for 1 hour, followed by irradiation with XeC1 excimer laser to polycrystallize the amorphous silicon film. A film is formed. Thereafter, the polycrystalline silicon film is patterned by a photoetching method to pattern the semiconductor layer 30 of the pixel TFT 18 in the display region.
[0017]
Next, as shown in FIG. 4A, a silicon oxide (SiOx) film to be the gate insulating film 31 is formed to 100 nm on the entire surface of the transparent insulating substrate 28 by the CVD method. Subsequently, as shown in FIG. 4B, a metal such as tantalum (Ta), chromium (Cr), aluminum (Al), molybdenum (Mo), tungsten (W), copper (Cu) or the like is formed on the gate insulating film 31. A single metal such as a single layer or a laminated film thereof or an alloy film is formed, and the gate electrode 32 and the gate line 33 are patterned by a photoetching method. Next, using the gate electrode 32 as a mask, impurities are implanted into both sides of the channel region 30a of the semiconductor layer 30 by ion implantation or ion doping to form a source region 30b and a drain region 30c. The impurity is implanted by, for example, implanting P (phosphorus) at a high concentration by PH 3 / H 2 (phosphine / hydrogen) at an acceleration voltage of 80 keV and a dose of 5 × 10 15 atoms / cm 2 . Thereafter, the transparent insulating substrate 28 is annealed to activate the impurities.
[0018]
Further, as shown in FIG. 4C, an interlayer insulating film 34 is formed on the entire surface of the transparent insulating substrate 28 using, for example, PECVD, and the drain region 30c of the pixel TFT 18 is formed on the interlayer insulating film 34 by photoetching. Contact holes 40 and 41 reaching the source region 30b are formed. Next, a metal such as tantalum (Ta), chromium (Cr), aluminum (Al), molybdenum (Mo), tungsten (W), copper (Cu), a single element of these metals, or a laminated film or alloy film thereof is formed to a thickness of 500 nm. 4D, and patterned into a predetermined shape by a photoetching method as shown in FIG. 4D, to form a signal line 36 integrated with the drain electrode 36a, a source electrode 37, and an auxiliary capacitance electrode 38. Thereby, the drain electrode 36a integrated with the signal line 36 is electrically connected to the drain region 30c via the contact holes 40 and 41, and the source electrode 37 is electrically connected to the source region 30b.
[0019]
Next, as shown in FIG. 4E, a transparent protective insulating film 42 made of silicon nitride (SiNx) is formed on the entire surface of the transparent insulating substrate 28 by PECVD, and photoetching is performed as shown in FIG. A first portion 47 a of a through hole 47 reaching from the source electrode 37 to the auxiliary capacitance electrode 38 on the gate line 33 is formed in the transparent protective insulating film 42 by the method. Further, a colored insulating layer 43 is formed by PECVD as shown in FIG. 4G, and reaches the source electrode 37 and the auxiliary capacitance electrode 38 on the colored insulating layer 43 by photoetching as shown in FIG. 4H. A second portion 47 b of the through hole 47 is formed and penetrates the through hole 47. On this, ITO is deposited to a thickness of 100 nm by a sputtering method, and patterned into a predetermined shape by a photoetching method to form a pixel electrode 44 as shown in FIG. As a result, the previous pixel electrode 44 a is electrically connected to the source electrode 37 through the through hole 47, and the next pixel electrode 44 b is electrically connected to the auxiliary capacitance electrode 38.
[0020]
Next, in the counter substrate 21, a counter electrode 50 made of ITO is formed on the entire surface of the transparent insulating substrate 48 by sputtering. Then, alignment films 22 and 23 made of low-temperature cured polyimide are printed on the opposing surfaces of the array substrate 20 and the counter substrate 21, respectively, and a rubbing process is performed so that the alignment axis is 90 ° when the substrates 22 and 23 are opposed to each other. After that, both the substrates 20 and 21 are assembled to face each other to form a cell, and a nematic liquid crystal 24 is injected into the gap to be sealed. Then, the liquid crystal display element 17 is formed by attaching the polarizing plates 26 and 27 to the transparent insulating substrates 28 and 48 of both the substrates 20 and 21.
[0021]
With this configuration, there is a single through-hole 47 per pixel for connecting the pixel electrode 44a in the previous stage and the source electrode 37 and for connecting the pixel electrode 44b in the next stage and the auxiliary capacitance electrode 38. Therefore, even if the colored insulating layer 43 is a thick film and it is difficult to process the through hole 47, the manufacturing yield can be improved by halving the number of processing compared to the conventional method. In addition, the through-hole 47 is common to the source electrode 37 and the auxiliary capacitance electrode 38, and the workability is increased by increasing the processing size as compared to the case where the source electrode and the auxiliary capacitance electrode are individually formed as in the prior art. Since it can be improved, display defects such as point defects due to formation defects do not occur, and the yield can be improved.
[0022]
Further, the source electrode 37 is wired so as to extend from the source region 30 b in the pixel electrode 44 to above the gate line 33, and the through hole 47 having a large processing area is disposed not in the pixel electrode 44 but above the gate line 33. As a result, the gate line 33 also serves as light shielding for the through hole 47, and it is not necessary to provide a light shielding region for the through hole 47 in the pixel electrode 44. Therefore, the aperture ratio of the liquid crystal display element 17 can be improved and brighter. A display image with good contrast can be obtained and display quality can be improved.
[0023]
The present invention is not limited to the above embodiment, and can be changed without changing the gist of the present invention. For example, a single through hole formed through a colored insulating layer and a transparent protective insulating film. The arrangement position is not limited to the upper side of the gate line, and may be arranged in the pixel electrode. Further, the through hole may be a thick film that has a single color insulating layer portion that is difficult to process, and the signal line 36, the source electrode 37, the auxiliary capacitance electrode, as in the modification shown in FIGS. In the transparent protective insulating film 42 on 38, a first through hole 51 reaching the source electrode 37 and a second through hole 52 reaching the auxiliary capacitance electrode 38 are formed above the gate line 33, respectively. In the colored insulating layer 43, by forming a single third through hole 53 that reaches the source electrode 37 and the auxiliary capacitance electrode 38 above the first through hole 51 and the second through hole 52, The previous pixel electrode 44 a is connected to the source electrode 37 via the first through hole 51 and the third through hole 53, and the next pixel electrode is connected via the second through hole 52 and the third through hole 53. 4b 2008 may be connected to the storage capacitor electrode 38. If formed in this way, the number of third through holes 53 formed in the thick colored insulating layer 43 is one per pixel, so that the manufacturing yield can be improved as compared with the conventional device.
[0024]
The structure of the array substrate is arbitrary, and the semiconductor layer of the pixel TFT may be formed of amorphous silicon. The colored insulating layer also serves as the transparent insulating layer, and insulates the source electrode and the auxiliary capacitance electrode. A colored insulating layer may be directly formed on the source electrode and the auxiliary capacitance electrode without using a layer.
[0025]
【The invention's effect】
As described above, according to the present invention, the number of through holes in the organic resin insulating film is one per pixel, and the connection between the pixel electrode and the source electrode in the previous stage and the next stage through the single through hole. By connecting the pixel electrode and the auxiliary capacitor electrode, the number of through-holes in the thick organic resin insulating film that is difficult to process can be halved compared to the conventional one, and the manufacturing yield of the array substrate can be improved compared to the conventional one. . Furthermore, compared to the case where through holes are individually formed, the processing dimensions of the through holes can be expanded, so that the workability is improved and display defects such as point defects due to formation defects can be reduced, which improves the manufacturing yield. I can plan.
[0026]
Further, the light shielding region in the pixel electrode can be reduced by extending the source electrode to above the gate line and forming a through hole with respect to the source electrode above the gate line. Thereby, the aperture ratio of the liquid crystal display element can be improved, and a brighter and higher contrast display image can be obtained, thereby improving the display quality.
[Brief description of the drawings]
FIG. 1 is a partial schematic plan view showing an array substrate according to an embodiment of the present invention.
FIG. 2 is a schematic plan view showing a through hole portion formed in the array substrate according to the embodiment of the present invention.
3 is a schematic cross-sectional view taken along the line AA ′ of FIG. 2 showing the liquid crystal display element according to the embodiment of the present invention.
4A and 4B show a manufacturing process of an array substrate according to an embodiment of the present invention, in which FIG. 4A shows the gate insulating film formation, FIG. 4B shows the gate line formation, and FIG. 4C shows the interlayer insulating film formation. (D) when forming the source electrode and auxiliary capacitance electrode, (e) when forming the transparent protective insulating film, (f) when forming the first part of the through hole, and (g) When forming a colored insulating film, (h) is a schematic explanatory diagram showing the second partial formation of the through hole, and (i) is a schematic explanatory view showing the pixel electrode formation.
FIG. 5 is a schematic plan view showing a through hole portion formed in an array substrate according to another modification of the present invention.
6 is a schematic cross-sectional view taken along line BB ′ of FIG. 5 showing a liquid crystal display device according to another modification of the present invention.
FIG. 7 is a partial schematic plan view showing a conventional array substrate.
8 is a schematic cross-sectional view taken along the line CC ′ of FIG. 7 showing a conventional liquid crystal display element.
[Explanation of symbols]
17 ... Liquid crystal display element 18 ... Pixel TFT
DESCRIPTION OF SYMBOLS 20 ... Array substrate 21 ... Counter substrate 22, 23 ... Orientation film 24 ... Nematic liquid crystal 26, 27 ... Polarizing plate 28 ... Transparent insulating substrate 30 ... Semiconductor layer 31 ... Gate insulating film 32 ... Gate electrode 33 ... Gate line 34 ... Interlayer insulation Film 36 ... Signal line 37 ... Source electrode 38 ... Auxiliary capacitance electrodes 40, 41 ... Contact hole 42 ... Transparent protective insulating film 43 ... Colored insulating film 44 ... Pixel electrode 47 ... Through hole 48 ... Transparent insulating substrate 50 ... Counter substrate

Claims (5)

絶縁基板上にゲート線と、このゲート線と交差するよう配線される信号線と、前記ゲート線及び前記信号線の交点に配列され少なくとも、チャネル領域を挟みソース領域及びドレイン領域を有する半導体層、前記ゲート線と一体のゲート電極、前記ソース領域に接続されるソース電極並びに前記ドレイン領域に接続されるドレイン電極を有するスイッチング素子と、前記ゲート線と補助容量を形成する補助容量電極と、前記スイッチング素子及び前記補助容量電極を被覆する有機樹脂絶縁膜と、この有機樹脂絶縁膜上の前記ゲート線及び前記信号線に囲まれる領域にマトリクス状に配置され前記有機樹脂絶縁膜に形成されたスルーホールを介して前記ソース電極に接続される複数の画素電極を有するアレイ基板と、
前記アレイ基板に間隙を隔てて対向配置される対向基板と、
前記アレイ基板及び前記対向基板間に封入される液晶組成物とを具備する液晶表示装置において、
前記補助容量電極が前記ソース電極と共通のスルーホールを介して前記有機樹脂絶縁膜より露出され、かつ前記ソース電極に接続された画素電極と前記ゲート線を挟んで隣接する他の画素電極に対し前記スルーホールを介して接続されている事を特徴とするアクティブマトリクス型液晶表示素子。
A semiconductor layer having a source region and a drain region sandwiched between a gate line, a signal line wired so as to intersect the gate line, and at least an intersection of the gate line and the signal line, with a channel region interposed therebetween, A switching element having a gate electrode integral with the gate line, a source electrode connected to the source region and a drain electrode connected to the drain region, an auxiliary capacitance electrode forming an auxiliary capacitance with the gate line, and the switching An organic resin insulation film covering the element and the auxiliary capacitance electrode, and a through hole formed in the organic resin insulation film in a matrix form in a region surrounded by the gate line and the signal line on the organic resin insulation film An array substrate having a plurality of pixel electrodes connected to the source electrode via
A counter substrate disposed opposite to the array substrate with a gap therebetween;
In a liquid crystal display device comprising a liquid crystal composition sealed between the array substrate and the counter substrate,
The auxiliary capacitance electrode is exposed from the organic resin insulating film through a common through hole with the source electrode, and is connected to the pixel electrode connected to the source electrode and the other pixel electrode adjacent to the gate line An active matrix type liquid crystal display element connected through the through-hole.
ソース電極はゲート線と重畳する位置まで延在される事を特徴とする請求項1に記載のアクティブマトリクス型液晶表示素子。2. The active matrix liquid crystal display device according to claim 1, wherein the source electrode extends to a position overlapping with the gate line. スルーホールはゲート線の内側の領域上に形成される事を特徴とする請求項2に記載のアクティブマトリクス型液晶表示素子。3. The active matrix type liquid crystal display device according to claim 2, wherein the through hole is formed on a region inside the gate line. 有機樹脂絶縁膜とソース電極及び補助容量電極の層間には無機絶縁膜が形成され、前記ソース電極及び前記補助容量電極はそれぞれに対応して形成されたスルーホールを介して前記無機絶縁膜より露出される事を特徴とする請求項1に記載のアクティブマトリクス型液晶表示素子。An inorganic insulating film is formed between the organic resin insulating film, the source electrode, and the auxiliary capacitance electrode, and the source electrode and the auxiliary capacitance electrode are exposed from the inorganic insulating film through through holes formed correspondingly. The active matrix type liquid crystal display element according to claim 1, wherein: 有機樹脂絶縁膜は着色層であることを特徴とする請求項1乃至請求項4のいずれかに記載のアクティブマトリクス型液晶表示素子。5. The active matrix type liquid crystal display element according to claim 1, wherein the organic resin insulating film is a colored layer.
JP13512598A 1998-05-18 1998-05-18 Active matrix type liquid crystal display device Expired - Fee Related JP4031105B2 (en)

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