JP4027963B2 - Optical disk device - Google Patents

Description

  The present invention relates to a disk recording medium synchronization detection and protection method and a disk recording apparatus, and more particularly to an ADIP system disk recording medium synchronization detection and protection method such as DVD + RW, and recording on both ADIP system optical disks and LPP system optical disks. The present invention relates to an optical disk recording apparatus.

  In recent years, high-density recording media such as DVD (Digital Versatile Disk) with dramatically improved recording density have been put to practical use, and DVD-RAM, DVD-R / RW, and DVD + RW discs have been developed. Yes. For example, as described in Patent Document 1, in DVD-R / RW, an address corresponding to a sync signal or a track position in a prepit carved in a land track on a disc for a fixed period of wobble. A land pre-pit (LPP) method in which information is modulated is adopted. On the other hand, the DVD + RW employs an ADIP (ADdress In Pregroove) method in which address information corresponding to a synchronization signal or track position is wobble phase modulated.

  The ADIP system of DVD + RW will be described with reference to FIGS. First, the relationship between the ADIP method and the data method will be described with reference to FIG. Two sync frames, which are data recording units to be recorded on tracks on the disc, contain 93 wobbles, and data indicating “0” or “1” included in the first 8 wobbles is called an ADIP bit. Since one sector is composed of 26 sync frames, 13 ADIP bits are included in one sector. Further, since one ECC (Error Correcting Code) block is composed of 16 sectors, 208 ADIP bits are included in one ECC block. Here, since the ADIP word (= address) is composed of 52 ADIP bits, the ADIP word (= address) is included by being wobble-modulated at a rate of one for every four sectors. That is, four addresses are included in one ECC block.

  The ADIP word configuration is shown in FIG. The ADIP word is one address in units of a total of 52 ADIP bits including sync bits (1 ADIP bits), 23 ADIP bits indicating address information, AUX data (8 ADIP bits) indicating disk information, and parity bits (20 ADIP bits) which are correction codes. Is configured. This address is composed of 13 words (1 word = 4 bits), and a parity word of 5 words (= 20 ADIP bits) for information of 8 words (a total of 32 ADIP bits of sync bits, address information, and disk information). Can be added to correct errors in address information and AUX information of up to 2 words.

  In the ADIP system, the relationship between the wobble frequency fc and the recording frequency fa is (fa = 32 × fc). That is, 32T (T is a channel bit which is a basic unit of the recording mark length on the optical disk, T = 26.16 MHz), and is 1 wobble. There are three types of wobble modulation patterns in the ADIP system as shown in FIGS. FIG. 4 (a) is a diagram showing a synchronization signal (hereinafter referred to as word sync) indicating the head of the ADIP word. FIGS. 5 (a) and 6 (a) show ADIP bits “1” and “1”, respectively. It is a figure which shows ADIP data containing the wobble which shows 0 ". Of the 8 wobbles included in the ADIP data shown in FIG. 5 or FIG. 6, the first 1 wobble is a synchronization signal (hereinafter referred to as a bit sync) indicating ADIP data head, and the last 4 wobbles are ADIP bits. . The ADIP data includes a phase inversion unit (phase 180 degrees), and indicates whether the word sync, the bit sync, or ADIP data “0” or “1” depends on the position of the phase inversion unit. Synchronization in disc rotation control can be achieved using this word sync or bit sync, and a recording track can be specified using address information in the ADIP word.

  However, Patent Document 1 does not disclose a technique for acquiring ADIP data after performing synchronization protection using a word sync and a bit sync.

  In addition, as described above, since the recording format of the address information is different between the LPP optical disc and the ADIP optical disc, an LPP compatible recording device is required to perform recording on the LPP optical disc, In order to perform recording on an ADIP optical disk, a recording device compatible with the ADIP system was required.

JP 2001-110061 A

  As described above, in the rotation control of the ADIP optical disk, the data pattern and the detection timing are different between the word sync and the bit sync. In the prior art that does not perform synchronization protection, there is a risk of erroneous detection of word sync, bit sync, and ADIP bits. Accordingly, it is a first object of the present invention to correctly detect the ADIP bit while performing detection and protection for the two synchronization signals.

  Further, if writing is continued when an abnormality in the ADIP word is detected, there is a risk that recording at an incorrect position on the disc and destruction of recorded data will occur. Therefore, it is a second object of the present invention to provide a recording control method for preventing destruction of recorded data.

  Furthermore, recent optical disc recording devices have realized the added value of realizing a multi-optical disc drive that records and plays back various types of write-once and rewritable optical discs such as DVD, CD-R, and CD-RW. It is an important factor to decide. A dedicated circuit that constitutes the inside of the recording apparatus and handles signal processing for each optical disk includes a logic circuit for performing signal processing according to the format of the optical disk. Therefore, there is a problem that it is not possible to cope with signal processing for an optical disk that is not assumed at the time of circuit design. As a method of improving this, a method of providing a plurality of dedicated circuits corresponding to each format or a method of employing a dedicated circuit corresponding to a plurality of formats can be considered. However, the former is disadvantageous in terms of cost because the circuit scale is large, and the latter requires a redevelopment of logic circuits, which is very disadvantageous in terms of the difficulty of early development of multi-optical disc drives and the cost. It becomes. Accordingly, it is a third object of the present invention to provide a recording apparatus that can handle both LPP and ADIP optical discs at an early stage without enlarging the circuit scale.

  The above problem is that, in the reproduction wobble signal from the wobble phase modulation type optical disc, the first and second synchronization signals that are phase-modulated have different appearance periods and patterns, and the first and second synchronization signals are different from each other. In the detection, a synchronization detection protection method for performing period protection for the first synchronization signal from the phase modulation unit of the reproduction wobble signal and performing period protection for the second synchronization signal using the detection result of the first synchronization signal Is improved.

  Also, a reproduction land pre-pit signal reproduced from the disc, means for outputting the reproduction wobble signal, means for detecting address information included in the land pre-pit signal and controlling recording on the disc, and reproduction wobble signal Detecting and protecting the first and second synchronization signals and detecting data bits from the second synchronization signal detection; and error correction means for address information on the disk in a plurality of data bit arrays; Conversion means for outputting the generated land pre-pit signal from the corrected address information, etc., reproduction land pre-pit signal, generated land pre-pit signal output selection means, and conversion according to the number of consecutive undetected first sync signals This can also be improved by an optical disk recording apparatus provided with control means for controlling output stop of the means.

  According to the present invention, it is possible to improve the problem of erroneous detection of word sync, bit sync, and ADIP bits in signal processing of an ADIP format optical disc, and to detect correct values of data bits. Further, it is possible to avoid a recording operation at an incorrect position on the disc, prevent destruction of recorded data on the disc, and protect the disc. Furthermore, an optical disc recording apparatus capable of recording and reproducing both ADIP and LPP discs can be configured.

  An embodiment in which the present invention is applied to an optical disk recording apparatus that records and reproduces optical disks of the ADIP system and the LPP system will be described with reference to FIG. In FIG. 1, 1 is an optical disk, 2 is a spindle motor that rotationally drives the optical disk 1, 3 is an optical pickup that records or reproduces data on the optical disk 1, and 4 is a laser driver that controls a semiconductor laser included in the optical pickup. 5 is a regenerative amplifier, 6 is a microcomputer for controlling the operation of the entire drive, 7 is an optical disk control circuit for controlling recording of a disk, 8 is an ADIP demodulator, 9 is a modulator for performing digital modulation processing on ECC data Reference numeral 10 denotes an LPP decoder that outputs address information for a track position on a recording target disk as a detected ECC address.

  The recording address information on the optical disk 1 is reproduced by the optical pickup 3, and a signal detected by a photo detector (not shown) is supplied to the reproduction amplifier 5. The output signal of the regenerative amplifier 5 is supplied to the ADIP demodulator 8. In the regenerative amplifier 5, the detection signal of the photodetector is calculated and a tracking error signal and a focus error signal are generated. In the case of an ADIP disc, the wobble signal is supplied. In the case of an LPP disc, the LPP signal is supplied to the ADIP demodulator 8.

  When the optical disk 1 is of the LPP method, an LPP signal is output from the reproduction amplifier 5 and input to the LPP decoder 10 of the optical disk control circuit 7 via the switch 21. The LPP decoder 10 can obtain LPP address information and the like.

  On the other hand, when the optical disc 1 is of the ADIP system, a wobble signal is output from the reproduction amplifier 5 and input to the ADIP demodulator 8. The ADIP demodulator 8 obtains address information through the phase modulator detector 11, the data bit detector 14, the data bit period protector 17, the data latch 24, and the error corrector 23. In order to output the obtained address information as the LPP method, the LPP signal generation unit 22 performs ADIP-LPP conversion. The converted data is output to the LPP decoder 10 via the switch 21 as a generated LPP signal. The error correction unit 23 performs error correction of ADIP data, and continuity check of the obtained ADIP address and the previous and previous ADIP addresses. Here, the switch 21 is included in the ADIP demodulator, but the present invention is not limited to this, and the switch 21 may be provided outside the ADIP demodulator.

  The word sync detection unit 12, the word sync cycle protection unit 15, and the word counter 18 can obtain a period-protected word sync. The bit sync detection unit 13, the bit sync cycle protection unit 16, the word counter 18, and the 2-frame counter According to 19, a cycle-protected bit sync can be obtained. The data bit cycle protector 17 is controlled by the cycle-protected bit sync and the 2-frame counter 19. The abnormality detection unit 20 stops the operation of the LPP signal generation unit 22 when an abnormality is detected by the word sync cycle protection unit 15 and the bit sync cycle protection unit 16, and outputs a low level without outputting the generated LPP signal. Or keep it high. The LPP stop signal of the abnormality detection unit 20 is also transmitted to the microcomputer 6, and the microcomputer 6 transmits a signal to each unit so as to stop the recording operation.

  Next, details of the operation of the ADIP demodulator 8 when playing back an ADIP optical disk will be described. In the phase modulation unit detection unit 11, the regenerative amplifier 5 detects a phase inversion unit (a switching unit between phase 0 degrees and phase 180 degrees) from the regenerated wobble signal. As shown in FIG. 4B, the input signal input to the phase modulation unit is a signal obtained by binarizing the reproduced wobble signal into “0” and “1” according to the amplitude level. As shown in FIG. 4B, the portion where the phase is switched has a width of 32T. Others change at 16T. The phase modulation detector detects the rise and fall of the 32T width.

  The detection signal having a width of 32T obtained by the phase modulation unit is input to the word sync detection unit 12, the bit sync detection unit 13, and the data bit detection unit 14. Each detection unit detects any of the three wobbles shown in FIGS. 4-6 and outputs a word sync, a bit sync, and a data bit separately. The characteristics of the three patterns are as follows.

  In FIG. 4B showing the word sync, the phase is switched at 4 wobbles (128T) from the rise of 32T to the fall of 32T. In FIG. 5B showing the bit sync, the phase is switched by 1 wobble (32T) from the rise of 32T to the fall of 32T. The data bits “0” and “1” are switched in phase by 2 wobbles (64T) from the rise of 32T to the fall of 32T. By detecting these three patterns of wobble separately, a word sync, a bit sync, and a data bit can be detected.

  Next, the word sync detection unit 12, the bit sync detection unit 13, and the data bit detection unit 14 will be described. First, FIG. 7 shows a timing chart of the word sync detector 12, and a detection method will be described. (A) is a binarized wobble signal reproduced by the regenerative amplifier 5, (b) is a 32T rising detection signal output from the phase modulation unit 11, and (c) is an output from the phase modulation unit 11. This is a 32T falling detection signal. (D) The determination counter is provided in the word sync detection unit 12, and (b) is cleared to 0 when the rising edge is detected. (D) The word detection window is opened with a window width of ± yT (y is an integer value) centered on 4 wobbles (128T) of the phase change width of the word sync according to the counter value of the determination counter of (d). . The set value of the window width can be varied by the microcomputer 6 in FIG.

  When the word sync detection window is open and (c) a falling detection signal is present, (h) an unprotected word sync is detected. Unprotected means that the word sync is not yet cycle-protected, and is distinguished from the cycle-protected word sync. (E) The word sync detection window is closed when (c) a falling edge is detected.

  The bit sync and data bit detectors 13 and 14 also change the detection timings of the detection windows (f) and (g), respectively, so that the unprotected bit sync or Data bit detection can be realized. In the example of FIG. 7, (d) the determination counter is shared by the word sync, bit sync, and data bit detection units 12, 13, and 14. (D) According to the determination counter, (f) the bit sync detection window has a window width of ± yT at the center of 1 wobble (31T), and (g) the data bit detection window has a width of ± w at the center of 2 wobbles (63T). yT window width. In the example of FIG. 7, since (c) there is no falling detection signal (Low) while the detection window is open, (i) unprotected bit sync and (j) unprotected data bits are not detected. . (D) Although the determination counter is provided in one place in the word sync detection unit 12, it may be provided in the bit sync detection unit 13 and the data bit detection unit 14, respectively. Further, the window width may be variable. This is for increasing the detection accuracy for each pattern.

  Next, the cycle protection of the word sync, the bit sync, and the data bit will be described. FIG. 8 shows a timing chart of the word sync cycle protection unit 15 and the word sync cycle protection method will be described. The word sync cycle protection unit 15 is provided to periodically protect the unprotected word sync detected by the word sync detection unit 12. (A) is an unprotected word sync which is the output of the word sync detector 12. (B) is a 2-frame counter, and (c) is a word counter. The 2-frame counter counts 0 to 2975T (0 to 93 wobbles) for two sync frames. The word counter counts 52 ADIP bits from 0 to 51. Each ADIP bit is sequentially stored in a data latch, forming an ADIP word. (D) is a word sync cycle protection window. In the initial state before entering the word sync (when no unprotected word sync is found yet), the period protection window is open (full open), and the first unprotected word sync is searched. (D) If the word sync cycle protection window is open and (a) there is an unprotected word sync, the word sync is detected and the word sync cycle protection window (d) is closed as shown in (e). . When the first word sync is detected, (b) a value is loaded into the 2-frame counter, and (c) the word counter is cleared to zero. (B) The value loaded into the 2-frame counter is 3 wobbles (96T), which is the difference between the appearance positions of the word sync and the bit sync. This is the difference in appearance position between the phase modulator 2 of the word sync shown in FIG. 4 and the phase modulator 2 of the bit sync shown in FIG. (C) The word counter is counted up to 51 every time the value of (b) 2 frame counter is cleared to 0.

  After the first word sync is found, the period protection window has a width centered on (c) 51 word counter value and (b) 2 frame counter value 93 wobble (2975T) in order to find the next word sync. Open at ± zT (z is an integer). The width of the period protection window can be changed by the microcomputer 6.

  As shown in FIG. 2, since one word sync is included in the ADIP word, the distance from the word sync to the next word sync is 1 ADIP word (93 wobbles × 52 ADIP data). Therefore, after the word sync at the head of the ADIP word is cyclically protected, this value is counted, a window is opened in a timely manner, and the cycle of the wordsync is protected. For example, in FIG. 8A, an erroneously detected word sync exists between the second word sync and the third word sync. However, (d) when the word sync cycle protection window is closed, it is not regarded as a word sync. As described above, since the appearance period is predicted from the previous detection value by opening and closing the period protection window and performing period protection, the influence of erroneous detection is reduced and the reliability of the detection signal is increased.

  Next, a countermeasure when the word sync is not continuously detected a certain number of times will be described with reference to FIG. (F) indicates the number of consecutive undetected word syncs. In FIG. 8, the fourth (a) unprotected word sync does not exist, and no word sync is detected as shown in (e). In such a case, (d) when the word sync cycle protection window falls, (f) the number of consecutive undetected numbers is counted up. (F) If the number of consecutive undetections exceeds a certain value, (d) the word sync cycle protection window is fully opened and a word sync is searched. This is because if the word sync is not found, the position of the bit sync and the data bit cannot be specified. The bit sync cycle protection window is opened and closed while the word sync cycle protection window is closed. This is because the bit sync cannot be protected unless the word sync cycle is protected. Therefore, when the word sync is not detected continuously for a certain number of times, the period protection window is fully opened and the word sync is searched again. As a result, the problem that the word sync is not found and as a result the data value cannot be detected can be avoided early.

  Next, a method for stopping the generation of the LPP signal will be described with reference to FIG. If the number of consecutive non-detections is greater than or equal to the set value, it is assumed that there is an abnormality. In FIG. 8, as an example, the consecutive undetected number setting value is set to 3 times. The abnormality detection unit 20 stops ADIP-LPP conversion of the LPP signal generation unit 22 and stops the generated LPP signal. The LPP stop signal of the abnormality detection unit 20 is also transmitted to the microcomputer 6, and the microcomputer 6 transmits a signal to each unit so as to stop the recording operation.

  Next, the bit sync cycle protection unit 16 will be described. The bit sync cycle protection unit 16 is provided for cycle protection of the unprotected bit sync detected by the bit sync detection unit 13. FIG. 9 is a timing chart of the bit sync cycle protection unit 16, and the bit sync cycle protection method will be described. (A) is a word sync which is the output of the word sync cycle protector 15. (B) is an unprotected bit sync output from the bit sync detector 13. (C) is a 2-frame counter.

  As shown in FIG. 2, due to the structure of the ADIP word, after the word sync at the beginning of the ADIP word is cycle protected, the cycle protection of the bit sync that is 93 wobbles away from the beginning of the word sync to the beginning of the bit sync is performed. . For this reason, the word sync cycle protection unit 15 is configured to open the cycle protection window of the bit sync cycle protection unit 16 with the word sync protected by the cycle as a reference. After that, from the bit sync to the next bit sync, the cycle protection of the bit syncs separated by 93 wobbles is sequentially performed.

  In order to protect the cycle of the bit sync, it is first necessary to protect the cycle of the word sync. (A) When a word sync is detected, as described above, (c) the value 96 (3 wobbles) is loaded into the 2-frame counter. (D) is a cycle protection window of the bit sync. (D) The bit sync cycle protection window opens with a width ± zT with (b) 2 frame counter value 93 wobble (2975T) as the center value. The width of the period protection window can be changed by the microcomputer 6. (B) If an unprotected bit sync is found when (d) the period protection window is open, (e) a bit sync is detected as a protected bit sync. If it is detected, (d) the bit sync cycle protection window is closed, and (c) the 2-frame counter is cleared to zero.

  Next, a countermeasure when the bit sync is not continuously detected a certain number of times will be described with reference to FIG. (F) indicates the number of consecutive undetected bit syncs. The bit sync cycle protection unit 16 is provided with a counter that counts the number of consecutive undetected bit syncs. When the number of undetected times exceeds a certain value, (d) the bit sync cycle protection window is opened. The setting of the number of undetected times for opening the cycle protection window can be changed by the microcomputer 6. In FIG. 9, as an example, the continuous undetected number of times is set to three.

  A method may be used in which the bit sync detection window is expanded to search for a bit sync when the number of consecutive bit sync undetected times exceeds a certain value. This method has the advantage of knowing exactly which ADIP bit is not detected.

  If the number of consecutive undetected times is equal to or greater than the set value, it is determined that there is an abnormality, and (h) an LPP stop signal is sent to the abnormality detection unit 20. The abnormality detection unit 20 stops ADIP-LPP conversion of the LPP signal generation unit 22 and stops the generated LPP signal. The LPP stop signal of the abnormality detection unit 20 is also transmitted to the microcomputer 6, and the microcomputer 6 transmits a signal to each unit so as to stop the recording operation.

  Next, a countermeasure when the bit sync is not continuously detected a certain number of times will be described with reference to FIG. In FIG. 10, when the number of consecutive unsuccessful bit sync detections exceeds a certain value, the word sync cycle protection window is opened to search for a word sync. The setting of the number of undetected times for opening the cycle protection window can be changed by the microcomputer 6. In FIG. 10, the continuous undetected number of times is set to six. (F) When the number of bit sync consecutive undetected times is 6, (g) the word sync cycle protection window is opened. As shown in FIG. 2, the ADIP word has 4 address data in one ECC block. Therefore, when the bit sync is not continuously detected for a certain value or more, the word sync is found early. (G) The word sync cycle protection window is opened simultaneously, and (d) the bit sync cycle protection window is closed. As shown in FIG. 2, because of the configuration of the ADIP word, the bit sync cannot be protected unless the word sync cycle is protected.

  When this configuration is used, the number of consecutive bit sync undetections is preferably set to 8 or less. This is because the error correction unit 23 can correct errors up to 2 words (8 bits) in a continuous bit sync, but cannot correct errors beyond that.

  Next, the data bit period protection unit 17 will be described. The data bit cycle protection unit 17 is provided for cycle protection of unprotected data bits detected by the data bit detection unit 14. FIG. 11 is a timing chart of the data bit cycle protection unit 17, and the data bit cycle protection method will be described. (A) is a cycle sync-protected bit sync that is an output of the bit sync cycle protector 16. (B) is an unprotected data bit that is the output of the data bit detector 14. (C) is a 2-frame counter. (D) is a “0” data cycle protection window. (A) When the bit sync is cyclically protected, (c) the 2-frame counter is cleared to zero. (D) The “0” data cycle protection window is opened by (c) 2 sync frame count value 7 wobble (223T) ± zT (z is an integer). This is because the space between the phase modulation unit 2 and the phase modulation unit 3 in FIG. 5 is 7 wobbles. (D) “e” data bit “0” is detected when “0” data cycle protection window is open and (a) bit sync detection is present. (F) is a “1” data period protection window. The “1” data period protection window is opened by (c) 2 sync frame count value 5 wobble (159T) center value ± zT. This is because the space between the phase modulation unit 2 and the phase modulation unit 3 is 5 wobbles as shown in FIG. (F) When the “1” data cycle protection window is open and (a) the bit sync is detected, (g) the data bit “1” is detected. The data bit cycle protection unit 17 can sequentially obtain 51 ADIP data bits from the detection results of the word sync cycle protection unit 15, the bit sync cycle protection unit 16, and the data bit cycle protection unit 17.

  Next, a method for stopping the recording operation by stopping the LPP signal generation when an abnormality is detected will be described. As shown in FIG. 1, the abnormality detection unit 20 stops ADIP-LPP conversion of the LPP signal generation unit 22 and stops the generated LPP signal. The LPP stop signal of the abnormality detection unit 20 is also transmitted to the microcomputer 6, and the microcomputer 6 transmits a signal to each unit so as to stop the recording operation. As described above, as a method of determining abnormality detection, there is a method of stopping LPP signal generation when word sync and bit sync are not continuously detected. The period-protected word sync, which is the output of the word sync period protection unit 15, is input to the abnormality detection unit 20, and if the word sync is not continuously detected for a certain number of times, it is determined to be in an abnormal state. In addition, the cycle-protected bit sync that is the output of the bit sync cycle protection unit 16 is input to the abnormality detection unit 20, and when the bit sync is not continuously detected for a certain number of times, it is determined to be in an abnormal state. The continuous undetected number of times value can be set by the microcomputer 6.

  As another abnormality detection determination method, a method using an error uncorrectable signal will be described. The error correction unit 23 performs error correction on the ADIP data. An address continuity determination unit is provided in the error correction unit 23 to check whether there is continuity between the address value of the ADIP data subjected to error correction and the address value of the ADIP data detected last time and the last time. If the address value continuity is not established for a certain number of times, it is determined that the address state is abnormal, and the LPP signal generation unit 22 stops the LPP signal generation. This is because if the address value continuity is not established a certain number of times, the address value is likely to be incorrect. On the other hand, even if the address value continuity is not established, if it is less than a certain number of times, a predicted value is obtained based on the address value determined to have continuity in the previous time, and the value is input to the LPP signal generation unit 22. . Similarly, when the error correction unit 23 becomes unable to correct errors continuously, the LPP signal generation by the LPP signal generation unit 22 is similarly stopped. This is because the address value is likely to be incorrect. Since it is dangerous to record even if the address cannot be reproduced, the recording operation to the wrong position on the disk is avoided, the recorded data on the disk is prevented from being destroyed, and the disk is protected.

  As described above, the ADIP optical disc can detect two types of synchronization signals such as word sync and bit sync at the same time, and detect the correct value of the data bit while protecting the synchronization. In addition, by performing recording stop of the disk when recording, word sync, bit sync abnormality is detected, the recording operation to the wrong position on the disk is avoided, and the recorded data on the disk is prevented from being destroyed, The disk can be protected. Furthermore, by performing ADIP-LPP conversion, both ADIP and LPP discs can be recorded and reproduced, and an optical disc recording apparatus can be constructed.

1 is a block diagram showing the overall configuration of a disk drive according to an embodiment of the present invention. Outline diagram to show the address data system (ADIP word, ADIP bit) in the ADIP optical disk Outline diagram for explaining ADIP data on an ADIP optical disc Diagram showing word sync on ADIP optical disc The figure which shows ADIP bit = 1 in the ADIP system optical disk Diagram showing ADIP bit = 0 in ADIP optical disc Timing chart of word sync detection operation in one embodiment of the present invention Timing diagram of word sync cycle protection operation in one embodiment of the present invention Timing chart of bit sync cycle protection operation in one embodiment of the present invention Timing chart of bit sync cycle protection operation in one embodiment of the present invention Timing chart of data bit period protection operation in one embodiment of the present invention

Explanation of symbols

 DESCRIPTION OF SYMBOLS 1 ... Optical disk, 2 ... Spindle motor, 3 ... Pickup, 4 ... LD driver, 5 ... Reproduction amplifier, 6 ... Microcomputer, 7 ... Optical disk control circuit, 8 ... ADIP demodulation part, 9 ... Modulation part, 10 ... LPP decoder, 11 ... phase modulation detector, 12 ... word sync detector, 13 ... bit sync detector, 14 ... data bit detector, 15 ... word sync cycle protector, 16 ... bit sync cycle protector, 16 ... data bit cycle protect , 18... Word counter, 19... 2 frame counter, 20 .. anomaly detector, 21... Switch, 22... LPP signal generator, 2 3.

Claims (3)

An optical disk recording apparatus that performs data recording control on an optical disk of a wobble phase modulation system or a land pre-pit system,
Means for outputting a reproduction land pre-pit signal reproduced from the disc and a reproduction wobble signal;
Means for detecting address information included in the land pre-pit signal and controlling recording on the disc;
Detect and protect the first and second sync signals from the playback wobble signal,
Data detection means for detecting data bits from the second synchronization signal detection;
Error correction means for address information on the disk in a plurality of data bit arrays;
Conversion means for outputting the generated land pre-pit signal from the corrected address information;
A reproduction land pre-pit signal, and a generation land pre-pit signal output selection means;
An optical disk recording apparatus comprising: control means for controlling output stop of the conversion means according to the number of consecutive undetected times of the first synchronization signal. The optical disk recording apparatus according to claim 1,
The optical disc recording apparatus characterized in that the control means determines the number of consecutive occurrences of correction errors from the error correction means P (P is an integer) or more, and performs output stop control of the conversion means according to the determination. The optical disk recording apparatus according to claim 1,
The control means determines the number of consecutive occurrences of address value discontinuity after correction Q times (Q is an integer) or more,
An optical disc recording apparatus that performs output stop control of the conversion means in accordance with the determination.

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