JP4027544B2 - Driving circuit, display device using the same, and integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a driving circuit and an integrated circuit (hereinafter referred to as a driver IC) for driving a capacitive load such as a plasma display panel, and a display device using the same.
[0002]
[Prior art]
  The prior art will be described below using an example of the structure of a plasma display panel (hereinafter referred to as PDP).
[0003]
  FIG. 2 shows an overview of the PDP and each electrode.In FIG.PDP30,Scan drive circuit31,Scan electrodeY1 ... Ym,Sustain drive circuit32,Sustain electrodeX1 ... Xm,Address drive circuit33,Address electrodeR1, G1, B1... Rn, Gn, Bn,unitShows cell 34. One pixel is composed of three unit cells of R, G, and B. For example, in a PDP having a number of pixels (number of cells) of 1024 × 768, there are 768 scan electrodes and sustain electrodes, and 3072 address electrodes. Each of the electrodes (scan electrodes Y, sustain electrodes X, address electrodes R, G, B) connected to the unit cells 34 arranged in a matrix is controlled to emit light by a drive signal, and an image is displayed. is there.
[0004]
  The unit cell 34 to be lit is selected by the address electrodes (R1, G1, B1... Rn, Gn, Bn) connected to the address drive circuit 33 and the scan electrodes (Y1... Ym) connected to the scan drive circuit 31. In addition, by driving the scan drive circuit 31 and the sustain drive circuit 32, display discharge is performed between the electrodes (Y1... Ym) (X... Xm) connected to the drive circuits 31 and 32.
[0005]
  FIG. 3 shows a schematic cross-sectional view of the unit cell 34.
[0006]
  In FIG.Front glass substrate50,Dielectric layer51,Protective film52,Phosphor53, 54, 55,Scan electrode56,Sustain electrode57,Address electrode58,And the address electrodeAddress electrode adjacent to 5859, 60 are shown.
[0007]
  The main load when the address electrode 58 is driven by the address drive circuit is the capacitance Ca-a (= Ca between the address electrode and the address electrode).^- + Ca⁺ ) And the capacitance Ca-xy between the address electrode-scan electrode and the sustain electrode.
[0008]
  The power loss in actual discharge is very small, and most of the power loss at the address electrodes is due to charging / discharging of these (Ca-a, Ca-xy). It is well known that this power loss is large, and reduction is required in terms of both power consumption of the PDP and allowable loss of the driver IC.
[0009]
  Therefore, as disclosed in Japanese Patent Laid-Open No. 8-160901, a method of collecting charges by connecting a capacitor and a coil for collecting charges has been proposed.
[0010]
  FIG. 4 shows a configuration example of a drive circuit using a driver IC that has been used conventionally, and FIG. 5 shows an example of an operation waveform thereof.
[0011]
  In FIG.High voltage power supply65,Recovery capacitorCref,Recovery coilL,Low voltage power supply66,n output driver IC67,Low voltage input terminal68,Low voltage power terminal69,Low voltage GND terminal70,High voltage power supply terminal71,High voltage GND terminal72,Low pressure part73,High voltage logic74,High voltage output stage75,High voltage output terminalQ1 ... Qn,Panel capacityCp1 indicates Cpn.Recovery capacitorCref is an extremely larger capacity than Cp1 + Cp2 + ... + Cpn. The operation waveform indicated by VIC in FIG. 5 indicates the potential of the high-voltage power supply terminal 71, and the operation waveform indicated by Vout indicates the potential of the high-voltage output terminals Q1. Here, the low-voltage power supply refers to a power supply having a voltage value normally used in an LSI logic system, and is, for example, 3V to 5V. The high-voltage power supply refers to a power supply for driving a load having a large voltage value with respect to the low-voltage power supply, and is, for example, 40V to 70V in the PDP. This definition of high pressure and low pressure will be described below.
[0012]
  The configuration of the driver IC is simply shown for the low-pressure system.
[0013]
  First, the operation of the driver IC will be briefly described. The signal input from the low voltage input terminal 68 undergoes serial-parallel conversion by the low voltage unit 73 and is input to the high voltage logic unit 74. A level shift or the like is performed by the high voltage logic unit 74 to form a signal for driving the high voltage output stage 75. The panel capacitors Cp1... Cpn are charged and discharged from the high voltage output stage 75 via the high voltage output terminals Q1.
[0014]
  Next, the collection operation will be briefly described with reference to FIGS.
[0015]
  In the period t1 in FIG. 5, SW1 is off, SW2 is on, and the pull-up switch of the high-voltage output stage is on. At this time, charges flow from Cref having about half the potential of the high-voltage power supply 65 to the high-voltage power supply terminal 71 via SW2 and L. The potential of the high-voltage power supply terminal 71 whose initial state is the GND level ideally rises to the high-voltage power supply level due to LC resonance. Charge flows into the panel capacitors Cp1... Cpn through the pull-up switch of the high voltage output stage 75 turned on from the high voltage power supply terminal 71 and the high voltage output terminals Q1.
[0016]
  During the period t2, SW1 is turned on and SW2 is turned off. During the period t1, the portion of the panel capacitance Cp1... Cpn that does not reach the high voltage power supply level is charged.
[0017]
  During the period t3, SW1 is turned off and SW2 is turned on. At this time, the charges of the panel capacitors Cp1... Cpn flow into Cref via the high voltage output terminals Q1... Qn, the parallel diodes of the pull-up switch of the high voltage output stage 75, and the high voltage power supply terminals 71, L, SW2. As a result, the potentials of the high-voltage output terminals Q1... Qn and the high-voltage power supply terminal 71 are ideally lowered to the GND level due to LC resonance.
[0018]
  During the period t4, SW2 is turned off, the pull-up switch of the high-voltage output stage 75 is turned off, and the pull-down switch of the high-voltage output stage 75 is turned on. During the period t3, the potentials of the panel capacitors Cp1. The portion that does not reach the GND level is discharged.
[0019]
  As described above, the charge / discharge charges of the panel capacitors Cp1... Cpn are ideally all exchanged with Cref. There is also a reduction in loss by using LC resonance.
[0020]
[Problems to be solved by the invention]
  However, in the above-described conventional example, even a continuous high signal is notched for each pulse. That is, the loss increases by performing extra charge / discharge for the continuous high.
[0021]
  In addition, by oscillating the power supply voltage of the high-voltage logic unit 74 connected to the high-voltage power supply terminal 71 together with the high-voltage output stage 75, the parallel capacitance of the elements constituting the high-voltage logic unit 74 is also loaded. This parallel capacitance is in the order of several pF and cannot be ignored from the viewpoint of resonance conditions, resonance period, etc., and is disadvantageous for loss reduction.
[0022]
  Further, by swinging the power supply voltage of the high-voltage logic unit 74, the determination of the high-voltage logic is delayed from the Vth of the constituent elements and the operation of the high-voltage output stage 75 is delayed, which is disadvantageous for loss reduction.
[0023]
  Further, no measures are taken to prevent destruction of the driver IC 67 against charges flowing backward from the panel capacitors Cp1... Cpn. That is, there is a period in which there is no path for the charge flowing back from the panel capacitors Cp1... Cpn to escape through the parallel diodes of the pull-up switch of the high voltage output stage 75, and the potential of the high voltage output terminals Q1. As a result, the driver IC may be destroyed, and the loss reduction and the IC breakdown tolerance are not compatible.
[0024]
  Although ideally LC resonance, it is actually LCR resonance via the on-resistance of the pull-up switch of the high-voltage output stage 75, and this on-resistance is high, and depending on the conditions, the resonance condition is not entered. It is not considered that the loss reduction effect is reduced.
[0025]
  An object of the present invention is to provide a drive circuit and a driver IC that can reduce loss with respect to charging and discharging of a capacitive load, and a display device using the same.
[0026]
[Means for Solving the Problems]
  In order to achieve the above object, according to the present invention, a power recovery circuit including a capacitor and a coil and a first power supply terminal are connected, and a cathode is connected to the first power supply terminal between the first power supply terminal and the output terminal. In the drive circuit in which the first switch means having the first diode formed in parallel is connected and the capacitive load is connected to the output terminal, independently of the first power supply terminal connected to the first switch means, A second power supply terminal connected to a logic means for controlling the first switch means is provided, an N-type MOSFET is provided as the first switch means, and the N-type MOSFET is connected to the gate of the N-type MOSFET during a predetermined period at the time of power recovery. Means is provided for setting the output of the logic means to a high impedance state.
[0027]
  In order to achieve the above object, according to the present invention, a power recovery circuit including a capacitor and a coil and a first power supply terminal are connected, and a cathode is connected to the first power supply terminal between the first power supply terminal and the output terminal. In a drive circuit in which a first switch means having a first diode connected in parallel is connected and a capacitive load is connected to the output terminal, it is independent of the first power supply terminal connected to the first switch means. And a second power supply terminal connected to a logic means for controlling the first switch means, and a cathode of a second diode having an anode connected to the output terminal is connected to the second power supply terminal. Is.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
  Reference example of the present inventionWill be described with reference to FIG. 1, FIG. 6, FIG. 7, and FIG.
[0029]
  First,Reference example of the present inventionFor comparison, the internal configuration of the conventional high-voltage output stage 75 in FIG. 4 will be described with reference to FIG.
[0030]
  In FIG. 6A, a terminal connected to the high voltage power supply terminal 71.80,Terminal connected to high-voltage GND terminal 7281,Terminal connected to high voltage logic 7482, 83,Terminal connected to high voltage output terminal84,Pull-up switch located between terminals 80 and 8485,Parallel diode of pull-up switch 85 with anode connected to terminal 84 side86,Pull-down switch located between terminal 81 and terminal 8487,The anode is connected to the terminal 81 sideTapParallel diode of pull-down switch 8788 is shown. The pull-up switch 85 is turned on / off using the signal at the terminal 82 as a control signal. The relationship between the terminal 83 and the pull-down switch 87 is the same. The parallel diodes 86 and 88 are protection diodes for the switches 85 and 87.
[0031]
  Here, the current path from the terminal 80 to the terminal 84 can be selected to be conductive / non-conductive by turning on / off the pull-up switch 85, but the current path from the terminal 84 to the terminal 80 is always conductive by the parallel diode 86. .
[0032]
  A specific example is shown in FIG. The pull-up switch 85 in FIG. 6A is replaced with a high gate breakdown voltage high-voltage pMOSFET 89, and the pull-down switch 87 is replaced with a high-voltage nMOSFET 90. Since these MOSFETs usually have their own parallel diodes, the parallel diodes 86 and 87 are included in the circuit symbols of the MOSFETs 89 and 90, but are shown for convenience of explanation.
[0033]
  Next, using FIG.Reference example of the present inventionThe configuration of will be described.
[0034]
  FIG.Reference example of the present inventionThe internal circuit configuration of the high-voltage output stage 75 and the configuration of its peripheral circuitsWhat was shownIt is. In order to simplify the explanation, the high voltage output of the driver IC 67 is set to one output of Q1. The high voltage power supply terminal 71 of the driver IC 67 is connected to the high potential side of the high voltage power supply 65 via the switch means SW1 (for example, a semiconductor switching element). The high voltage GND terminal 72 of the driver IC 67 is connected to the GND potential side of the high voltage power supply 65. The high voltage power supply terminal 71 is connected to one end of the power recovery capacitor Cref via the power recovery coil L and the switch means SW2 connected in series. Further, the high voltage GND terminal 72 is connected to the other end of the recovery capacitor Cref. In the driver IC 67, a high voltage output stage 75 that drives the panel capacitor Cp 1 by the switch means 85, 96, 87 is connected between the high voltage power supply terminal 71 and the high voltage GND terminal power supply 72. That is, the terminals 80 and 81 of the high voltage output stage are connected to the high voltage power supply terminal 71 and the high voltage GND terminal 72, respectively. The output terminal 84 of the high voltage output stage 75 is connected to the high voltage output terminal Q1 of the driver IC. A panel capacitor Cp1 is connected to the high voltage output terminal Q1, and the panel capacitor Cp1 is charged / discharged by a voltage applied to the high voltage output terminal Q1. The high voltage output stage 75 is controlled by a high voltage logic unit 74 connected between the high voltage power supply terminal 71 and the high voltage GND terminal power supply 72. That is, in the high voltage logic unit 74, a plurality of outputs for outputting signals for driving the switch means 85, 96, 87 of the high voltage output stage 75 are connected to the input terminals 82, 95, 83 of the high voltage output stage 75, respectively. In the driver IC 67, the input of the high voltage logic unit 74 is connected to the output of the low voltage unit 73 that performs signal processing. Here, for simplicity, only one low-voltage input terminal is shown, but there are actually a plurality of terminals. For example, in addition to data input, data output, clock, and latch control terminals, there are power recovery control terminals that are one of the features of the present invention. The input of the low voltage unit 73 is connected to the low voltage input terminal 68 of the driver IC. A signal input from the outside to the low voltage input terminal 68 is input to the low voltage unit 73, subjected to signal processing such as serial-parallel conversion by the low voltage unit 73, and output from the low voltage unit 73. The output signal is input to the high voltage logic unit 74, subjected to signal processing such as level shift in the high voltage logic unit 74, and output as a drive signal for the high voltage output stage 75. The power source of the low voltage unit 73 is a low voltage power source 66 having a voltage lower than that of the high voltage power source 65. The high potential side and the GND side of the low voltage power supply 66 are connected to the low voltage power supply terminal 69 and the low voltage GND terminal 70 of the driver IC 67, respectively. The low-voltage unit 73 is connected between the low-voltage power supply terminal 69 and the low-voltage GND terminal 70 so that a voltage is applied from the low-voltage power supply 66. Cref is a large capacitance that maintains a substantially constant potential even when the charge / discharge charge of Cp1 moves.
[0035]
  The configuration of the high voltage output stage 75 will be described. In FIG. 6A, the switch means 96 serving as a backflow limit switch, the parallel diode 97 of the backflow limit switch means 96, and a terminal 95 for controlling the backflow limit switch 96 are newly added. That is, the backflow limiting switch means 96 is connected between the pull-up switch means 85 and the pull-down switch means 88 in series with these switch means. Specifically, one end of the pull-up switch means 85 is connected to the terminal 80 of the high voltage output stage 75. The other end of the pull-up switch means 85 is connected to one end of the backflow limiting switch means 96. The other end of the backflow limiting switch means 96 is connected to one end of the pull-down switch means 87. The other end of the pull-down switch means 87 is connected to the terminal 81 of the high voltage output stage 75. A diode is connected in parallel to each switch means. The directions of the diode 86 connected to the pull-up switch means 85 and the diode 88 connected to the pull-down switch means 87 are directions in which current flows from the other end of each switch means toward one end. On the other hand, the direction of the diode 97 connected to the backflow limiting switch means 96 is the direction opposite to the other diodes, that is, the direction in which current flows from one end of the switch means to the other end. As will be described below, the backflow limiting switch 96 can control the conduction / non-conduction of the current path from the terminal 84 to the terminal 80.
[0036]
  In FIG.Reference example of the present inventionAn example of the operation waveform is shown. In the figure, VIC indicates the potential of the high voltage power supply terminal 71, and Vout indicates the potential of the high voltage output terminal Q1.
[0037]
  The operation will be described with reference to FIGS.
[0038]
  During the period t1, SW1 is off, SW2 is on, SW85 is on, SW96 is off, and SW87 is off. Vout, whose initial state is the GND level, causes the charges stored in Cref to be SW2, L, high-voltage power supply terminal 71, terminals 80, SW85, SW96 due to LC resonance between L and Cp1 (+ parasitic capacitance such as driver IC). By flowing into Cp1 through the parallel diode 97, the terminal 84, and the high-voltage output terminal Q1, ideally, the voltage rises to the high-voltage power supply level. Similarly, the VIC rises ideally to the high voltage power supply level.
[0039]
  During the period t2, SW1 is on, SW2 is off, SW85 is on, SW96 is off, and SW87 is off. The amount that Vout and VIC do not reach the high voltage power supply level during the period t1 is charged from the high voltage power supply 65 via SW1.
[0040]
  During the period t3, SW1 is off, SW2 is on, SW85 is on, SW96 is off, and SW87 is off. In the conventional high voltage output stage 75 configuration (FIG. 6A), Vout is the LC resonance as shown by the broken line 100, and the charge stored in Cp1 is converted into the high voltage output terminal Q1, the parallel diode 86, the terminal 80, By flowing into Cref via the high-voltage power supply terminals 71, L, and SW2, ideally, the voltage drops to the GND level. Similarly, VIC ideally falls to the GND level. But,Reference example of the present inventionThen, since the backflow limiting switch 96 is turned off and the direction of the parallel diode is reversed, the current path from the terminal 84 to the terminal 80 can be made non-conductive so that the drop of the VIC can be suppressed. VIC drops to near the GND level.
[0041]
  During the period t4, SW1 is off, SW2 is off, SW85 is on, SW96 is off, and SW87 is off. Vout maintains the high voltage power supply level. In the conventional high-voltage output stage 75 configuration (FIG. 6A), Vout is discharged by using the SW 87 for the period in which Vout does not reach the GND level during the period t3 as indicated by the broken line 100.
[0042]
  During the period t5, SW1 is off, SW2 is on, SW85 is on, SW96 is off, and SW87 is off. Vout maintains the high voltage power supply level. In the conventional high voltage output stage 75 configuration (FIG. 6A), Vout here rises to the vicinity of the high voltage power supply level as shown by the broken line 100.
[0043]
  During the period t6, SW1 is on, SW2 is off, SW85 is on, SW96 is off, and SW87 is off. Vout maintains the high voltage power supply level. In the conventional high voltage output stage 75 configuration (FIG. 6 (a)), Vout is charged as much as it does not reach the high voltage power supply level during the period t5.
[0044]
  During the period t7, SW1 is off, SW2 is on, SW85 is off, SW96 is on, and SW87 is off. Vout is ideally grounded by the fact that the electric charge stored in Cp1 flows into Cref through the parallel diode 86 of the high voltage output terminals Q1, SW96, and SW85, the terminal 80, and the high voltage power supply terminals 71, L, and SW2 due to LC resonance. Descent to level. Similarly, VIC ideally falls to the GND level.
[0045]
  During the period t8, SW1 is off, SW2 is off, SW85 is off, SW96 is on, and SW87 is on. The portion that Vout does not reach the GND level during the period t7 is discharged using SW87.
[0046]
  FIG. 8 shows an example in which the switches 85, 96 and 87 in FIG. 1 are replaced with high voltage MOSFETs.In FIG.High gate high voltage pMOSFET89The source is connected to the terminal 80, the gate is connected to the terminal 82, and the drain is connected to the source of the high gate breakdown voltage high-voltage nMOSFET 98. In the high gate breakdown voltage high voltage nMOSFET 98, the drain is connected to the terminal 84 and the drain of the high voltage nMOSFET 90, and the gate is connected to the terminal 95. The high voltage nMOSFET 90 has a source connected to the terminal 81 and a gate connected to the terminal 83. A high gate breakdown voltage MOSFET is a MOSFET that can apply a high voltage equivalent to that between the source and drain between the gate and source by increasing the gate breakdown voltage and increasing the gate breakdown voltage. By using a high gate breakdown voltage MOSFET for the SW 96, the gate signal of the terminal 95 can be easily generated by the high voltage logic unit 74, and the configuration is simplified.
[0047]
  The parallel diodes 86, 97, and 88 are parasitic diodes inherently present in the MOSFETs 89, 98, and 90, respectively, as described above. In FIG. 8, the switch 86 is described as a high gate breakdown voltage high voltage nMOSFET, but this can be implemented by a high gate breakdown voltage high voltage pMOSFET.
[0048]
  Shown aboveReference example of the present inventionThus, when a continuous high pulse is output, it is possible to provide a driver IC that can suppress an increase in power loss without nicking the high-voltage output and reduce power loss.
[0049]
  The type of MOSFET isReference example of the present inventionWithout being limited to the above, if the direction of the parallel diode is noted, the same effect can be obtained with other switch elements.
[0050]
  Reference example of the present inventionWill be described with reference to FIGS.
[0051]
  FIG.Of the present inventionReference exampleAnd is characterized by the provision of a power supply terminal 105 for recovery. Note that the low-voltage system shown in FIG. 1 is omitted, and the parasitic capacitors 106 and 107 necessary for explanation are shown. In order to simplify the explanation, the high voltage output of the driver IC 67 is set to one output of Q1. The description overlapping with FIG. 1 is omitted.
[0052]
  There are a parasitic capacitance 106 of elements constituting the high voltage output stage 75 and a parasitic capacitance 107 of elements constituting the high voltage logic unit 74. These are each about several pF, and when viewed as a whole, they may be several hundred pF or more. In the power recovery system in which the voltage of the high-voltage power supply terminal 71 is vibrated, these parasitic capacitors 106 and 107 also become loads, and the load capacity increases compared to the case without power recovery. Therefore,Reference example of the present inventionThen, the power supply terminals of the high-voltage output stage 75 and the high-voltage logic unit 74 are provided, the high-voltage power supply terminal 71 directly connected to the high-voltage power supply 65 is connected to the high-voltage logic unit 74, and the recovery power supply terminal 105 connected to L is provided. Connected to the output stage 75, the load capacity at the time of power recovery is reduced by the parasitic capacity 107 of the elements constituting the high-voltage logic unit 74 from the conventional one.
[0053]
  FIG. 12 shows a configuration example of the high voltage logic unit 74. For simplification of description, only a portion for generating a control signal to be input to the terminal 82 for the pull-up switch 85 of the high-voltage output stage 75 is shown.
[0054]
  In FIG.Terminal connected to high voltage power supply terminal 71120,Terminal connected to high-voltage GND terminal 72121,Low-voltage input terminal that receives signals from the low-voltage section122,A high voltage output terminal for outputting a control signal to a terminal 82 and a terminal 95 for the pull-up switch 85 and the backflow limiting switch 96 of the high voltage output stage 75.123,High gate high voltage pMOSFET124, 125, High-voltage nMOSFET126, 127,Inverter128 is shown.
[0055]
  When outputting a low voltage to the high voltage output terminal 123, a low voltage is input to the low voltage input terminal 122. At this time, the high voltage nMOSFET 126 is turned off, and the high voltage nMOSFET 127 to which a high voltage is applied to the gate by the inverter 128 is turned on. As a result, the high gate breakdown voltage high voltage pMOSFET 124 is turned on and the high gate breakdown voltage high voltage pMOSFET 125 is turned off, so that a low voltage is output to the high voltage output terminal 123.
[0056]
  When a high voltage is output to the high voltage output terminal 123, a high voltage is input to the low voltage input terminal 122. At this time, the high voltage nMOSFET 126 is turned on, and the high voltage nMOSFET 127 to which a low voltage is applied to the gate by the inverter 128 is turned off. As a result, the high gate breakdown voltage high voltage pMOSFET 124 is turned off and the high gate breakdown voltage high voltage pMOSFET 125 is turned on, whereby a high voltage is output to the high voltage output terminal 123.
[0057]
  When the power supply terminals of the high-voltage output stage 75 and the high-voltage logic unit 74 are shared, when the power supply terminal voltage decreases to near the GND level and rises from the GND level, the voltage at the terminal 120 also temporarily decreases to near the GND level and rises. . Until this voltage reaches Vth (for example, about 5 to 15 [V]) of the high gate breakdown voltage high voltage pMOSFETs 124 and 125, the potential of the high voltage output terminal 123 is indeterminate. When the power supply terminals of the high voltage output stage 75 and the high voltage logic unit 74 are provided independently, the voltage at the terminal 120 is constant at the high voltage power supply level, and the above problem does not occur.
[0058]
  Shown aboveReference example of the present inventionThus, it is possible to provide a driver IC that increases the loss reduction effect by reducing the load during power recovery.
[0059]
  In addition, since the potential of the high-voltage logic unit 74 is stable, the signal for controlling the high-voltage output stage 75, which is the output of the high-voltage logic unit 74, is also stabilized, the operation of the output stage MOSFET can be accelerated, and resonance can be efficiently performed. Can be caused. That is, it is possible to provide a driver IC that enhances the loss reduction effect.
[0060]
  The internal circuit configuration of the high-voltage output stage 75 is not limited to that shown in FIG. 9, and the same effect can be obtained with the configuration of FIG. 8, for example.
[0061]
  Reference example of the present inventionWill be described with reference to FIGS.
[0062]
  FIG. 10 illustrates the present invention.Reference exampleAnd is characterized by the provision of a power supply terminal 105 for recovery. The low-voltage system and high-voltage logic unit 74 shown in FIG. 1 is omitted, and the backflow current protection diodes 111 and 112 necessary for explaining the present invention are shown. The anode of the diode 111 is connected to Q1, and the cathode is connected to the terminal 71. The anode of the diode 112 is connected to the terminal 110, and the cathode is connected to Q1. In order to simplify the explanation, the high voltage output of the driver IC 67 is set to one output of Q1. The description overlapping with FIG. 1 is omitted.
[0063]
  In a driver IC that drives a capacitor as a load, the withstand capability against current (hereinafter referred to as abnormal discharge) that flows backward from the load capacitance at an unexpected time is important.
[0064]
  In the power recovery method using the conventional IC, Cp1 is the period during which both SW1 and SW2 indicated by t4 in FIG. 5 are OFF, or the period when SW1 indicated by t1 and t3 in FIG. 5 is OFF and SW2 is ON. The path for releasing the electric charge flowing into the driver IC due to the abnormal discharge from the terminal is cut off or becomes high impedance. At this time, if abnormal discharge occurs, the potential of the high-voltage output terminal Q1 rises abnormally, leading to destruction of the driver IC 75. Therefore, in the present invention, the reverse current protection diodes 111 and 112 are provided, and the high voltage output stage 75 and the power terminal for abnormal discharge are provided. A high voltage power supply terminal 71 directly connected to the high voltage power supply 65 is connected to the cathode side of the reverse current protection diode 111, and a recovery power supply terminal 105 connected to L is connected to the output stage 75. By connecting the anode side of the reverse current protection diode 111 to the high voltage output terminal Q1, it is possible to always provide a charge extraction path for Cp1, Q1, the reverse current protection diode 111, the high voltage power supply terminal 71, and the high voltage power supply 65.
[0065]
  Shown aboveReference example of the present inventionThus, it is possible to provide a driver IC that can withstand an abnormal discharge while maintaining the power recovery effect.
[0066]
  The internal circuit configuration of the high-voltage output stage 75 is not limited to that shown in FIG. 10, and the same effect can be obtained with the configuration of FIG. 8, for example.
[0067]
  The present inventionThis embodiment will be described with reference to FIG.
[0068]
  FIG. 11 shows the high-voltage logic unit 74 and the parasitic capacitors 106 and 107 omitted in FIG. In order to simplify the explanation, the high voltage output of the driver IC 67 is set to one output of Q1 as in FIG. A description of the same points as those in FIGS. 1, 9, and 10 will be omitted. In the present invention, the high-voltage logic unit 74 and the abnormal-discharge high-voltage power supply terminal 71 are made common, and a recovery power supply terminal 105 is additionally provided.
[0069]
  Shown aboveThe present inventionBy sharing the high-voltage power supply of the high-voltage logic unit 74 and the backflow protection diode 111 with this embodiment,Reference example of the present inventionThis effect can be realized while simplifying the wiring of the driver IC 67.
[0070]
  The internal circuit configuration of the high-voltage output stage 75 is not limited to that shown in FIG. 11, and the same effect can be obtained with the configuration of FIG. 8, for example.
[0071]
  Reference example of the present inventionWill be described with reference to FIGS. 9 and 13 to 17.
[0072]
  The operation at the time of charging Cp1 will be described with reference to FIG.
[0073]
  The charge stored in Cref having a potential half that of the high-voltage power supply 65 flows into Cp1 through SW2, L, the recovery power supply terminal 105, the terminal 80, the pull-up switch 85, the terminal 80, and the high-voltage output terminal Q1. At this time, if the potential of the high voltage output terminal Q1 is higher than the potential of Cref in the LCR resonance due to the ON resistance of L, Cp1, and the pull-up switch 85 and the resistance is zero, it is ideal for a certain period. Rises to a voltage that is twice the potential of Cref, that is, the potential of the high-voltage power supply.
[0074]
  The resonance condition of LCR resonance is
    R <2√ (L / C)
It is. For this reason, the on-resistance of the pull-up switch 85 needs to be low. Further, the power loss at the LC resonance is basically zero, but when there is a resistance, there is a resistance loss. When the current value is I, the resistance loss is IR² Therefore, the on-resistance of the pull-up switch 85 needs to be low.
[0075]
  Therefore,Reference example of the present inventionThen, the on-resistance of the pull-up switch 85 is reduced by the configuration of FIG.
[0076]
  In FIG. 13, the parasitic capacitors 106 and 107 in FIG. 9 are omitted, and the pull-up switch 85 is replaced with a high gate breakdown voltage high-voltage nMOSFET 130 and the pull-down switch 87 is replaced with a high-voltage nMOSFET 90. The source of the high gate breakdown voltage high voltage nMOSFET 130 is connected to the terminal 84, the drain is connected to the terminal 80, and the gate is connected to the terminal 82. The source of the high voltage nMOSFET 90 is connected to the terminal 81, the drain is connected to the terminal 84, and the gate is connected to the terminal 83. A high gate breakdown voltage MOSFET is a MOSFET that can apply a high voltage between the gate and the source that is equivalent to that between the source and the drain. The on-resistance reduction by using the pull-up switch 85 as the high gate breakdown voltage high voltage nMOSFET 130 will be described below.
[0077]
  FIG. 14A shows the configuration of a part of the high-voltage logic unit 74 of FIG. 13, the high gate breakdown voltage high-voltage nMOSFET 130 and Cp1, and FIG. 14B shows the high gate breakdown voltage high-voltage nMOSFET 130 in the mode in which the high-voltage output level is high. An example of gate-source voltage characteristics with respect to the source potential is shown. At this time, for simplification of explanation, the potential of Cp1 is fixed to the GND level.
[0078]
  The potential of the terminal 105 changes from the GND level to the high voltage power supply level (assumed to be 50 [V] here), but the potential of the terminal 71 is fixed to the high voltage power supply level. Therefore, the gate applied voltage (= high voltage power supply level) for turning on the high gate breakdown voltage high voltage nMOSFET 130 is stably supplied to the gate G. At this time, the gate-source voltage with respect to the potential of the terminal 105 shows the characteristic of the straight line 116.
[0079]
  Next, in the case where the high-voltage output stage 75 and the power supply terminal of the high-voltage logic unit 74 are shared, the same ones as in FIGS. 14A and 14B are shown in FIGS.
[0080]
  The potential of the terminal 71 changes from the GND level to the high-voltage power supply level (assuming 50 [V] here). Therefore, the gate applied voltage for turning on the high gate breakdown voltage high voltage nMOSFET 130 also changes from the GND level to the high voltage power supply level and is supplied to the gate G. At this time, the voltage between the gate and the source with respect to the potential of the terminal 71 shows the characteristic of the straight line 115.
[0081]
  Next, in the case where a high gate withstand voltage high voltage pMOSFET 89 is used instead of the high gate withstand voltage high voltage nMOSFET 130, the same as those shown in FIGS. 14A and 14B are shown in FIGS.
[0082]
  The potential of the terminal 105 changes from the GND level to the high-voltage power supply level (here, assumed to be 50 [V]), and the potential of the terminal 71 is fixed to the high-voltage power supply level. The gate applied voltage (= GND level) for turning on the high gate breakdown voltage high voltage pMOSFET 89 is stably supplied to the gate G. However, since the source of the high gate breakdown voltage high voltage pMOSFET 89 is on the terminal 105 side, the gate-source voltage with respect to the potential of the terminal 105 shows the characteristic of the straight line 131.
[0083]
  FIG. 17 shows an example of the on-resistance characteristic of the pull-up switch with respect to the voltage at the voltage terminal to which the pull-up switch 85 of the high-voltage output unit 75 is connected, from FIGS. 14 (b), 15 (b), and 16 (b). Show.
[0084]
  A curve 117 is a characteristic of FIG. 14 in which the high gate breakdown voltage high voltage nMOSFET 130 is used as a pull-up switch, and the power supply terminals of the high voltage output stage 75 and the high voltage logic unit 74 are provided independently. A curve 118 is shown in FIG. 15 in which the high gate breakdown voltage high-voltage nMOSFET 130 is used as a pull-up switch, and the power supply terminals of the high-voltage output stage 75 and the high-voltage logic unit 74 are shared, and in FIG. It is a characteristic.
[0085]
  From FIG. 17, it can be seen that the ON resistance at the initial stage of recovery (when the voltage at the voltage terminal to which the pull-up switch of the high-voltage output unit 75 is connected is low) uses the high gate breakdown voltage high-voltage nMOSFET 130 as the pull-up switch. It can be seen that when the power supply terminal of the logic unit 74 is provided independently, a remarkably small value is shown.
[0086]
  Shown aboveReference example of the present inventionAs a result, it is possible to provide a driver IC that reduces the resistance at the initial stage of recovery and improves the power recovery effect and increases the power loss reduction effect.
[0087]
  The configuration of the high voltage output stage 75 is not limited to this. For example, the same effect can be obtained by replacing the high gate breakdown voltage high voltage pMOSFET 89 of FIG. 8 with a high gate breakdown voltage high voltage nMOSFET.
[0088]
  Reference example of the present inventionWill be described with reference to FIGS. 1, 18, 19, and 21. FIG.
[0089]
  FIG. 18 is a simple block diagram focusing on the PDP video system.
[0090]
  In FIG.PDP device140,Video signal input terminal141Video signal processing block connected to terminal 141142,Control block connected to video signal processing block 142143. Scan drive circuit31,Power recovery circuit of scan drive circuit 31146Sustain drive circuit32,Power recovery circuit of sustain drive circuit 32147,Address drive circuit according to the present invention33,Power recovery circuit of address drive circuit 33 according to the present invention148It is. These circuits 31, 146, 32, 147, 33, 148 are connected to the control block 143. High voltage power block145The power recovery circuits 146, 147, and 148 are connected to high-voltage power lines, respectively.149, 151, 150Connected with. Display panel (PDP)30It is. The low-voltage power supply and the GND line are omitted. In addition, the control signal line output from the control block is set to one for each block in order to simplify the drawing, and this indicates a plurality of control lines. Further, the power recovery circuit 146 of the scan drive circuit and the power recovery circuit 147 of the stint drive circuit may be omitted. In this case, the high voltage power line 149 is directly input to the scan drive circuit 31 and the high voltage power line 151 is directly input to the sustain drive circuit 32.
[0091]
  The video signal input from the input terminal 141 is input to the control block 143 after being subjected to processing such as A / D conversion in the video signal processing block 142. In the control block 143, control signals necessary for the scan drive circuit 31, the power recovery circuit 146, the sustain drive circuit 32, the power recovery circuit 147, the address drive circuit 33, and the power recovery circuit 148 are generated and input to the respective blocks. Each block applies a voltage to the display panel 30 according to the input control signal and signals from the power recovery circuits 146, 147, and 148 (address system is indicated by 160), and displays an image on the display panel 30.
[0092]
  FIG. 19 shows a block diagram of the power recovery circuit 148 of the address drive circuit 33. FIG. 19 is obtained by adding a SW control signal to a part of FIG. 1, and the description overlapping that described in FIG. 1 is omitted.In FIG.Power supply terminal connected to high-voltage power supply line 150155Control signal input terminal for controlling SW2 connected to control block 143156Control signal input terminal for controlling SW1 connected to the control block 143157,GND terminal158,Output terminal connected to the address drive circuit 33159.
[0093]
  FIG. 21 shows a simple configuration of the address drive circuit 33.
[0094]
  In FIG.n driver ICs67-1 to 67-n, N high voltage output terminals eachQ1-Qnhave. A signal from the power recovery circuit 148 is input from the input terminal 165 and supplied to the high voltage power supply terminal 71 of each driver IC 67. The high voltage output terminal group 166 of the address drive circuit 33 is connected to the display panel 30.
[0095]
  In FIG. 18, one power recovery circuit 148 and one address drive circuit 33 are shown. However, the driver IC 67 may be divided into several groups, and the power recovery circuit 148 may be provided for each group.
[0096]
  Here, the configurations of the driver ICs 67-1 to 67-n are the same as those of the driver IC 67 of FIG. 1, and the high-voltage output stage 75 is provided with a backflow limiting switch 96 to conduct / non-conduct a current path from the terminal 84 to the terminal 80. Control.
[0097]
  Shown aboveReference example of the present inventionThus, when a continuous high pulse is output, it is possible to provide a display device that can suppress an increase in loss without being stepped into a high-voltage output and reduce power loss. In addition, since power loss is reduced, power can be used for high image quality such as an increase in gradation, and a display device with high image quality can be provided.
[0098]
  Reference example of the present inventionWill be described with reference to FIGS. 9, 20, and 22.
[0099]
  FIG. 20 is provided with signal paths indicated by high-voltage power supply blocks 145 to 161 in addition to FIG. A duplicate description is omitted. In FIG. 9, the same description is omitted.
[0100]
  FIG. 22 is provided with a high voltage power supply terminal 167 in addition to FIG. The high voltage power supply block 145 is connected to the high voltage power supply terminal 71 of each driver IC 67-1 to 67-n through the high voltage power supply terminal 167. The signal supplied from the power recovery circuit 148 via the input terminal 165 is input to the recovery power supply terminal 105 of each driver IC 67-1 to 67-n.
[0101]
  Here, the configurations of the driver ICs 67-1 to 67-n are the same as those of the driver IC 67 of FIG. 9, and the high-voltage power supply terminal 71 and the recovery power supply terminal 105 are provided independently. In FIG. 20, one power recovery circuit 148 and one address drive circuit 33 are shown. However, the driver IC 67 may be divided into several groups, and the power recovery circuit 148 may be provided for each group.
[0102]
  Reference example of the present inventionAccording to the above, it is possible to reduce the load capacity at the time of power recovery by separating the power supply terminal of the high-voltage logic unit and the high-voltage output stage, and to efficiently resonate by speeding up the operation of the output stage MOSFET Therefore, it is possible to provide a display device with improved power loss reduction effect.
[0103]
  Reference example of the present inventionWill be described with reference to FIGS. 10, 20, and 22.
[0104]
  Reference example of the present inventionThe configuration of the driver IC 67 in the address drive circuit 33 is the same as the configuration of the driver IC 67 of FIG. 10 in the configuration similar to that of FIGS. 22 is omitted.
[0105]
  Reference example of the present inventionAccording to the present invention, it is possible to provide a display device having resistance against abnormal discharge while maintaining the effect of power recovery by separating the power supply terminals for abnormal discharge and the high-voltage output stage.
[0106]
  The present inventionThis embodiment will be described with reference to FIG. 11, FIG. 20, and FIG.
[0107]
  In the present embodiment, the configuration of the driver IC 67 in the address drive circuit 33 is the same as that of the driver IC 67 of FIG. 11 with the same configuration as that of FIGS. 20 and overlapping with FIG.
[0108]
  According to the present embodiment, by sharing the high voltage power source of the high voltage logic unit 74 and the backflow protection diode 111,Reference example of the present inventionThis effect can be realized while simplifying the wiring of the driver IC 67 and the surrounding wiring.
[0109]
  Reference example of the present inventionWill be described with reference to FIGS. 13, 20, and 22.
[0110]
  Reference example of the present inventionThe configuration of the driver IC 67 in the address drive circuit 33 is the same as the configuration of the driver IC 67 of FIG. 13 in the configuration similar to that of FIGS. 22 is omitted.
[0111]
  Reference example of the present inventionAccording to the above, by separating the power supply terminals of the high-voltage logic unit and the high-voltage output stage and using a pull-up switch as a high gate breakdown voltage high-voltage nMOSFET, the initial recovery resistance is lowered and the power recovery effect is improved. It is possible to provide a display device with improved display quality.
[0112]
  Reference example of the present inventionWill be described with reference to FIGS.
[0113]
  FIG. 23 shows the high-voltage output means 75 and the high-voltage logic unit 74 in FIG. 9 other than those shown in FIG. 6B, FIG. 8, FIG. 13 and FIG.Reference example of the present inventionIs shown.
[0114]
  The high voltage output means 75 generates a gate-source voltage when outputting a high voltage nMOSFET 900 corresponding to the pull-up switch 85, a parallel diode 86 inherently present inside the high voltage nMOSFET 900, and a high voltage power supply level HV (hereinafter referred to as HV level). A resistor 910 for preventing the voltage, a zener diode 920 for protecting the generated voltage from exceeding the gate-source breakdown voltage of the high-voltage nMOSFET 900, a high-voltage nMOSFET 90 corresponding to the pull-down switch 87, and a parallel diode 88 thereof.
[0115]
  The high-voltage logic unit 74 includes a level conversion circuit composed of the high gate breakdown voltage high-voltage pMOSFET and high-voltage nMOSFET shown in FIG. 12, a high-voltage diode 1231, and a high-voltage nMOSFET 1270.
[0116]
  The low-voltage logic circuit 73 mainly includes a shift register, a data latch circuit, and a low-voltage drive circuit 7300 as shown in FIG. The address data input to the data input terminal 68a is input to the low voltage driving circuit 7300 through the data latch circuit, and simultaneously passes through the shift register circuit and is output from the data output terminal 68b. A clock signal is input to the shift register, a latch control signal is input to the data latch circuit, and a power recovery control signal and the latched address data signal are input to the low voltage drive circuit.
[0117]
  Next, main circuit operations of the recovery circuit and the driver IC 67 used therefor will be described.
[0118]
  By using the pull-up switch 85 as a normal high-voltage nMOSFET 900 having a low gate breakdown voltage (for example, 5V), the time corresponding to t1 and t5 in FIG. 7 can be shortened as compared with the case where a high-voltage nMOSFET having a high gate breakdown voltage is used. Can do. As a result, the speed of the power recovery operation can be increased, so that highly efficient power recovery can be achieved even in a high-definition display having a large number of data lines.
[0119]
  The reason why the times t1 and t5 can be shortened is that the high gate withstand voltage high voltage MOSFET does not exhibit the full performance unless the voltage of the high voltage power supply level HV is applied between the gate and the source (high on-resistance and small operating current). This is because a normal high-voltage nMOSFET fully exhibits its performance when 5V is applied between the gate and source. In addition, since the gate oxide film is thin, the threshold voltage can be reduced, which is advantageous for speeding up.
[0120]
  However, when a normal high-voltage nMOSFET is used on the pull-up side of the high-voltage output stage 75, even if the circuit of FIG. The reason is described below.
[0121]
  In the first half of the power recovery period (corresponding to t3 and t7 in FIG. 7), the panel capacitors Cp1 to Cpn (for the sake of simplicity, only Cp1 and a circuit connected thereto are shown) are charged to the HV level. The charge stored in the panel capacitance Cpm needs to flow into the recovery capacitor Cref via the high voltage output terminal Qm, the parallel diode 86, the terminal 80, the high voltage power supply terminal 71, the inductor L, and the switch SW2. Then, ideally, the potential of Cpm drops to the GND level due to LCR series resonance.
[0122]
  At this time, when the level conversion circuit of FIG. 12 is used for the high-voltage logic unit, the voltage of the output terminal 123 needs to be set to the GND level. This is because if the high voltage nMOSFET 125 is kept on and the output voltage of the terminal 123 is kept at the HV level, the terminal 123 and the terminal 80 are connected via the resistor 910 inside the high voltage output stage 75, and the terminal 80 is connected to the terminal 80. This is because a current flows in the direction of, and a predetermined operation cannot be obtained. However, when the voltage of the output terminal 123 is set to the GND level, the charge of Cpm at the HV level flows into the terminal 123 through the resistor 910 and the terminal 901, and the efficiency of power recovery is significantly reduced.
[0123]
  So to prevent this,Reference example of the present inventionThen, a terminal 1230 is provided, and a high voltage diode 1231 is provided between a node corresponding to the terminal 123 and the terminal 1230. The anode and cathode of the high-voltage diode 1231 are connected to the node corresponding to the terminal 123 and the terminal 1230, respectively. Even when the high-voltage nMOSFET 127 is turned on and the node corresponding to the terminal 123 is set to the GND level, the node 123 and the terminal 123 are connected. There is no charge flowing into the side.
[0124]
  The terminals shown inside the driver IC 67, for example,TerminalReference numerals 120, 80, 1230, 83, 122, 1220, 1221, etc. are virtual terminals, and bonding pads or the like are not present there.
[0125]
  In addition to the above, in order for the driver IC 67 shown in FIG. 23 to operate normally as a power recovery driver IC, it is necessary to operate the high-voltage nMOSFETs 90 and 1270 appropriately. The contents of the operation will be described below with reference to FIG. The drive circuit 7300 includes a NOR circuit 7303, a NAND circuit 7304, and inverters 7305, 7306, and 7307. A power recovery control signal is input from a terminal 7301 and an address data signal is input from a terminal 7302, and four output signals pass through the logic circuit. Are input to terminals 122, 1220, 1221, and 83, respectively. When the GND level is output by the normal inverter circuit operation, the high voltage nMOSFET 90 is turned on, the high gate breakdown voltage high voltage pMOSFET 125 is turned off, the high voltage nMOSFET 127 is turned on, and when the HV level is output, the high voltage nMOSFET 90 is turned off. The high voltage pMOSFET 125 is turned on, and the high voltage nMOSFET 127 is turned off.
[0126]
  However, at times t3 and t7 (see FIG. 7) in the first half of the power recovery period, the high voltage nMOSFETs 90 and 1270 need to be turned off, the high voltage nMOSFET 127 should be turned on, and the high gate breakdown voltage high voltage pMOSFET 125 should be turned off in order not to disturb the power recovery operation. And does not match the normal inverter circuit operation.
[0127]
  In view of this, the power recovery control signal, which is normally at the GND level and the first half of the power recovery period, t3 and t7, and becomes the low voltage power supply level (hereinafter referred to as Vcc level) is used to obtain the logic from the address data signal and at times t3 and t7. The high voltage nMOSFETs 90 and 1270 and the high voltage nMOSFET 127 are turned off at the same time.
[0128]
  In FIG. 24B, when the power recovery control signal becomes the Vcc level, the outputs of the NOR circuit 7303 and NAND circuit 7304 are forcibly set to the GND level and the Vcc level, respectively, regardless of the address data signal. Therefore, GND, Vcc, GND, and GND level signals are input to the terminals 122, 1220, 1221, and 83, respectively, the high-voltage nMOSFET 126 is off, the high-voltage nMOSFET 127 is on (thus, the high gate breakdown voltage high-voltage pMOSFET 125 is off), and the high voltage The nMOSFET 1270 is turned off and the high voltage nMOSFET 90 is turned off.
[0129]
  When the power recovery control signal is at the GND level, the output voltage level is determined according to the address data signal, and the terminals 122, 1220, 1221 and 83 output the inverted, non-inverted, non-inverted and non-inverted signals of the address data signal, respectively. Thus, the normal inverter operation is realized.
[0130]
  When performing power recovery, the resonance frequency changes depending on the capacitance value of the panel capacitance Cp1 and the series resistance value of the circuit, and the values of the times t3 and t7 also change. The panel capacitance value varies depending on the panel manufacturer and the model of the panel. Since the same manufacturer and the same model change due to manufacturing variations, the pulse width of the power recovery control signal input from the external terminal of the driver IC 67 (terminal 68 in FIG. 1). Is appropriately adjusted in accordance with the capacity of the panel for power recovery, etc., the power recovery efficiency can be improved.
[0131]
  In FIG. 23, a high voltage nMOSFET 1270 assists the high voltage nMOSFET 90. When the output terminal Q1 is set to the GND level, the forward voltage drop of the Zener diode 920 appears transiently only with the high-voltage nMOSFET 90. Therefore, the output of the output terminal Q1 is pulled down to the GND level through the resistor 910 using the high voltage nMOSFET 1270. Therefore, when the forward voltage drop is not a problem, this can be eliminated.
[0132]
  The present inventionThis embodiment will be described with reference to FIGS. 25 and 26. FIG.
[0133]
  FIG. 25 is a circuit in which the circuit of the high voltage logic unit 74 in FIG. 23 is a constant current source driven type level conversion circuit instead of a level conversion circuit using a high gate breakdown voltage high voltage pMOSFET.
[0134]
  The high voltage logic unit 74 includes high voltage nMOSFETs 1260 and 1261, a high voltage pMOSFET 1250, a resistor 1251, and a Zener diode 1252 that constitute a current mirror circuit. The resistor 1251 and the Zener diode 1252 function in the same manner as the resistor 910 and the Zener diode 920 of the high-voltage output stage 75 described above.
[0135]
  FIG. 26 shows a schematic circuit configuration of the low-voltage logic circuit 73 in the case of the high-voltage logic circuit. Except for the low-voltage drive circuit 7310, it is the same as FIG. The low-voltage drive circuit 7310 mainly includes a constant current source 7315 for supplying a small current, a constant current source 7316 for supplying a large current, a logic circuit (not shown) for switching the current, and NOR circuits 7313 and 7314. Having a constant current source of two types, large and small, when the output voltage of the output terminal Q1 is switched (when rising or falling), the level conversion circuit is operated at high speed using a constant current source with a large current and switched. This is to reduce power consumption by changing to a constant current source with a small current in a later steady state. Both constant current sources are turned off when the output of the NOR circuit 7313 is at the Vcc level. Therefore, both constant current sources are turned off when the power recovery control signal becomes Vcc level. As a result, at times t3 and t7 in the first half of the power recovery period, the gate voltage of the high voltage pMOSFET 1250 is raised to the HV level, and the high voltage pMOSFET 1250 is turned off. Therefore, the output terminal 1232 of the high-voltage logic unit 74 is in a high impedance state and does not hinder the power recovery operation.
[0136]
  The present inventionThis embodiment will be described with reference to FIGS.
[0137]
  FIG. 27 is a circuit in which the high-voltage logic unit 74 in FIG. 23 is implemented by another circuit. In this embodiment, instead of providing the diode 1231 of FIG. 23, a high voltage nMOSFET 1272, a high gate breakdown voltage high voltage pMOSFET 1240, and a resistor 1241 are provided. This portion does not operate during normal inverter operation, and operates only when the power recovery control signal becomes Vcc level at times t3 and t7 in the first half of the power recovery period. Then, the gate voltage of the high gate breakdown voltage high voltage pMOSFET 125 is raised to the HV level, and the high gate breakdown voltage high voltage pMOSFET 125 is turned off.
[0138]
  As can be seen from FIG. 28B, when the power recovery control signal is at the HV level, the outputs of the NOR circuits 7323 and 7324 are both at the GND level, and both the high voltage nMOSFETs 126 and 127 are turned off. As a result, at time t3 and t7, the output terminal 123 of the high-voltage logic unit 74 is in a high impedance state and does not interfere with the power recovery operation.
[0139]
  Since the normal inverter operation is the same as that of the above-described embodiment, the description thereof is omitted.
[0140]
  Reference example of the present inventionWill be described with reference to FIG.
[0141]
  29, a high gate breakdown voltage high voltage pMOSFET 930 is provided in parallel with the high voltage nMOSFET 900 of the high voltage output stage 75 in FIG. 23, and its gate terminal 931 is output to another output terminal 1242 of the high voltage logic unit 74 (an inverted signal of the terminal 1230 is output). ). When a high-voltage nMOSFET is used as the pull-up side transistor of the high-voltage output stage 75, when the voltage at the output terminal Q1 rises and approaches the HV level when the output rises, the gate-source voltage becomes 5V or less and the load drive capability Decreases. As a result, the voltage reached at times t1 and t5 (see FIG. 7) in the latter half of the power recovery period is lowered, which affects the recovery efficiency. Therefore, the high gate breakdown voltage high voltage pMOSFET 930 is operated in parallel to prevent the ultimate voltage from being lowered. The configuration and operation of the low-voltage logic circuit 73 are the same as those in FIG.
[0142]
  Reference example of the present inventionWill be described with reference to FIGS. 30 and 31. FIG.
[0143]
  30 is obtained by adding a high gate breakdown voltage high voltage nMOSFET 98 (same as the high gate breakdown voltage high voltage nMOSFET 98 of FIG. 8) as the reverse current limiting switch means of FIG. 1 to the high voltage output means 75 in FIG. Its purpose isReference example of the present invention described aboveThis is the same as described in.
[0144]
  Therefore, only the high gate withstand voltage high voltage nMOSFET 98 of the high voltage output stage 75 corresponding to the output terminal outputting the GND level is turned on and the HV level output is output. That corresponding to the terminal needs to keep off.
[0145]
  ThereforeReference example of the present inventionThen, a high voltage nMOSFET 1280 and a resistor 1281 are added to the high voltage logic unit 74, and a NOR circuit 7334a and inverters 7338 and 7337a are added to the low voltage logic circuit.
[0146]
  Thus, when the output terminal Q1 is at the GND level, that is, when the address data signal in FIG. 31B is at the Vcc level, the output of the NAND circuit 7334a is at the Vcc level, and the high voltage nMOSFET 1280 is turned off. The gate voltage of the high voltage nMOSFET 98 is kept at the HV level. At times t3 and t7 in the first half of the power recovery period, since the potential of the terminal 80 is lowered from the HV level, a gate-source voltage is generated in the forward direction, and the high gate breakdown voltage high voltage nMOSFET 98 is turned on. For this reason, charge recovery of the panel capacitance Cp1 is performed. On the other hand, when the output terminal Q1 is at the HV level, that is, when the address data signal is at the GND level, the output of the NAND circuit 7334a is at the GND level when the power recovery control signal is at the Vcc level. As a result, a Vcc level signal is input to the terminal 1283 of the high voltage logic unit 74, the high voltage nMOSFET 1280 is turned on, and the gate voltage of the high gate breakdown voltage high voltage nMOSFET 98 is lowered to the GND level. Is preserved.
[0147]
  It should be noted that since the parallel diode 97 built in the high gate breakdown voltage high voltage nMOSFET 98 works when the output rises, the rise operation is not hindered.
[0148]
  Reference example of the present inventionWill be described with reference to FIGS. 32 and 33. FIG.
[0149]
  FIG. 32 shows a case where a high gate breakdown voltage high voltage pMOSFET 98a is used instead of the high gate breakdown voltage high voltage nMOSFET 98 of the high voltage output stage 75 in FIG.
[0150]
  Reference exampleHowever, the high gate breakdown voltage high voltage pMOSFET 98a that is turned off during normal operation is turned on only during the power recovery, and only the high gate breakdown voltage high voltage nMOSFET 98 of the high voltage output stage 75 corresponding to the output terminal that outputs the GND level is output to output the HV level. The circuit of the low voltage drive circuit 7340 is configured so that it corresponds to the output terminal and keeps off.
[0151]
  more than,Reference examples of the present invention and the present inventionIn this embodiment, the PDP has been described as an example. However, the present invention is not limited to this, and the present invention is applied to a display panel serving as a capacitive load such as an electroluminescent panel or a liquid crystal panel, or a driver IC for driving the display panel. It is valid.
[0152]
【The invention's effect】
  As described above, according to the present invention, it is possible to realize a display device including a capacitive load drive circuit and a driver IC suitable for reducing power loss, and a display panel serving as a capacitive load.
[0153]
  Specifically, power recovery efficiency can be improved. In addition, a high-speed power recovery circuit compatible with high-definition displaysCan be realized.
[Brief description of the drawings]
[Figure 1]Reference example of the present inventionDriver IC, recovery circuit.
FIG. 2 is a schematic view of a PDP and each electrode.
3 is a schematic sectional view of a unit cell 34. FIG.
FIG. 4 is a conventional example of a driver IC and a recovery circuit.
FIG. 5 is an operation waveform of a conventional example.
FIG. 6 shows a conventional high voltage output stage configuration.
[Fig. 7]Reference example of the present inventionWaveform of operation.
[Fig. 8]Reference example of the present inventionHigh voltage output stage configuration.
FIG. 9Reference example of the present inventionDriver IC, recovery circuit.
FIG. 10Reference example of the present inventionDriver IC, recovery circuit.
FIG. 11Of the present inventionExample driver IC and recovery circuit.
FIG. 12 shows a configuration example of a high voltage logic unit.
FIG. 13Reference example of the present inventionDriver IC, recovery circuit.
FIG. 14 shows a high gate breakdown voltage high voltage nMOSFET.
FIG. 15 shows a comparison of high gate breakdown voltage high voltage nMOSFETs.
FIG. 16 High gate breakdown voltage high voltage pMOSFET.
FIG. 17 shows recovery power supply voltage versus on-resistance characteristics.
FIG. 18Reference example of the present inventionDisplay device.
FIG. 19Reference example of the present inventionRecovery circuit.
FIG. 20Reference example of the present inventionDisplay device.
FIG. 21 shows a configuration example of an address drive circuit.
FIG. 22 shows an example of an address drive circuit configuration.
FIG. 23Reference example of the present inventionDriver IC, recovery circuit.
FIG. 24Reference example of the present inventionLow-voltage logic circuit inside the driver IC.
FIG. 25The present inventionThe driver IC and recovery circuit of the embodiment.
FIG. 26The present inventionThe low-voltage logic circuit in the driver IC of the embodiment.
FIG. 27The present inventionThe driver IC and recovery circuit of the embodiment.
FIG. 28The present inventionThe low-voltage logic circuit in the driver IC of the embodiment.
FIG. 29Reference example of the present inventionDriver IC, recovery circuit.
FIG. 30Reference example of the present inventionDriver IC, recovery circuit.
FIG. 31Reference example of the present inventionLow-voltage logic circuit inside the driver IC.
FIG. 32Reference example of the present inventionDriver IC, recovery circuit.
FIG. 33Reference example of the present inventionLow-voltage logic circuit inside the driver IC.
[Explanation of symbols]
  DESCRIPTION OF SYMBOLS 30 ... PDP, 33 ... Address drive circuit, 67 ... Driver IC, 71 ... High voltage power supply terminal, 73 ... Low voltage logic circuit, 74 ... High voltage logic part, 75 ... High voltage output stage, 85, 87, 96 ... Switch means, 86, 88, 97 ... Parallel diode, 89 ... High gate withstand voltage high voltage pMOSFET, 98 ... High gate withstand voltage high voltage nMOSFET, 106, 107 ... Parasitic capacitance, 108 ... Recovery high voltage power supply terminal, 111, 112 ... Reverse current protection diode, 117, 118 ... ON-resistance characteristics, 142 ... Video signal processing block, 143 ... Control block, 145 ... High voltage power supply block, 146, 147, 148 ... Recovery circuit, 7300, 7310, 7320, 7330, 7340 ... Low voltage drive circuit.

Claims (6)

A power recovery circuit including a capacitor and a coil and a first power supply terminal are connected;
Between the first power supply terminal and the output terminal, a first switch means having a first diode having a cathode connected to the first power supply terminal in parallel is connected, and a capacitive load is connected to the output terminal. In the connected drive circuit,
A second power supply terminal connected to a logic means for controlling the first switch means is provided independently of the first power supply terminal connected to the first switch means, and an N-type MOSFET is used as the first switch means. And a means for bringing the output of the logic means connected to the gate of the N-type MOSFET into a high impedance state when power is recovered to the capacitor . A power recovery circuit including a capacitor and a coil is connected to a first power supply terminal, and a first diode having a cathode connected to the first power supply terminal is connected in parallel between the first power supply terminal and the output terminal. In a drive circuit in which a first switch means having a connection is connected and a capacitive load is connected to the output terminal,
Independently of the first power supply terminal connected to the first switch means, a second power supply terminal connected to a logic means for controlling the first switch means is provided,
A drive circuit, wherein a cathode of a second diode having an anode connected to the output terminal is connected to the second power supply terminal. A power recovery circuit comprising a capacitor and a coil;
A high-voltage power supply,
An integrated circuit that drives the capacitive load of the display unit;
The integrated circuit is connected to the power recovery circuit and a first power supply terminal,
Between the first power supply terminal and the output terminal, a first switch means having in parallel a first diode having a cathode connected to the first power supply terminal,
A second power source connected to the logic means for controlling the first switch means independently of the first power supply terminal connected to the first switch means, wherein a capacitive load of the display unit is connected to the output terminal. A drive circuit provided with a terminal, wherein the first power supply terminal is connected to the power recovery circuit, the second power supply terminal is connected to the high-voltage power supply,
A display comprising: an N-type MOSFET as the first switch means; and means for bringing the output of the logic means connected to the gate of the N-type MOSFET into a high impedance state when power is recovered to the capacitor. apparatus. A power recovery circuit comprising a capacitor and a coil;
A high-voltage power supply,
An integrated circuit that drives the capacitive load of the display unit;
In the integrated circuit, the power recovery circuit and a first power supply terminal are connected, and a first diode having a cathode connected to the first power supply terminal is connected in parallel between the first power supply terminal and the output terminal. First switch means having,
A capacitive load is connected to the output terminal, and a second power supply terminal connected to a logic means for controlling the first switch means is provided independently of the first power supply terminal connected to the first switch means. Drive circuit,
The first power supply terminal is connected to the power recovery circuit, the second power supply terminal is connected to the high voltage power supply,
The display device according to claim 1, wherein the drive circuit has a cathode of a second diode having an anode connected to the output terminal connected to the second power supply terminal. In a circuit for driving a capacitive load, a first switch means having a first diode having a cathode connected to the first power supply terminal in parallel is connected between the first power supply terminal and the output terminal, Independently of the first power supply terminal connected to the first switch means, a second power supply terminal connected to a logic means for controlling the first switch means is provided,
An N-type MOSFET is provided as the first switch means, and means for setting the output of the logic means connected to the gate of the N-type MOSFET in a high impedance state during a predetermined period at the time of power recovery when recovering power to the capacitor. An integrated circuit comprising: In a circuit for driving a capacitive load, a first switch means having a first diode having a cathode connected to the first power supply terminal in parallel is connected between the first power supply terminal and the output terminal, Independently of the first power supply terminal connected to the first switch means, a second power supply terminal connected to a logic means for controlling the first switch means is provided,
An integrated circuit, wherein a cathode of a second diode having an anode connected to the output terminal is connected to the second power supply terminal.

Images