JP4021113B2 - Digital audio interface signal demodulator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital audio interface signal demodulating device that receives a digital audio interface signal used for data transmission between digital audio devices and demodulates the digital audio signal.
[0002]
[Prior art]
IEC (International Commission) -958 “Digital Audio Interface” and EIAJ (standards for transmitting digital audio signals between digital audio devices such as compact disc (CD), digital audio tape recorder (DAT), and mini disc (MD). Electronic Industries Association of Japan) -CP-1201 “Digital Audio Interface”.
[0003]
FIG. 10 shows an outline of a digital audio interface based on these standards. In the case of CD, DAT, MD, etc., the audio sample is composed of two channels, a left channel and a right channel. Two data units called subframes represent channel 1 and channel 2, and the two are a set. One sample is constituted, and the period of one sample corresponds to a period of exactly one sampling frequency FS. One block is composed of 192 samples.
[0004]
One subframe is composed of 64T periods, where T is 1/128 of the sampling period, and represents 32 bits of data. This T is the minimum inversion period of the digital audio interface signal. The content of one subframe is composed of a preamble of 8T (4 bits), preliminary data of 8T (4 bits), audio sample data of 40T (20 bits), and additional information of 8T (4 bits). Yes. The additional information includes a validity flag V, user bits U, channel status C, and parity P.
[0005]
Preliminary data other than the preamble, audio sample data, and additional information are biphase mark modulated. These are indicated by a sequence of 2T for 0 and 1T for 1 and have two patterns respectively according to the immediately preceding logic.
[0006]
The preamble is used to indicate the synchronization of subframes during transmission, and is configured to include 3T at the head, which is not used in biphase mark modulation, in order to obtain a unique periodic pattern. Using the periodic pattern, the block head of 192 frames and channel 1 and channel 2 can be distinguished. Hereinafter, the preamble is referred to as PA, the preamble having the B periodic pattern is referred to as the preamble PAb, the preamble having the B periodic pattern is referred to as the preamble PAm, and the preamble PAm having the M periodic pattern.
[0007]
FIG. 11 shows a conventional demodulator that demodulates the digital audio interface signal described above. A conventional digital audio interface signal demodulator DDAc includes a preamble detection circuit 101, an analog PLL circuit 102, and a biphase demodulation circuit 103.
[0008]
The preamble detection circuit 101 detects a 3T detection signal in the digital audio interface signal Sdai and outputs a preamble detection signal Spd. The PLL circuit 102 locks the phase to the preamble detection signal Spd and outputs a synchronous clock Ssc having a frequency 32 times higher.
[0009]
The bi-phase demodulation circuit 103 performs bi-phase demodulation of the digital audio interface signal Sdai using the synchronization clock Ssc and outputs a digital audio signal Sda.
[0010]
FIG. 12 shows the operation timing of the digital audio interface signal demodulator DDAc. As shown in FIG. 12, the preamble detection circuit 101 detects an inversion interval of 2.5T or more based on a reference clock Ssc having a period shorter than the minimum inversion interval of the digital audio interface signal Sdai, and outputs a preamble signal Spd. To do.
[0011]
The PLL circuit 102 forms an analog phase locked loop (PLL) using the VCO, compares the phase of the VCO divided by 32 and the preamble detection signal Spd, and outputs a synchronous clock Ssc having a frequency 32 times.
[0012]
The bi-phase demodulation circuit 103 outputs the digital audio signal Sda by punching out the digital audio interface signal Sdai with the synchronous clock Ssc and outputting 1 if different from the previous one and 0 if matching.
[0013]
As described above, the conventional digital audio interface signal demodulating device detects the preamble of the digital audio interface signal, generates a clock synchronized with the digital audio interface signal using an analog PLL, and generates a digital signal that is a biphase mark signal. The audio interface signal Sdai is demodulated.
[0014]
[Problems to be solved by the invention]
However, the digital audio interface signal demodulating device has the following problems caused by the analog PLL circuit. When an LSI is used, an analog PLL has a larger area size on the LSI than a digital circuit, and increases the LSI cost.
[0015]
In order to configure an analog PLL circuit, an analog circuit such as a VCO or a low-pass filter is required, and the number of parts increases. As a result, the integration of the PLL circuit and the digital audio interface signal demodulator cannot be increased, and the production cost is increased.
[0016]
The analog PLL circuit consumes a large amount of power, and the digital audio interface signal demodulator consumes a large amount of power, which is problematic in terms of energy saving. In particular, power consumption has a significant effect on battery life in portable devices.
[0017]
An analog PLL circuit is so large that it cannot be ignored over time that its performance or characteristics change over time. As a result, it is necessary to take measures against aging that occurs after being sold in an audio device.
[0018]
Furthermore, the conventional digital audio signal demodulating device requires a reference clock, a PLL clock, and two asynchronous clocks.
[0019]
These problems are obstacles to ensuring stability and reliability, miniaturization, ease of testing, and the like, especially when the digital audio signal demodulating device is made into an LSI. It should be noted that there is a problem that the circuit cannot be adapted to the wide frequency range of the input digital audio interface signal simply by making the circuit suitable for LSI implementation.
[0020]
The present invention solves the above-described conventional problems, and is a reference clock having a relatively low frequency that is not necessarily synchronized with an input digital audio interface signal without using an analog PLL circuit by being fully digitized. An object of the present invention is to provide a digital audio signal demodulating apparatus that can demodulate a digital audio interface signal and can be adapted to a wide frequency range.
[0021]
[Means for Solving the Problems and Effects of the Invention]
In order to achieve the above object, the present invention has the following features.
[0022]
A first aspect of the present invention is a digital audio interface signal demodulating device that adds a preamble and additional information to a digital audio signal and demodulates a digital audio interface signal transmitted by biphase modulation,
Each time the edge of the digital audio interface signal is detected based on the positive edge of the reference clock having a frequency higher than twice the minimum inversion frequency of the digital audio interface signal and not necessarily synchronized with the digital audio interface signal An edge detector for generating a detection signal and a second half detection signal indicating that there is an edge of the digital audio interface signal in the second half of the reference clock;
Each time the edge detection signal is input, the value obtained by counting the edge detection signal with the reference clock is obtained, and 1 is added to the value obtained by doubling this value if the second half detection signal is input, while the second half immediately before A count value calculator for calculating a half clock count value obtained by subtracting 1 if a detection signal is input;
An approximate 3T detector that obtains a value obtained by counting the edge detection signal with a reference clock every time the edge detection signal is input and detects a value that falls within a predetermined range to generate a first approximate 3T detection signal When,
A roughly 3T period detector that counts the period of the first roughly 3T detection signal with a reference clock to generate first 慨 3T period information;
A determinator for comparing the half clock count value with a predetermined table corresponding to the first approximately 3T detection signal to determine a modulation period of the digital audio interface signal and generating a determination signal;
A preamble detector that detects a preamble and generates a preamble detection signal based on the determination signal;
A bi-phase demodulator that demodulates and outputs a digital audio signal from the determination signal using the preamble detection signal as a timing reference;
[0023]
As described above, in the first invention, every time an edge detection signal is input, a value within a predetermined range is detected from the value obtained by counting the edge detection signal with the reference clock, and approximately 3T is detected. Approximate 3T period can be measured, and demodulated output can be obtained by table decision determined from the approximate 3T period, so that it can be adapted to a wide frequency range with only a low frequency reference clock without using PLL. it can.
[0024]
According to a second aspect of the present invention, in the first aspect, the edge detector is
A digital audio interface signal is punched with a reference clock to generate a first punch signal,
A digital audio interface signal is punched with an inverted clock of the reference clock, and a first inverted punch signal is generated by punching with the reference clock; and
An edge of the first punching signal is detected and an edge detection signal is output, and the second half detection signal is generated by exclusive-ORing the first punching signal and the first inverted punching signal.
[0025]
According to a third aspect of the present invention, in the first aspect, the digital filter further includes a digital filter that filters the first フ ィ ル タ リ ン グ 3T period information to generate second approximate 3T period information,
The determiner generates a determination signal by comparing the half clock count value with a predetermined table corresponding to the second approximate 3T period information.
As described above, in the third invention, even if the first approximate 3T period information is erroneously detected due to noise or the like, stable approximate 3T period information can be obtained, and the approximate 3T period information is slow. Since the fluctuation can be tracked, the determination of the period can be performed accurately in the determination device.
[0026]
According to a fourth aspect of the present invention, the first aspect further includes a limiter that outputs the second approximate 3T detection signal after suppressing the first approximate 3T detection signal for a predetermined period,
The approximately 3T period detector counts the period of the second approximately 3T detection signal with a reference clock.
[0027]
As described above, in the fourth invention, the limiter provided between the approximate 3T detector and the approximate 3T period detector detects the first approximate 3T even if the preamble 3Ts are close to each other. More accurate approximate 3T cycle information is output by adding a limit signal to limit the approximate 3T cycle information so that the approximate 3T detection signal is not output during a predetermined period from the fall of the approximate 3T detection signal. be able to.
[0028]
According to a fifth aspect of the present invention, in the first aspect, the limiter outputs the second approximate 3T detection signal after suppressing the first approximate 3T detection signal for a predetermined period;
A digital filter that filters the first approximate 3T period information to generate the second approximate 3T period information;
The approximately 3T period detector counts the period of the second approximately 3T detection signal with the reference clock,
The determiner generates a determination signal indicating the modulation period of the digital audio interface signal by comparing the half clock count value with a predetermined table corresponding to the second approximate 3T period information.
As described above, in the fifth aspect, the effects in the third and fourth aspects can be obtained simultaneously.
[0029]
A sixth aspect of the present invention is a digital audio interface signal demodulating apparatus that adds a preamble and additional information to a digital audio signal and demodulates a digital audio interface signal transmitted by biphase modulation,
Each time the edge of the digital audio interface signal is detected based on the positive edge of the reference clock having a frequency higher than twice the minimum inversion frequency of the digital audio interface signal and not necessarily synchronized with the digital audio interface signal An edge detector for generating a detection signal and a second half detection signal indicating that there is an edge of the digital audio interface signal in the second half of the reference clock;
Each time the edge detection signal is input, the value obtained by counting the edge detection signal with the reference clock is obtained, and 1 is added to the value obtained by doubling this value if the second half detection signal is input, while the second half immediately before A count value calculator for calculating a half clock count value obtained by subtracting 1 if a detection signal is input;
An approximately 3T detector for detecting a value of the half clock count value falling within a predetermined range and generating a third approximately 3T detection signal;
A roughly 3T period detector that counts the period of the third roughly 3T detection signal with a reference clock to generate first roughly 3T period information;
A determinator for determining a modulation period of the digital audio interface signal by generating a determination signal by comparing the half clock count value with a predetermined table corresponding to the first approximately 3T detection signal;
A preamble detector that detects a preamble and generates a preamble detection signal based on the determination signal;
A bi-phase demodulator that demodulates and outputs a digital audio signal from the determination signal using the preamble detection signal as a timing reference;
[0030]
As described above, in the sixth aspect of the invention, the edge of the digital audio interface signal is detected at both the positive and negative edges of the reference clock, and the count value at the half clock of the reference clock is obtained from this output to obtain a more accurate approximate 3T. Since it can be detected, more accurate approximate 3T cycle information can be output.
[0031]
According to a seventh aspect of the present invention, in the first aspect, the switch for switching the half clock count value between a plurality of predetermined tables corresponding to the first approximate 3T cycle information based on the first approximate 3T cycle information Is provided.
[0032]
As described above, according to the seventh aspect of the present invention, it is possible to provide a demodulator that operates so as to automatically change the determination criterion based on the count value output of the approximately 3T period detector and can be adapted to a wide frequency range. .
According to an eighth aspect of the present invention, in the first aspect, the modulation period is any one of 1 time, 2 times, and 3 times the reciprocal of the minimum inversion frequency.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
First, the basic concept of the digital audio interface signal demodulator according to the present invention will be described. As described above, the present invention solves the above-mentioned problems caused by the analog PLL circuit by configuring the digital audio interface signal demodulating apparatus with full digital. However, when full digitization is performed, the following new problems are expected to occur.
[0034]
First, in order to ensure control accuracy, the frequency of the reference clock must be set higher than when an analog PLL is used. As a result, the power consumption increases due to the high frequency, and the process cost increases because a high-speed process corresponding to the high frequency is required.
[0035]
Furthermore, only signals having a frequency within a certain range with respect to the frequency of the reference clock can be received. Therefore, in order to demodulate a plurality of digital audio interface signals having different frequencies, it is necessary to switch between a plurality of reference clocks having different frequencies corresponding to the frequency of the signal to be demodulated. As a result, the apparatus becomes complicated and costs increase.
[0036]
It is an object of the present invention to provide a digital audio interface signal demodulating apparatus that prevents problems expected to occur due to full digitization and solves problems inherent in a digital audio interface signal demodulating apparatus having a conventional analog PLL. Objective.
In order to describe the present invention in more detail, it will be described with reference to the accompanying drawings.
[0037]
(First embodiment)
The digital audio interface signal demodulator DDAp1 according to the first embodiment of the present invention will be described below with reference to FIGS. 1, 2, 3, and 4. FIG.
As shown in FIG. 1, the digital audio interface signal demodulator DDAp1 includes an edge detector 1, a count value calculator 2, an approximately 3T detector 3, an approximately 3T period detector 4, an nT determiner 5, a preamble detector 6, And a biphase demodulator 7.
[0038]
The edge detector 1 outputs a pulsed edge detection signal Sed each time an edge of the input digital audio interface signal Sdai is detected based on the positive edge of the reference clock Src, and digitally outputs the second half of the reference clock Src. The second half detection signal Sfd indicating that there is an edge of the audio interface signal Sdai is output.
[0039]
Each time the edge detection signal Sed is input, the count value calculator 2 counts the interval of the edge detection signal Sed based on the reference clock Src to obtain the edge interval count value Cei. Further, the count value calculator 2 adds 1 to the value obtained by doubling the edge interval count value Cei if the latter half detection signal Sfd is input, and 1 if the immediately preceding latter half detection signal Sfd is input. A half-clock count value Shc having a value obtained by subtracting is output.
[0040]
The approximate 3T detector 3 obtains an edge interval count value Cei (not shown) by counting the interval of the edge detection signal Sed based on the reference clock Src every time the edge detection signal Sed is input, and is determined in advance. If the count value falls within the range of the detected value, it is detected as approximately 3T, and an approximately 3T detection signal S3T is output. The predetermined value is experimentally determined to be an optimal value based on the fulfillment standard, the process capability of manufacturing the product, and the noise entering the transmission line.
[0041]
The approximate 3T period detector 4 counts the period of the approximate 3T detection signal S3T input from the approximate 3T detector 3, obtains an approximate 3T interval count value C3ta, and outputs the approximate 3T period information I3T.
[0042]
Based on the half clock count value Shc input from the count value calculator 2 and the approximate 3T period information I3T input from the approximate 3T period detector 4, the nT determiner 5 is n times T (n is an arbitrary value). A determination signal Sj indicating the determined pulse width nT is generated. In this embodiment, the boundary between 1T and 2T and the boundary between 2T and 3T are determined in accordance with the above-mentioned digital audio interface signal standard.
[0043]
The preamble detector 6 is based on the determination signal Sj input from the nT determiner 5, 3T, 1T, 1T and 3T array, 3T, 3T, 1T and 1T array, or 3T, 2T, 1T, And 2T array are detected and output as a preamble signal Spa.
[0044]
The bi-phase demodulator 7 starts the digital audio interface signal Sdai when the preamble detection signal Sp input from the preamble detector 6 becomes “L” based on the determination signal Sj input from the nT determiner 5. When 2 is 2T, “0” is output, while when 1T and 1T are continuous, “1” is output to obtain demodulated data. The biphase demodulator 7 further separates audio data from the obtained demodulated data and outputs a digital audio signal Sda.
[0045]
Note that the reference clock Src is input with a frequency shorter than half of the minimum inversion period (1T) of the digital audio interface signal Sdai, that is, at an arbitrary frequency higher than twice the minimum inversion frequency of the digital audio interface signal Sdai. It is not always necessary to synchronize with the digital audio interface signal Sdai. For example, a clock such as 16.9344 MHz can be used.
[0046]
Next, the operation of the edge detector 1 will be described in detail with reference to FIG. The edge detector 1 includes a flip-flop 1_01, a flip-flop 1_02, a flip-flop 1_03, a flip-flop 1_04, an exclusive OR element 1_05, and an exclusive OR element 1_06.
[0047]
The flip-flop 1_01 outputs a signal obtained by punching out the digital audio interface signal Sdai at the positive edge of the reference clock Src as the primary positive edge signal q1.
[0048]
The flip-flop 1_03 uses a signal obtained by punching out the primary positive edge signal q1 output from the flip-flop 1_01 at the positive edge of the reference clock Src as a secondary positive edge signal q2.
[0049]
The flip-flop 1_02 outputs a signal obtained by punching out the digital audio interface signal Sdai at the negative edge of the reference clock Src as a zero-order negative edge signal nq0.
[0050]
The flip-flop 1_04 outputs a signal obtained by further punching out the zero-order negative edge signal nq0 output from the flip-flop 1_02 at the positive edge of the reference clock Src as the zero-order positive edge signal nq1.
[0051]
The exclusive OR element 1_05 obtains an exclusive OR of the primary positive edge signal q1 input from the flip-flop 1_01 and the secondary positive edge signal q2 input from the flip-flop 1_03, and outputs it as the edge detection signal Sed. .
[0052]
The exclusive OR element 1_06 obtains an exclusive OR of the primary positive edge signal q1 output from the flip-flop 1_01 and the zero-order positive edge signal nq1 output from the flip-flop 1_04, and outputs it as the latter half detection signal Sfd. .
[0053]
Next, the operation of the edge detector 1 will be described in more detail with reference to the timing chart shown in FIG. First, a reference clock Src, which is a pulse signal having a predetermined period as shown in the figure, is input to the edge detector 1 and the count value calculator 2.
[0054]
In the figure, a digital audio interface signal Sdai having a high level portion and a low level portion as indicated by A, B, C, D and E is input to the edge detector 1. Hereinafter, they are referred to as a high level A portion, a low level B portion, a high level C portion, a low level D portion, and a high level E portion.
[0055]
The high level A section has a pulse width of about 6Hc (6Hcp or 6Hcf) counted by a half clock of the reference clock Src. Similarly, the low level B portion has a pulse width of about 7 Hc, the high level C portion has a pulse width of about 6 Hc, the low level D portion has a pulse width of about 7 Hc, and the high level E portion has a pulse width of about 12 Hc. Note that the pulse width is not necessarily an integral multiple of the half clock width of the reference clock.
[0056]
In the edge detector 1, a primary positive edge signal q1 obtained by punching out the digital audio interface signal Sdai at the positive edge of the reference clock Src rises at the positive edge of the reference clock Src, and the digital audio interface signal Sdai is at a high level. The three consecutive clocks of the reference clock Src are at a high level. At the next (fourth) rising edge of the clock after step Scr, the digital audio interface signal Sdai is at low level, so the primary positive edge signal q1 is at low level. Similarly, the 0th-order negative edge signal nq0 obtained by punching out the digital audio interface signal Sdai at the negative edge of the reference clock Src, and the 0th order positive edge obtained by punching out the 0th-order negative edge signal nq0 at the positive edge of the reference clock Src. The signal nq1 and the secondary positive edge signal q2 obtained by further punching the primary positive edge signal q1 with the positive edge of the reference clock Src have waveforms as shown in FIG.
[0057]
The edge detection signal Sed that detects the edge of the primary positive edge signal q1 is output for each edge of the primary positive edge signal q1.
[0058]
The latter half detection signal Sfd, which is an exclusive OR of the primary positive edge signal q1 and the zeroth positive edge signal nq1, is an edge between the low level B portion and the high level C portion, and the high level C portion and the low level D portion. It is output when there is a transition of the digital audio interface signal Sdai in the latter half of the reference clock Src (within the time corresponding to Hcf of the reference clock Src) as in the middle edge.
[0059]
In the count value calculator 2, the edge interval count value Cei of the edge detection signal Sed, the value p (t) of the latter half detection signal Sfd, and the latter half detection signal p (t−t immediately before the edge of the counted edge detection signal Sed. From 1), the half clock count value N (t) is given by the following equation (1). t is the time when a transition between the edge detection signal Sed and the digital audio interface signal Sdai is detected.
[0060]
N (t) = − p (t−1) + 2 × Cei + p (t) (1)
[0061]
Note that p (t) is a signal indicating that there is a transition of the digital audio interface signal Sdai in the second half between the edges of the count clock.
Briefly explaining the concept in the equation (1), the fact that there is an edge in the latter half between the edges of the immediately preceding clock at the time of calculation means that the actual signal is longer than the edge interval count value Cei. In addition, the fact that there is an edge in the second half between the edges one sample before the calculation means that the actual signal is shorter than the edge interval count value Cei.
[0062]
First, the edge interval count value Cei is doubled, and the edge interval count value Cei is calculated using p (t) and p (t-1) immediately before the edge detected by the edge detection signal Sed. Based on the equation (1), N (t) is calculated.
[0063]
However, p (t-1) and p (t) are 1 or 0. Therefore, for the high level A portion of the reference clock Src, the edge interval count value Cei is 3, and the second half detection signal Sfd has not risen, so the value of N (t) is 6.
[0064]
For the low level B portion of the reference clock Src, the edge interval count value Cei is 3, and the second half detection signal Sfd rises, so the value of N (t) is 7.
[0065]
For the high level C portion of the reference clock Src, the edge interval count value Cei is 3, and the second half detection signal Sfd continues to rise immediately before, so the value of N (t) is 6.
[0066]
For the low level portion D, the value of N (t) is 7. In the low level D portion, the value of N (t) is 12.
These values of N (t) are output from the count value calculator 2 as the half clock count value Shc.
[0067]
Next, operations of the approximately 3T detector 3 and the approximately 3T period detector 4 will be described with reference to FIG.
First, as shown in FIG. 4 (a), the preamble signal includes preambles PAb, 3T, 3T, 1T, and 1T having a periodic pattern of 3T, 1T, 1T, and 3T. Any of the three types of preambles PAw having 2T, 1T, and 2T periodic patterns.
[0068]
For the input of the preamble PA having each periodic pattern, the approximately 3T detector 3 has a period of approximately 3T, as shown in FIGS. 4 (b), 4 (c), and 4 (d). When a width edge interval count value Cei is detected, an approximate 3T detection signal S3T is output.
[0069]
The approximate 3T detector 3 predetermines an approximate 3T interval count value C3ta having a period width of approximately 3T with respect to the edge interval count value Cei of the edge detection signal Sed, and when the count value C3Ta is within the range, An approximate 3T detection signal S3T is output.
[0070]
The approximately 3T period detector 4 outputs approximately 3T period information I3T in which the rising edge of the approximately 3T detection signal S3T counts the interval between edges.
[0071]
Next, the operation of the nT determiner 5 will be described with reference to the determination table shown in FIG. 5A shows an nT determination table T3k when the sampling frequency is 32 kHz, and FIG. 5B shows an nT determination table T4k when the sampling frequency is 44.1 kHz / 48 kHz.
[0072]
Based on the count value C3Ta of the approximate 3T period information I3T, the nT determiner 5 refers to either the nT determination table T3k or the nT determination table T4k to determine which period pattern is 1T, 2T, or 3T. Determination is made and a determination signal Sj is output.
[0073]
The distinction between the nT determination table T3k) of the sampling frequency 32 kHz of the digital audio interface signal Sdai and the nT determination table T4k of the set of 44.1 kHz and 48 kHz is based on the edge interval count value Cei of the approximate 3T period information I3T. Thus, the nT determination table T3k and the nT determination table T4k can be distinguished by switching using switching means (not shown).
[0074]
Based on the determination signal Sj, the preamble detection circuit 6 has a period pattern of 3T, 1T, 1T and 3T of the preamble PAb, a period pattern of 3T, 3T, 1T and 1T of the preamble PAm, and 3T, 2T of the preamble PAw, Any one of three types of 1T and 2T periodic patterns is detected and a preamble detection signal Spa is output.
[0075]
The preamble detection circuit 6 stores only four determination signals Sj. That is, since each preamble PA is composed of four types of periodic units, it is necessary to store four determination signals Sj obtained by detecting the amplitude of each of the four types of periodic units. When any one of the above three patterns is detected, “H” is output. From the falling edge of “H” of the preamble detection signal Spa, 28 bits of the digital audio interface signal Sdai become a part subjected to biphase mark modulation.
[0076]
The biphase demodulator 7 obtains demodulated data by outputting “0” for 1T and “1” for 1T in succession from the falling edge of the preamble detection signal Spa. Audio data is separated from the demodulated data and a digital audio signal Sda is output.
[0077]
As described above, in the present embodiment, the edge of the digital audio interface signal Sdai is detected at both positive and negative edges of the reference clock Src, the count value at the half clock of the reference clock Src is obtained from this output, and the count value is obtained. By using the reference clock Src of a relatively low frequency that does not necessarily synchronize with the input digital audio interface signal Sdai without using an analog PLL circuit, by performing each determination of 1T, 2T, and 3T by a period of approximately 3T, Digital audio interface signal Sdai can be demodulated, and approximately 3T period is measured, and 1T, 2T, and 3T suitable for the period are determined from the table, so that the digital audio interface can be adapted to a wide frequency range. Interface signal demodulating apparatus can be realized.
[0078]
(Second Embodiment)
With reference to FIG. 6, a digital audio interface signal demodulating apparatus according to a second embodiment of the present invention will be described. The digital audio interface signal demodulator DDAp2 according to this example is the same as the digital audio interface signal demodulator DDAp1 shown in FIG. 1, except that a digital filter 8 is newly provided between the 3T period detector 4 and the nT determiner 5. It has a configuration.
[0079]
The digital filter 8 is provided to obtain stable approximate 3T cycle information I3Ts even if the approximate 3T cycle information I3T output from the 慨 3T cycle detector 4 is fluctuated due to erroneous detection caused by noise or the like.
[0080]
That is, the digital filter 8 adds digital filter processing to the approximate 3T cycle information I3T input from the approximate 3T cycle detector 4 and outputs stable approximate 3T cycle information I3Ts. In addition, by appropriately selecting the digital filter coefficients, stable approximate 3T period information I3Ts that follows the slow fluctuation of the approximate 3T period information I3T is output, and each period of 1T, 2T, and 3T is accurately determined. Can be done.
[0081]
The nT determiner 5 receives the half-clock count value Shc, determines the 1T and 2T boundaries, 2T and 3T boundaries based on the stable approximate 3T period information I3Ts, and determines 1T, 2T, and 3T for determination. Output as signal Sj.
[0082]
As described above, in the present embodiment, by using the digital filter 8, stable approximate 3T period information I3Ts is obtained even if the approximate 3T period information I3T output from the 3T period detector 4 is erroneously detected due to noise or the like. be able to. Furthermore, since the approximate 3T cycle information I3Ts can follow the slow fluctuation of the approximate 3T cycle information I3T, the nT determiner 5 can accurately determine the 1T, 2T, and 3T cycles.
[0083]
(Third embodiment)
With reference to FIG. 7, a digital audio interface signal demodulating apparatus according to a third embodiment of the present invention will be described. The digital audio interface signal demodulator DDAp3 according to this example is the same as the digital audio interface signal demodulator DDAp1 shown in FIG. 1, except that a limiter 9 is newly provided between the approximate 3T detector 3 and the approximate 3T period detector 4. It has a configuration.
[0084]
Hereinafter, the operation of the limiter 9 will be described with reference to FIG. In the case of the preamble PAb, since the periodic patterns of 3T, 1T, 1T, and 3T are obtained, 3T is close as shown in FIG. S3T is detected twice. In this case as well, in order to obtain an accurate approximate 3T detection signal S3TL, the limiter 9 converts the approximate 3T detection signal S3T input from the approximate 3T detector 3 to FIGS. 4 (b), 4 (c), and 4 As shown in (d), the first approximate 3T is detected, and a limit signal is added so that the approximate 3T detection signal is not output for a predetermined period from the fall of the approximate 3T detection signal S3T. The detection signal S3T is limited, and a more accurate approximate 3T detection signal S3TL is output.
[0085]
The approximate 3T period detector 4 counts the period of the accurate approximate 3T detection signal S3TL input from the limiter 9 to obtain a value, and outputs it as approximate 3T period information I3T. The nT determiner 5 receives the half-clock count value Shc, determines the 1T and 2T boundaries, the 2T and 3T boundaries based on the stable approximate 3T period information I3T, and determines each of 1T, 2T, and 3T. And output as a determination signal Sj.
[0086]
As described above, in this embodiment, the limiter 9 is inserted between the approximate 3T detector 3 and the approximate 3T period detector 4, and even if the 3Ts of the preamble PA are close to each other, the first approximate 3T is detected. A more accurate approximate 3T detection signal S3TL is obtained by limiting the approximate 3T detection signal S3T by adding a limit signal so that the approximate 3T detection signal is not output for a predetermined period from the fall of the approximate 3T detection signal S3T. In addition, more accurate approximate 3T cycle information I3T can be output.
[0087]
(Fourth embodiment)
With reference to FIG. 8, a digital audio interface signal demodulating apparatus according to a fourth embodiment of the present invention will be described. The digital audio interface signal demodulator DDAp4 according to this example has a configuration in which the digital audio interface signal demodulator DDAp2 shown in FIG. 6 and the digital audio interface signal demodulator DDAp3 shown in FIG. 7 are combined.
[0088]
That is, in the digital audio interface signal demodulator DDAp4, in the digital audio interface signal demodulator DDAp1, a limiter 9 is newly provided between the approximately 3T detector 3 and the approximately 3T period detector 4, and the approximately 3T period detector. A digital filter 8 is newly provided between 4 and the nT determiner 5.
[0089]
Hereinafter, the operation of the digital audio interface signal demodulator DDAp4 will be described with reference to FIG.
[0090]
The limiter 9 limited the approximate 3T detection signal S3T input from the approximate 3T detector 3, and detected the first approximate 3T as shown in FIGS. 4B, 4C, and 4D. A limit signal is added for a predetermined period from the fall of the approximate 3T detection signal S3T to limit the approximate 3T detection signal S3T, and a more accurate approximate 3T detection signal S3TL is output.
[0091]
The approximate 3T period detector 4 receives an accurate approximate 3T detection signal S3TL input from the limiter 9, counts the period, obtains a count value, and outputs it as approximate 3T period information I3T.
[0092]
The digital filter 8 outputs stable approximate 3T period information I3Ts by digital filter processing even if the approximate 3T period information I3T fluctuates due to erroneous detection caused by noise or the like in the approximate 3T detection signal S3T. Since the approximate 3T period information I3Ts follows the slow fluctuation of the approximate 3T period information I3T, the nT determiner 5 can accurately determine the period width (1T, 2T, 3T).
[0093]
(Fifth embodiment)
A digital audio interface signal decoding apparatus according to a fifth embodiment of the present invention will be described with reference to FIG. In the digital audio interface signal demodulator DDAp5 according to this example, the approximately 3T detector 3 in the digital audio interface signal demodulator DDAp1 shown in FIG. The reference clock Src and edge detection signal Sed that have been input are configured so that a half clock count value Shc is input instead of the 3T detector 3R.
[0094]
The approximately 3T detector 3R predetermines a count value having a width of approximately 3T with respect to the half clock count value Shc. As a result, when the count value N (t) falls within the predetermined range, an approximate 3T detection signal S3Ta that is more accurate than the approximate 3T detection signal S3T in the case of the digital audio interface signal demodulator DDAp1 is output.
[0095]
Then, the approximate 3T cycle detector 4 counts the cycle of the approximate 3T detection signal S3Ta input from the approximate 3T detector 3R to obtain a value C3Ta, and outputs it as approximate 3T cycle information I3T.
[0096]
Based on the half clock count value Shc input from the count value calculator 2 and the value of the stable approximate 3T period information I3T input from the approximate 3T period detector 4, the nT determiner 5 determines the boundary between 1T and 2T. The boundary between 2T and 3T is determined, 1T, 2T, and 3T are determined and output as a determination signal Sj.
[0097]
In this way, by performing approximately 3T detection with the half clock count value Shc for the edge interval count value Cei of the edge interval of the edge detection signal Sed, a more accurate approximate 3T value detection signal S112 is obtained and more accurate. The approximate 3T period information I3T can be output.
[0098]
In addition, the specific example of each circuit of each said embodiment can be arbitrarily changed in the range with which a claim is satisfy | filled.
Moreover, the illustrated numerical values and the combinations thereof are examples, and should be changed according to the change of the conditions.
Further, although the above embodiments are designed with LSIs in mind, some or all of the functions of each circuit can be realized on the software of a microcomputer.
[0099]
As described above, the digital audio interface signal demodulator according to the present invention performs edge detection of the digital audio interface signal using both positive and negative edges of the reference clock, and obtains a count value at a half clock of the reference clock from this output. In addition, by detecting approximately 3T information from the edge detection of the digital audio interface signal, obtaining the period thereof, and obtaining a demodulated output by table determination from the period value, a low frequency reference is obtained without using a PLL. It is possible to provide a demodulator that can perform demodulation only with a clock and can also handle digital audio interface signals of a wide range of frequencies.
Further, since an analog circuit such as PLL or LPF is not required, the circuit can be reduced in size, stable in operation, and a wide frequency digital audio interface signal demodulator can be realized.
The present invention can also be applied to digital audio equipment that demodulates digital audio interface signals, such as compact discs, digital audio tape recorders, and minidiscs.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a digital audio interface signal demodulating apparatus according to a first embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of the edge detector of FIG. 1;
FIG. 3 is a timing chart of various signals observed by the edge detector and the count value calculator of FIG. 1;
FIG. 4 is a timing chart of various signals observed by the approximate 3T detector and the approximate 3T period detector of FIG. 1;
FIG. 5 is a table used for 1T, 2T, and 3T determination by the nT determiner of FIG. 1;
FIG. 6 is a block diagram showing a configuration of a digital audio interface signal demodulating apparatus according to a second embodiment of the present invention.
FIG. 7 is a block diagram showing a configuration of a digital audio interface signal demodulating apparatus according to a third embodiment of the present invention.
FIG. 8 is a block diagram showing a configuration of a digital audio interface signal demodulating apparatus according to a fourth embodiment of the present invention.
FIG. 9 is a block diagram showing a configuration of a digital audio interface signal demodulating apparatus according to a fifth embodiment of the present invention.
FIG. 10 is an explanatory diagram showing an outline of a digital audio interface standard;
FIG. 11 is a block diagram showing a configuration of a conventional digital audio interface signal demodulating apparatus.
FIG. 12 is a timing chart of various signals observed by the digital audio interface signal demodulating device shown in FIG. 11;
[Explanation of symbols]
DDAp1 to DDAp5, DDAc Digital audio interface signal demodulator
1 Edge detector
2 Count value calculator
3 About 3T detector
4 Approximately 3T period detector
5 nT detector
6 Preamble detector
7 Biphase demodulator
8 Digital filter
9 Limiter
Src reference clock
Sdai digital audio interface signal
Sed edge detection signal
Sfd latter half detection signal
Shc Half clock count value
S3T Approximately 3T detection signal
I3T Approximate 3T period information
Sj judgment signal
Spa preamble signal
Sda Digital audio signal
I3Ts approximate 3T period information
S3TL Approximately 3T detection signal
S3Ta Approx 3T detection signal

Claims (8)

A digital audio interface signal demodulating apparatus that adds a preamble and additional information to a digital audio signal and demodulates a digital audio interface signal transmitted by bi-phase modulation,
Each time an edge of the digital audio interface signal is detected based on a positive edge of a reference clock having a frequency higher than twice the minimum inversion frequency of the digital audio interface signal and not necessarily synchronized with the digital audio interface signal Each time the edge detection signal is input, the edge detection means for generating a second edge detection signal indicating the presence of an edge of the digital audio interface signal in the second half of the reference clock The value obtained by counting the edge detection signal is obtained by subtracting 1 if the latter half detection signal is input to the value obtained by doubling this value, and subtracting 1 if the last half detection signal is input. Count for calculating half clock count value And value calculation means,
Each time the edge detection signal is input, a value obtained by counting the edge detection signal with the reference clock is obtained, and a value within which the count value falls within a predetermined range is detected to generate a first approximate 3T detection signal. 3T detection means;
Approximately 3T period detecting means for generating the first 慨 3T period information by counting the period of the first approximately 3T detection signal with the reference clock;
Determining means for comparing the half clock count value with a predetermined table corresponding to the first approximately 3T detection signal to determine a modulation period of the digital audio interface signal and generating a determination signal;
Preamble detection means for detecting the preamble and generating a preamble detection signal based on the determination signal;
A digital audio interface signal demodulating device comprising biphase demodulating means for demodulating and outputting a digital audio signal from the determination signal using the preamble detection signal as a timing reference. The edge detection means includes
Punching the digital audio interface signal with the reference clock to generate a first punch signal;
Punching the digital audio interface signal with an inverted clock of the reference clock, and further punching with the reference clock to generate a first inverted punch signal; and
Detecting an edge of the first punching signal, outputting the edge detection signal, and generating an exclusive OR of the first punching signal and the first inverted punching signal to generate the second half detection signal; The digital audio interface signal demodulator according to claim 1. Digital filter means for filtering the first 慨 3T period information to generate second approximate 3T period information;
2. The digital audio according to claim 1, wherein the determination unit generates the determination signal by comparing the half clock count value with a predetermined table corresponding to the second approximate 3T period information. Interface signal demodulator. Limit means for outputting the second approximate 3T detection signal after suppressing the first approximate 3T detection signal for a predetermined period,
2. The digital audio interface signal demodulating apparatus according to claim 1, wherein the approximately 3T period detecting means counts the period of the second approximately 3T detection signal with the reference clock. Limit means for outputting the second approximate 3T detection signal after suppressing the first approximate 3T detection signal for a predetermined period;
Digital filter means for filtering the first approximate 3T period information to generate second approximate 3T period information;
The approximately 3T period detecting means counts the period of the second approximately 3T detection signal with the reference clock,
The determination means generates a determination signal indicating the modulation period of the digital audio interface signal by comparing the half clock count value with a predetermined table corresponding to the second approximate 3T period information. The digital audio interface signal demodulating device according to claim 1. A digital audio interface signal demodulating apparatus that adds a preamble and additional information to a digital audio signal and demodulates a digital audio interface signal transmitted by bi-phase modulation,
Each time an edge of the digital audio interface signal is detected based on a positive edge of a reference clock having a frequency higher than twice the minimum inversion frequency of the digital audio interface signal and not necessarily synchronized with the digital audio interface signal Each time the edge detection signal is input, the edge detection means for generating a second edge detection signal indicating the presence of an edge of the digital audio interface signal in the second half of the reference clock The value obtained by counting the edge detection signal is obtained by subtracting 1 if the latter half detection signal is input to the value obtained by doubling this value, and subtracting 1 if the last half detection signal is input. Count for calculating half clock count value And value calculation means,
An approximate 3T detection means for generating a third approximate 3T detection signal by detecting a value within which the half clock count value falls within a predetermined range;
Approximately 3T period detecting means for generating first approximately 3T period information by counting the period of the third approximately 3T detection signal with the reference clock;
Determining means for determining a modulation period of the digital audio interface signal by generating a determination signal by comparing the half clock count value with a predetermined table corresponding to the first approximately 3T detection signal;
Preamble detection means for detecting the preamble and generating a preamble detection signal based on the determination signal;
A digital audio interface signal demodulating device comprising biphase demodulating means for demodulating and outputting a digital audio signal from the determination signal using the preamble detection signal as a timing reference. 2. The digital audio interface according to claim 1, further comprising switching means for switching the half clock count value based on the first approximate 3T cycle information between a plurality of predetermined tables corresponding to the first approximate 3T cycle information. Signal demodulator. 2. The digital audio interface signal demodulating apparatus according to claim 1, wherein a modulation period is one, two, or three times the reciprocal of the minimum inversion frequency.

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