JP4020730B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, for example, the present invention relates to a semiconductor device using a substrate bias effect such as a dynamic threshold transistor in which a gate electrode and a well region are connected, and a manufacturing method thereof.
[0002]
[Prior art]
Conventionally, a bulk substrate has been used as a MOSFET (Metal Oxide Field Effect Transistor) technology capable of low-voltage driving, low power consumption, and high-speed operation utilizing the substrate bias effect generated by changing the bias in the well region. Dynamic threshold operation transistors (hereinafter referred to as DTMOS) have been proposed.
[0003]
Here, the effect of DTMOS will be considered. Here, the N-channel type DTMOS is considered, but the P-channel type DTMOS is the same except that the sign is different.
[0004]
In the DTMOS, the gate electrode and the well region are electrically connected. Therefore, the potential of the well region rises only when a high level potential is applied to the gate electrode, the effective threshold decreases due to the substrate bias effect, and the drive current increases as compared with the case of a normal MOSFET. Therefore, a large drive current can be obtained while maintaining a low leakage current with a low power supply voltage. Therefore, a low voltage drive and low power consumption MOSFET is realized.
[0005]
Here, the substrate bias effect of DTMOS will be described. The substrate bias effect is an effect that when a bias is applied to the well region, the threshold value of the transistor changes and the drain current increases or decreases. It is convenient to use the substrate bias effect factor γ as an amount representing the magnitude of the substrate bias effect. Hereinafter, a case where a forward bias is applied as a substrate bias realized by DTMOS (a forward bias for a source / drain junction) will be described.
[0006]
γ = | ΔVt / Vb | (1)
Here, Vb is a voltage applied to the shallow well region with reference to the potential of the source region, and ΔVt is a threshold shift amount (negative value) due to the application of the voltage Vb to the shallow well region. It should be noted that the threshold here is a threshold when the voltage Vb is always applied to the shallow well region, and is different from an effective threshold of DTMOS in which the voltage of the well region varies. In DTMOS, γ is obtained from ΔVt when Vb is the power supply voltage Vdd.
[0007]
From equation (1), it can be seen that when a constant voltage Vb is applied to the shallow well region, the threshold shift amount ΔVt increases as γ increases, and a larger drive current flows.
[0008]
Meanwhile, it is known that the threshold shift amount ΔVt has the following relationship with the width Xd of the depletion layer extending from the gate oxide film to the substrate side.
[0009]
ΔVt∝ToxVdd / Xd (2)
Here, Tox is a gate insulating film thickness. Therefore, it can be seen from Equation (2) that it is effective to suppress the width Xd of the depletion layer extending from the gate insulating film to the substrate side in order to increase the substrate bias effect.
[0010]
A method for increasing the substrate bias effect factor γ by suppressing the width Xd of the depletion layer extending from the gate insulating film to the substrate side has been proposed (Channel Profile Optimization and Low-Power High Performance Dynamic MOSFET). Wann et al., IEDM Tech. Dig., P113, 1996). The structure shown in the above document will be described with reference to FIG. In FIG. 10, 31 is a P-channel DTMOS, 32 is an N-channel DTMOS, 301 is a P-type substrate, 302 is an N-type deep well region, 303 is an N-type shallow well region, and 304 is a P-type shallow well region. 305, a region with a high N-type impurity concentration, 306, a region with a high P-type impurity concentration, 307, a channel region of P-channel DTMOS, 308, a channel region of N-channel DTMOS, and 309, P⁺Diffusion region, 310 is N⁺A diffusion region, 311 is a gate insulating film, 312 is a gate electrode, and 313 is an element isolation region. Although not shown, in each DTMOS, the gate electrode 312 and the shallow well regions 303 and 304 are electrically connected to each other.
[0011]
The electric field sharply attenuates in the regions 305 and 306 having a high impurity concentration, and the regions 305 and 306 serve as a ground plate. Therefore, the extension of the depletion layer remains in the vicinity of the surfaces of the regions 305 and 306. Therefore, the depletion layer width Xd extending from the gate oxide film 311 toward the channel regions 307 and 308 is limited if the channel regions 307 and 308 are sufficiently thin and the regions 305 and 306 having a high impurity concentration serve as stoppers. . Therefore, the substrate bias effect factor γ becomes larger than the equations (1) and (2). Therefore, the drive current of the dynamic threshold transistors 31 and 32 can be further increased.
[0012]
[Non-Patent Document 1]
C. Wann et al., “Channel Profile Optimization and Device Design for Low Power High Performance Dynamic Threshold MOSFET (Channel Profile Optimization and Device Design). for Low-Power High Performance Dynamic Threshold MOSFET) ", IDM Tech. Dig., 1996, p113.
[0013]
[Problems to be solved by the invention]
However, according to the above prior art, P⁺Diffusion region 309 (N⁺There is a problem that the junction capacitance between the diffusion region 310) and the N-type shallow well region 303 (P-type shallow well region 304) is large. In particular, a region 305 having a high N-type impurity concentration (region 306 having a high P-type impurity concentration) and P⁺Diffusion region 309 (N⁺The diffusion region 310) is in contact with the junction region, and the junction capacitance is further increased. This increases the power consumption of the DTMOS and slows down the operation speed.
[0014]
The present invention has been made to solve the above problems, and its main purpose is to provide a junction capacitance between a diffusion layer region and a shallow well region in a DTMOS or the like in which the gate depletion layer is suppressed to increase the drive current. Is to enable high-speed operation with lower power consumption. In addition to the DTMOS, it is to provide a semiconductor device having a structure in which the substrate bias effect factor γ increases as shown in the equations (1) and (2).
[0015]
[Means for Solving the Problems]
  In order to achieve the above object, a semiconductor device of the present invention includes:
  A semiconductor substrate;
  A second conductivity type well region formed in the semiconductor substrate;
  An element isolation region;
  A source region and a drain region of a first conductivity type formed on the element isolation region;
  A second conductivity type channel region formed between the source region and the drain region and formed on the second conductivity type well region;
  A gate insulating film formed on the channel region, source region and drain region;
  A gate electrode formed on the gate insulating film;
With
  The channel region is made of a single crystal semiconductor, the source region and the drain region are made of a polycrystalline semiconductor,
  The thickness of the channel region is the same as the thickness of the source region and drain region,
  A part of the channel region is on the element isolation region,
  The source region and drain region have a junction with the part of the channel region, but have no junction with the well region,
  The impurity concentration giving the second conductivity type in the well region is higher than the impurity concentration giving the second conductivity type in the channel region, and
  The portion of the gate insulating film formed on the source region and the drain region is thicker than the portion of the gate insulating film formed on the channel region.
[0017]
In the present specification, the first conductivity type means P type or N type. The second conductivity type means N type when the first conductivity type is P type, and P type when the first conductivity type is N type.
[0018]
According to the above configuration, the shallow second region of the second conductivity type having a high impurity concentration is formed under the channel region of the second conductivity type having a low impurity concentration. Therefore, since the width of the depletion layer extending from the gate electrode to the channel region is suppressed by the well region of the second conductivity type, the substrate bias effect can be increased. Therefore, the drive current of the semiconductor device (element) can be increased.
[0019]
  In addition, since the source region and the drain region are formed on the element isolation region, the junction capacitance associated with the source region and the drain region can be extremely reduced, and the source region and the drain region are formed on the source region and the drain region. Since the portion of the gate insulating film formed is thicker than the portion of the gate insulating film formed on the channel region, the capacity of the gate electrode, the source region, and the drain region can be reduced. it can. Accordingly, the power consumption of the semiconductor device can be reduced and the speed can be increased.Further, since the source region and the drain region are made of a polycrystalline semiconductor, the impurity diffusion can be easily controlled. That is, since a polycrystalline semiconductor has a very large diffusion coefficient (100 times or more) compared to a single crystal semiconductor, impurities diffuse quickly into the source region and the region to be the drain region (region made of the polycrystalline semiconductor). However, it hardly diffuses into the region to be the channel region (region made of a single crystal semiconductor). Therefore, since the channel width is controlled with good reproducibility, the variation of each element and lot of the semiconductor device can be reduced.
[0020]
In addition, the semiconductor device of one embodiment
A first conductivity type deep well region formed in the semiconductor substrate;
The second conductivity type well region is a second conductivity type shallow well region formed on the first conductivity type deep well region,
The gate electrode and the second conductivity type shallow well region are electrically connected.
[0021]
According to the above configuration, since the width of the depletion layer extending from the gate electrode to the channel region is suppressed by the shallow well region of the second conductivity type, the above effect that the substrate bias effect can be increased. In addition, since the gate electrode and the second conductivity type shallow well region are electrically connected to form a DTMOS structure, a larger substrate bias effect can be obtained and the drive current can be reduced. Can be very large. Therefore, it is possible to realize a DTMOS that has a very large driving current, low power consumption, and high speed.
[0022]
In one embodiment,
The element isolation region is
A deep isolation region having a depth deeper than a junction depth between the first conductivity type deep well region and the second conductivity type shallow well region;
A shallow element isolation region which is an insulating layer having a depth shallower than a junction depth between the deep well region of the first conductivity type and the shallow well region of the second conductivity type;
Consists of
The shallow element isolation region is located between the source region and the drain region and the shallow well region of the second conductivity type.
[0023]
According to the embodiment, the element isolation region includes the deep element isolation region for isolating the second conductivity type shallow well region for each element, the source region and the drain region, and the second conductive region. It consists of a shallow element isolation region which is the insulating layer separating the shallow well region of the mold. Accordingly, since the second conductivity type shallow well region exists under the insulating layer which is the shallow element isolation region, the resistance of the second conductivity type shallow well region can be reduced. Therefore, since the delay time when the potential applied to the gate electrode is transmitted to the shallow well region of the second conductivity type can be shortened, the substrate bias effect of the DTMOS can be used effectively.
[0026]
In one embodiment,
Part of the source region and drain region is silicided.
[0027]
According to the embodiment, a part of the source region and the drain region is silicided to reduce the resistance. Therefore, the drive current of the semiconductor device can be further increased.
[0028]
In one embodiment,
The polycrystalline semiconductor has a particle size of 50 nm or less.
[0029]
According to the above embodiment, since the grain size of the polycrystalline semiconductor is 50 nm or less, the difference in diffusion coefficient between the polycrystalline semiconductor and the single crystal semiconductor becomes extremely large. Therefore, the temperature of activation annealing of the diffusion layer region serving as the source region and the drain region can be lowered to 800 ° C. or less, and variation among elements and lots of the semiconductor device can be further reduced. When the grain size of the polycrystalline semiconductor exceeds 50 nm, the difference in diffusion coefficient does not increase so much, and the activation annealing temperature of the diffusion layer region that becomes the source region and the drain region can be lowered to 800 ° C. or lower. It will disappear.
[0030]
  In one embodiment,
The impurity concentration giving the second conductivity type in the second conductivity type well region is:10 ¹⁸ cm ^-3 -10 ²⁰ cm ^-3 AndThe impurity concentration of the second conductivity type in the channel region is set to 10 times or more higher.
[0031]
According to the above-described embodiment, the shallow well region of the second conductivity type having a sufficiently high impurity concentration (10 times or more) is formed under the channel region having a low impurity concentration. As described above, since the impurity concentration of the second well type shallow well region is high, the electric field attenuation becomes steep, and the width of the depletion layer extending from the gate electrode to the channel region is more effectively suppressed. The substrate bias effect can be increased with good controllability. Therefore, the driving current of the semiconductor device can be extremely increased.
[0032]
  In addition, a method for manufacturing a semiconductor device according to the present invention includes:
  Forming a second conductivity type well region and an element isolation region on a semiconductor substrate in a state where the second conductivity type well region and the element isolation region are exposed on the surface;
  Under the condition that the single crystal semiconductor film is selectively grown epitaxially in the region where the shallow well region of the second conductivity type is exposed, while the polycrystalline semiconductor film is selectively grown on the element isolation region,The thickness of the single crystal semiconductor film is the same as the thickness of the polycrystalline semiconductor film, and a part of the single crystal semiconductor film is on the element isolation region, and the polycrystalline semiconductor film Has a junction with the part of the single crystal semiconductor film, but does not have a junction with the well region.Depositing a semiconductor film on the surface;
  Introducing a first conductivity type impurity into the polycrystalline semiconductor film;
  Diffusing the first conductivity type impurity to form a source region and a drain region;
  Forming a gate insulating film on the channel region, the source region, and the drain region of the single crystal semiconductor film by a thermal oxidation method;
It is characterized by having.
[0033]
According to the invention, since the semiconductor film to be the channel region is formed after the element isolation region and the second conductivity type well region having a high impurity concentration are formed, the vicinity of the interface between the channel region and the well region is formed. Thus, a steep profile of the impurity concentration distribution can be provided. Therefore, it is easy to give a desired threshold value to a semiconductor device such as a MOS transistor or a DTMOS and to limit the depletion layer width by the well region of the second conductivity type.
[0034]
According to the invention, a single crystal semiconductor film is formed in a self-aligned manner on the region where the well region of the second conductivity type is exposed, and a polycrystalline semiconductor film is formed on the element isolation region in a self-aligned manner. The source region and the drain region are formed by introducing and diffusing conductive impurities into the polycrystalline semiconductor film. Therefore, it is possible to prevent the source region and the drain region from coming into contact with the second conductivity type well region without using a special device or process, and a junction capacitance associated with the source region and the drain region. Can be made very small.
[0035]
Further, the gate insulating film formed on the source region and the drain region in order to form the source region and the drain region by diffusing the impurity of the first conductivity type before forming the gate insulating film. This portion is formed thicker than the thickness of the portion of the gate insulating film formed on the channel region. For this reason, the capacity | capacitance put together in the said gate electrode and the said source region and drain region can be made small.
[0036]
In one embodiment,
In the step of depositing the semiconductor film on the surface, the semiconductor film is formed by a chemical vapor deposition method at a growth temperature of 650 ° C. or higher.
[0037]
According to the embodiment, the polycrystalline semiconductor film having a thickness of 50 nm or less can be formed with good controllability.
[0038]
In one embodiment,
The step of diffusing the first conductivity type impurity to form the source region and the drain region is performed in an oxygen atmosphere.
[0039]
According to the above embodiment, since the annealing is performed in an oxygen atmosphere, an accelerated diffusion phenomenon occurs, and for example, the impurity speed in the polycrystalline silicon film can be increased as compared with annealing in a nitrogen atmosphere. Thereby, the annealing time can be shortened and the annealing temperature can be further reduced.
[0040]
In one embodiment,
The step of diffusing the first conductivity type impurity to form the source region and the drain region and the step of forming the gate insulating film by a thermal oxidation method are performed simultaneously.
[0041]
According to the above embodiment, the process can be simplified.
[0042]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
[0043]
The semiconductor substrate that can be used in the present invention is not particularly limited, but a silicon substrate is preferable. The semiconductor substrate may have a P-type or N-type conductivity type.
[0044]
(Embodiment 1)
In the semiconductor device according to the first embodiment, a channel region is formed on an active region on a semiconductor substrate, and a diffusion region is formed on an element isolation region in a self-aligned manner, thereby significantly reducing the junction capacitance associated with the diffusion region. It is a thing. The semiconductor device according to the first embodiment will be described with reference to FIGS. FIG. 1 is a cross-sectional view in a direction perpendicular to the longitudinal direction of the gate electrode of the semiconductor device according to the first embodiment. In FIG. 1, the interlayer insulating film and the upper wiring are omitted. FIG. 2 is an enlarged view of the end of the gate electrode 117 of the N-channel MOS transistor 11 of FIG. 1, and illustrates the overlap capacitance between the gate electrode 117 and the source region 114 and drain region 114 in detail.
[0045]
First, the configuration of the semiconductor device according to the first embodiment will be described with reference to FIG.
[0046]
An N-type deep well region 104 and a P-type deep well region 105 are formed in the silicon semiconductor substrate 101. An N-type shallow well region 107 having a concentration higher than that of the N-type deep well region 104 is formed on the N-type deep well region 104. A P-type shallow well region 106 having a higher concentration than the P-type deep well region 105 is formed on the P-type deep well region 105. The shallow well regions 106 and 107 are electrically isolated for each element by an element isolation region 103 made of a silicon oxide film as an example of an insulating layer. The direct connection between the P-type shallow well region 106 and the N-type shallow well region 107 should be avoided because it causes a problem of an increase in leakage current and capacitance. The depth is preferably shallower than the depth of the isolation region 103. Of course, if there is a sufficient margin between the elements, the shallow well regions 106 and 107 may be deeper than the element isolation region 103 as long as they are not directly connected.
[0047]
The upper surface of the P-type shallow well region 106 and a part of the upper surface of the element isolation region 103 are covered with a semiconductor thin film. The semiconductor thin film becomes a channel region 108 of a single crystal semiconductor thin film containing P-type impurities on the P-type shallow well region 106, and N on the polycrystalline semiconductor thin film on the element isolation region 103.⁺A diffusion layer region 114 is formed. A gate electrode 117 is formed on the channel region 108 and the P-type shallow well region 106 with a gate insulating film 116 interposed therebetween.
[0048]
On the other hand, the upper surface of the N-type shallow well region 107 and a part of the upper surface of the element isolation region 103 are covered with a semiconductor thin film. The semiconductor thin film becomes a channel region 108 ′ of a single crystal semiconductor thin film containing N-type impurities on the N-type shallow well region 107, and the polycrystalline semiconductor thin film P on the element isolation region 103.⁺A diffusion layer region 115 is formed. A gate electrode 117 is formed on the channel region 108 ′ and the N-type shallow well region 107 via a gate insulating film 116.
[0049]
The channel regions 108 and 108 ′ of the single crystal semiconductor thin film are slightly wider than the upper surfaces of the shallow well regions 106 and 107, and a part thereof is on the element isolation region 103.
[0050]
The semiconductor thin film is made of general silicon, but may be germanium, silicon germanium (SiGe), or a laminated film made of these.
[0051]
In the gate insulating film 116, the thickness of the portion 116b formed on the diffusion layer regions 114 and 115 is 2 to 5 times thicker than the thickness of the portion 116a formed on the channel regions 108 and 108 '.
[0052]
Therefore, the overlap capacitance between the gate electrode 117 and the diffusion layer regions (source / drain regions) 114 and 115 can be reduced. This will be described with reference to FIG. The gate electrode 117 is formed so as to overlap with the channel region 108 with a design margin (DM: positioning dimension of the gate electrode with respect to element isolation) in order to suppress variation in element characteristics due to variation in channel width. There is a need. Therefore, since the gate electrode 117 cannot be formed in a self-aligned manner with respect to the element isolation region 103 (or the source / drain region 114), there is a concern about an increase in overlap capacitance between the gate electrode 117 and the source / drain region 114. Is done. However, in the first embodiment, as shown in FIGS. 1 and 2, on the diffusion layer regions 114 and 115, a portion 116a of the gate insulating film (silicon oxide film) 116 on the channel regions 108 and 108 ′ is formed. On the other hand, since the portion 116b of the gate insulating film 116 having a thickness 2 to 5 times larger is formed, the overlap capacitance between the gate electrode 117 and the source / drain regions 114 and 115 can be reduced.
[0053]
The impurity concentration of the channel regions 108 and 108 ′ may be determined so that the MOS transistors 11 and 12 have a desired threshold value. Channels (inversion layers) are formed in the uppermost layer portions of the channel regions 108 and 108 'when the MOS transistors 11 and 12 are on. Further, the thickness of the channel regions 108 and 108 'is determined to be smaller than the maximum depletion layer width when the channels have a uniform concentration so that the channel regions 108 and 108' are completely depleted even when the MOS transistors 11 and 12 are off. Is preferred. In this case, the substrate bias effect of the MOS transistors 11 and 12 can be sufficiently obtained. Specifically, when the MOS transistors 11 and 12 are in the off state, the width of the depletion layer extending from the gate insulating film 116 side into the channel regions 108 and 108 ′ is, for example, the impurity concentration of the channel regions 108 and 108 ′. Uniform 1x10¹⁷cm^-3In this case, the maximum depletion layer width is about 100 nm. Accordingly, the thickness of the channel regions 108 and 108 ′ is preferably 100 nm or less. The relationship between the thickness of the channel regions 108 and 108 'and the drive current will be described in detail in the second embodiment.
[0054]
Since the electric field sharply attenuates in the shallow well regions 106 and 107 having a high impurity concentration and the well regions 106 and 107 serve as a ground plate, the depletion layer extends only in the vicinity of the surfaces of the well regions 106 and 107. Therefore, the higher the concentration of the shallow well regions 106 and 107, the sharper the electric field is attenuated, so that the depletion layer extending from the channel regions 108 and 108 ′ can be more effectively suppressed. The impurity concentration of the shallow well regions 106 and 107 is, for example, 10 times higher than that of the channel regions 108 and 108 ′.¹⁸cm^-3-10²⁰cm^-3By doing so, the effect of suppressing the growth of the depletion layer is increased, which is more desirable. Thus, since the width of the depletion layer extending from the gate electrode 117 to the channel regions 108 and 108 ′ is suppressed by the shallow well regions 106 and 107, the substrate bias effect factor γ is increased by the equation (2). It can be done. It is preferable that the impurity profile be as steep as possible at the boundary between the channel regions 108 and 108 'and the shallow well regions 106 and 107. This is because the ability to prevent the depletion layer from growing decreases when the profile changes slowly.
[0055]
The semiconductor device according to the first embodiment has an electric field in a direction perpendicular to the surface of the semiconductor substrate with respect to the electric field strength between the source / drain regions 114 and 115, as compared with a conventional element having a uniform impurity concentration in the channel region. Since the strength is large, there is an effect of suppressing the short channel effect.
[0056]
As is apparent from FIG. 1, the diffusion layer regions 114 and 115 only have junctions with a very small area with the channel regions 108 and 108 ′, and do not have junctions with the shallow well regions 106 and 107. In addition, since the polycrystalline semiconductor has a grain size of 50 nm or less and the diffusion coefficient of the polycrystalline semiconductor can be made extremely larger than that of the single crystal semiconductor, the impurity is the source / drain region (source region and drain region) 114. , 115 quickly diffuses into a region (region made of a polycrystalline semiconductor), and hardly diffuses into regions (regions made of a single crystal semiconductor) that should become the channel regions 108 and 108 ′. The diffusion layer regions (source / drain regions) 114 and 115 are formed on the element isolation region 103 and in a self-aligned manner with respect to the element isolation region 103. Therefore, the junction capacitance associated with the diffusion layer regions 114 and 115 can be made very small, and the channel width can be controlled with good reproducibility, so that the variation of each element and lot of the semiconductor device can be reduced.
[0057]
The manufacturing procedure of the semiconductor device according to the first embodiment is different from the manufacturing procedure of the semiconductor device according to the second embodiment described later in that there is no deep element isolation region 102 described later, and shallow well regions 106 and 107. Since the formation regions are different and the gate electrode 117 and shallow well regions 106 and 107 are not connected to each other, the description is omitted here.
[0058]
(Embodiment 2)
The semiconductor device according to the present second embodiment is a DTMOS in which the gate electrode and the shallow well region are connected to the semiconductor device according to the first embodiment, thereby further increasing the substrate bias effect and obtaining a larger driving force. The semiconductor device according to the second embodiment will be described with reference to FIGS. 3 is a plan view of the semiconductor device according to the second embodiment, FIG. 4 is a cross-sectional view taken along line AA ′ in FIG. 3, and FIG. 5 is a cross-sectional line BB ′ in FIG. It is sectional drawing seen from. 3 to 5, the interlayer insulating film and the upper wiring are omitted. 6 and 7 illustrate a procedure for manufacturing the semiconductor device according to the second embodiment. FIG. 8 explains the relationship between the thickness of the channel region and the drive current.
[0059]
First, the configuration of the semiconductor device according to the second embodiment will be described with reference to FIGS.
[0060]
As shown in FIG. 4, an N-type deep well region 104 and a P-type deep well region 105 are formed in the semiconductor substrate 101. A P-type shallow well region 106 is formed on the N-type deep well region 104. On the P-type deep well region 105, an N-type shallow well region 107 is formed. The shallow well regions 106 and 107 are electrically isolated element by element by a deep element isolation region 102 made of a silicon oxide film as an example of an insulating layer.
[0061]
In the P-type shallow well region 106, a shallow element isolation region 103 made of a silicon oxide film as an example of an insulating layer is formed. As shown in FIGS. 3 and 4, the upper surface of the P-type shallow well region 106 and part of the upper surfaces of the element isolation regions 102 and 103 are covered with a semiconductor thin film. The semiconductor thin film becomes a channel region 108 made of a single crystal semiconductor thin film containing a P-type impurity on the P-type shallow well region 106, and N made of a polycrystalline semiconductor thin film on the element isolation regions 102 and 103.⁺A diffusion layer region 114 is formed. The shallow element isolation region 103 is located between the diffusion layer region 114 and the P-type shallow well region 106. A gate electrode 117 is formed on the channel region 108 and the P-type shallow well region 106 with a gate insulating film 116 interposed therebetween. 3 and 5, a part of the gate electrode 117 is removed to expose the P-type shallow well region 106 (see the region 131 in FIG. 3), and the P-type shallow well region 106 is exposed. P in the area⁺A diffusion layer 132 (see FIG. 5) is formed. Although not shown, the gate electrode 117 and P⁺A contact is formed across the diffusion layer 132, and the gate electrode 117 and the P-type shallow well region 106 are ohmically connected. Thus, the N channel type DTMOS 21 is configured.
[0062]
On the other hand, a shallow element isolation region 103 made of a silicon oxide film as an example of an insulating layer is formed in the N-type shallow well region 107. The upper surface of the N-type shallow well region 107 and part of the upper surfaces of the element isolation regions 102 and 103 are covered with a semiconductor thin film. The semiconductor thin film becomes a channel region 108 ′ made of a single crystal semiconductor thin film containing an N-type impurity on the N-type shallow well region 107, and P made of a polycrystalline semiconductor thin film on the element isolation regions 102 and 103.⁺A diffusion layer region 115 is formed. The shallow element isolation region 103 is located between the diffusion layer region 115 and the N-type shallow well region 107. A gate electrode 117 is formed on the channel region 108 ′ and the N-type shallow well region 107 via a gate insulating film 116. Although not shown, a part of the gate electrode 117 is removed to expose the N-type shallow well region 107 (see the region 131 in FIG. 3), and the region where the N-type shallow well region 107 is exposed is exposed to N⁺A diffusion layer is formed. Although not shown, the gate electrode 117 and N⁺A contact is formed across the diffusion layer, and the gate electrode 117 and the N-type shallow well region 107 are ohmically connected. Thus, the P channel type DTMOS 22 is configured.
[0063]
The impurity concentration of the shallow well regions 106 and 107 increases the substrate bias effect factor γ by suppressing the width of the depletion layer extending from the gate electrode 117 to the channel regions 108 and 108 as in the semiconductor device of the first embodiment. In order to achieve this, the channel regions 108 and 108 'are formed to be deeper than the impurity concentration. Although not shown, in order to reduce the capacity of the shallow well regions 106 and 107 and the deep well regions 104 and 105, a shallow well having an impurity concentration lower than that of the shallow well regions 106 and 107 between them. A well region having the same conductivity type as the region may be formed.
[0064]
Silicon is used for the semiconductor thin film, but germanium, silicon germanium (SiGe), or a laminated film made of these may be used.
[0065]
Although the element isolation region may have a single depth only of the deep element isolation region 102, it is desirable that the element isolation region includes the deep element isolation region 102 and the shallow element isolation region 103 as described above. By using the shallow element isolation region 103 in combination, shallow well regions 106 and 107 exist under the shallow element isolation region 103. Therefore, the resistance of the shallow well regions 106 and 107 under the shallow element isolation region 103 can be reduced. When the potential applied to the gate electrode 117 is transmitted to the shallow wells 106 and 107, a delay expressed by the product of the resistance of the shallow well regions 106 and 107 and the junction capacitance associated with the shallow well regions 106 and 107 occurs. When this delay cannot be ignored compared with the switching time of the element, the substrate bias effect cannot be obtained effectively.
[0066]
Therefore, when the shallow element isolation region 103 is used in combination, the delay is shortened, and the substrate bias effect of DTMOS can be used effectively.
[0067]
The shallow element isolation region 103 is formed for the purpose of preventing contact between the source / drain regions, that is, the diffusion layer regions 114 and 115, and the shallow well regions 106 and 107. I just need it. Therefore, although not shown, the present invention is not limited to the manufacturing method described later in the second embodiment. For example, after the silicon film is formed on the entire surface of the shallow well region, only the silicon oxide film in the region that becomes the channel region is used. It may be formed by removing. Further, the film thickness may be set so that the impurity does not penetrate the insulating layer and is not doped into the shallow well region when the impurity is implanted into the source / drain regions.
[0068]
The impurity concentration of the channel regions 108 and 108 ′ may be determined so that the DTMOSs 21 and 22 have a desired threshold value. Channels (inversion layers) are formed in the uppermost layer portions of the channel regions 108 and 108 'when the DTMOSs 21 and 22 are in an on state. The channel regions 108 and 108 'have a maximum depletion layer width when the channel regions 108 and 108' have a uniform concentration so that the channel regions 108 and 108 'are completely depleted even when the DTMOSs 21 and 22 are off. It is preferable to determine smaller. In this case, the substrate bias effect of the DTMOSs 21 and 22 can be sufficiently obtained. Specifically, when the DTMOSs 21 and 22 are in the off state, the width of the depletion layer extending from the gate insulating film 116 side into the channel regions 108 and 108 ′ is, for example, that the impurity concentrations of the channel regions 108 and 108 ′ are uniform. 1 × 10¹⁷cm^-3In this case, the maximum depletion layer width is about 100 nm. Accordingly, the thickness of the channel regions 108 and 108 ′ is preferably 100 nm or less.
[0069]
Further, the relationship between the thickness of the channel regions 108 and 108 'and the drive current will be described in more detail. FIG. 8 shows that the off-leakage current Ioff of the DTMOS according to the present invention is 1 × 10.^-11The relationship between the drive current (μA / μm) at A / μm and the thickness D (nm) of the channel regions 108 and 108 ′ is shown. The effective channel length Leff is 200 nm, and the gate oxide film thickness Tox is 2 nm. The driving current of the DTMOS having the conventional structure is also shown by a dotted line. The DTMOS according to the second embodiment can realize a larger driving current than the conventional DTMOS. In addition, it can be seen that when D = 12 nm, the drive current has a maximum value and an optimum film thickness. As described above, the DTMOS according to the second embodiment can improve the driving force by about 80% at the maximum. Here, the result is that Ioff is 1 × 10^-11This is an example at Leff = 200 nm where the threshold voltage is set to be A / μm, and the optimum value of D also varies depending on Leff, Tox, channel concentration, and threshold voltage.
[0070]
Similar to the semiconductor device of the first embodiment, the semiconductor device of the second embodiment is different from the surface of the semiconductor substrate with respect to the electric field strength between the source and the drain as compared with the conventional structure element having a uniform channel concentration. Since the electric field strength in the vertical direction is large, there is an effect of suppressing the short channel effect. In the DTMOSs 21 and 22, the potential of the gate electrode 117 (forward bias) is transmitted from the channel regions 108 and 108 ′ to the well regions 106 and 107, so that the width of the depletion layer extending from the drains 114 and 115 can be reduced. As compared with the first embodiment, the substrate bias effect can be further increased and the short channel effect can be suppressed.
[0071]
Next, a procedure for manufacturing the semiconductor device according to the second embodiment will be described with reference to FIGS. 6 and 7 are cross-sectional views of the element in the process of being produced, and correspond to the cross section seen from the section line A-A 'in FIG.
[0072]
First, as shown in FIG. 6A, element isolation regions 102 and 103, deep well regions 104 and 105, and shallow well regions 106 and 107 are formed in a semiconductor substrate 101 by a known method. At this time, the impurity concentration in the vicinity of the exposed surfaces of the shallow well regions 106 and 107 is sufficiently higher than that of the channel region (for example, the impurity concentration of the channel region is 10%).¹⁷cm^-3In this case, the impurity concentration in the vicinity of the exposed surface is 10 times or more.¹⁸cm^-3-10²⁰cm^-3Keep it. ).
[0073]
Next, as shown in FIG. 6B, single crystal semiconductor films 108 and 108 ′ are epitaxially grown on the regions where the shallow well regions 106 and 107, which are active regions, are exposed, and on the element isolation regions 102 and 103. Deposits a polycrystalline semiconductor film 109. Since the single crystal semiconductor films 108 and 108 ′ on the active regions where the shallow well regions 106 and 107 are exposed are epitaxially grown, as shown in FIG. Is on the shallow element isolation region 103. As an example, when a silicon film is formed using a silicon substrate, the surface of the active region is cleaned by HF (hydrogen fluoride) treatment, and then, for example, 580 by low pressure chemical vapor deposition (LPCVD). ~ 700 ° C (more preferably 650-700 ° C), Si₂H₆Or SiH₄If a silicon film is deposited under a condition of gas of 20 to 100 Pa, a silicon single crystal film 108, 108 'is formed on the active region, and a polycrystalline silicon film 109 is formed on the element isolation regions 102, 103 in a self-aligned manner. Can be formed. When formed at a growth temperature of 650 ° C. or higher, the polycrystalline semiconductor film 109 having a grain size of 50 nm or less can be formed with good controllability. Accordingly, the annealing temperature for the impurity activation of the source / drain region, that is, the diffusion layer region and the diffusion up to the vicinity of the channel regions 108 and 108 ′, which are the subsequent steps, can be lowered to 800 ° C. or lower. It is possible to suppress the auto-doping from the deep shallow well region 106, 107 to the channel region 108, 108 'and keep the interface sharp.
[0074]
Next, as shown in FIG. 6C, parts of the single crystal semiconductor films 108 and 108 'and the polycrystalline semiconductor film 109 are removed by etching, and pattern processing is performed. Next, the channel regions 108 'and 108 of the P channel type DTMOS and the N channel type DTMOS are covered with a resist 110, and an N type impurity 111 (P, As, etc.) 2 × 10¹⁵~ 1x10¹⁶cm^-2inject.
[0075]
Next, as shown in FIG. 7A, after removing the resist 110, the channel regions 108 and 108 ′ of the N-channel type DTMOS and the P-channel type DTMOS are covered with the resist 112 in the same manner as in FIG. The P-type impurity 113 (B (boron) or BF) is added to the region 109 which becomes the source / drain region of the P-channel DTMOS.₃Etc.) 2 × 10¹⁵~ 1x10¹⁶cm^-2inject.
[0076]
At this time, a part of the single crystal semiconductor films 108 and 108 ′ and the polycrystalline semiconductor film 109 is patterned by etching, and then a silicon oxide film of 5 to 20 nm is formed and used as a screen oxide film at the time of implantation. May be. In addition, the resist on the channel regions 108 and 108 ′ has a design margin (DM) that allows the channel regions 108 and 108 ′ to have a design margin (DM) so that impurities are not directly implanted into the channel regions 108 and 108 ′. , 108 'are completely covered.
[0077]
Next, as shown in FIG. 7B, after removing the resist 112, an annealing process is performed so that the N-channel DTMOS has an N⁺The diffusion layer region 114 is P for the P-channel DTMOS.⁺Diffusion layer regions 115 are formed respectively. The annealing treatment is preferably performed at a temperature of 700 to 800 ° C., for example. In order to prevent impurities from being directly implanted into the channel regions 108 and 108 ′, the impurities are implanted at a position that is separated from the channel regions 108 and 108 ′ by a design margin. However, the polycrystalline semiconductor film 109 has a very large diffusion coefficient. Impurities are quickly diffused by this annealing treatment. On the other hand, impurities diffuse slowly in the single crystal semiconductor films 108 and 108 '. Therefore, by appropriately setting the annealing conditions, the impurity can be slightly exuded from the polycrystalline semiconductor film 109 into the single crystal semiconductor films 108 and 108 ′. Accordingly, the diffusion layer regions 114 and 115, that is, the source / drain regions 114 and 115 can be formed in a self-aligned manner with respect to the element isolation regions 102 and 103, and the channel width is controlled with good reproducibility. Variations between elements and lots can be reduced. Further, since the diffusion layer regions 114 and 115 and the shallow well regions 106 and 107 can be hardly contacted, the junction capacitance can be reduced. Here, this annealing treatment may be performed in an oxygen atmosphere. When annealing is performed in an oxygen atmosphere, the diffusion rate of impurities in the polycrystalline silicon film 109 can be increased as compared with, for example, a nitrogen atmosphere due to the accelerated diffusion phenomenon. Thereby, the annealing time can be shortened and the annealing temperature can be further reduced. When the gate insulating film 116 to be formed later is formed of a silicon oxide film by thermal oxidation, the silicon oxide film 116 is formed in order to activate the source / drain regions, that is, the diffusion layer regions 114 and 115. Since it can serve as an annealing process, the process can be simplified.
[0078]
Next, as shown in FIG. 7C, gate insulating films 116a and 116b and a gate electrode 117 are formed. The gate insulating film is obtained by forming a silicon oxide film using a thermal oxidation method. Then, the gate oxide film 116a is formed on the channel regions 108 and 108 ', and the film thickness is about 2 to 5 times that of the gate oxide film 116a formed on the channel regions 108 and 108' on the source and drain diffusion layers. A thick gate oxide film 116b is formed. This is because the growth rate of the thermal oxide film on the regions such as the source and drain diffusion layers 114 and 115 doped with the impurity at a high concentration is similar to that of the channel regions 108 and 108 ′ where the impurity is doped at a low concentration. It is because it is larger than the above-mentioned area. Thus, since the source and drain diffusion layers 114 and 115 doped with impurities at a high concentration are formed before the gate oxidation step, the channel regions 108 and 108 ′ are formed on the source and drain diffusion layer regions 114 and 115. A thicker gate oxide film can be formed. Therefore, the capacity of the gate electrode, the source, and the drain electrode can be reduced. Further, since this can be performed only by the gate oxidation step without adding a new process step, the production cost can be reduced. Although not shown, a part of the gate electrode 117 (region 131 in FIG. 3) is removed to form a region connecting the gate electrode 117 and the shallow well regions 106 and 107.
[0079]
Thereafter, the upper wiring and the like are formed by a known method to complete the semiconductor device.
[0080]
According to the above manufacturing procedure, the shallow well regions 106 and 107 having a high impurity concentration are formed, and then the semiconductor film to be the channel regions 108 and 108 'is formed. Therefore, the shallow well regions 106 and 107 and the channel regions 108 and 108 are formed. It is possible to have a steep profile of impurity concentration distribution near the interface with '. Therefore, a desired threshold value can be given to the DTMOS, and the depletion layer width can be easily limited by the shallow well regions 106 and 107.
[0081]
Further, according to the above manufacturing procedure, the diffusion layer regions (source / drain regions) 114 and 115 of the semiconductor device of the second embodiment can be formed in a self-aligned manner. That is, a single crystal semiconductor film 108, 108 ′ is formed on the active region and a polycrystalline semiconductor film 109 is formed on the element isolation regions 102, 103 in a self-aligned manner, and impurities are introduced into the polycrystalline semiconductor film 109. Diffusion layer regions 114 and 115 are formed. Therefore, since the diffusion layer regions 114 and 115 and the shallow well regions 106 and 107 are hardly in contact with each other, the junction capacitance associated with the diffusion layer regions 114 and 115 can be made very small. In addition, a semiconductor device having a desired structure can be obtained without using a special process device.
[0082]
(Embodiment 3)
The semiconductor device according to the third embodiment is the same as the semiconductor device according to the second embodiment except that a part of the diffusion layer region and the upper part of the gate electrode are silicided to reduce the resistance. FIG. 9 is a cross-sectional view of the semiconductor device according to the third embodiment.
[0083]
In FIG. 9, the above-mentioned reference numerals indicate the same components as those described in the second embodiment shown in FIG.
[0084]
A gate sidewall insulating film 118 is formed on the sidewall of the gate electrode 117. In addition, in the diffusion layer regions 114 and 115, the portion not covered with the gate sidewall insulating film 118 is silicided, and the upper portion of the gate electrode 117 is also silicided to form a high melting point silicide layer 119, respectively. ing. The gate sidewall insulating film 118 functions to prevent a short circuit between the gate electrode 117 and the diffusion layer regions 114 and 115, and the silicide layer 119 reaches the junction between the diffusion layer regions 114 and 115 and the channel regions 108 and 108 ′. With the function to prevent.
[0085]
In the semiconductor device according to the third embodiment, a part of diffusion layer regions 114 and 115 and the upper part of gate electrode 117 are silicided, so that these resistances can be reduced. In particular, since the diffusion layer regions 114 and 115 are thin films and originally have high resistance, the effect of reducing resistance by silicidation is great. Therefore, the drive current of DTMOS can be further increased.
[0086]
Although not shown, the configuration using gate sidewall insulating film 118 and silicide layer 119 of the semiconductor device of the third embodiment is also applicable to the semiconductor device of the first embodiment.
[0087]
【The invention's effect】
As apparent from the above, according to the semiconductor device of the present invention, the second conductivity type shallow well region having a high impurity concentration is formed under the second conductivity type channel region having a low impurity concentration, and the gate electrode is formed. Since the width of the depletion layer extending to the channel region is suppressed by the well region of the second conductivity type, the substrate bias effect can be increased and the driving current of the semiconductor device can be increased.
[0088]
Further, since the source region and the drain region are formed on the element isolation region, the junction capacitance associated with the source region and the drain region can be extremely reduced, and the source region and the drain region are formed on the source region and the drain region. Since the portion of the gate insulating film is formed thicker than the portion of the gate insulating film formed on the channel region, the capacity of the gate electrode and the source and drain regions can be reduced. . Accordingly, the power consumption of the semiconductor device can be reduced and the speed can be increased.
[0089]
In addition, since the semiconductor device according to one embodiment has a DTMOS structure in which the gate electrode and the second well-conducting shallow well region are electrically connected to each other, a larger substrate bias effect can be obtained. Thus, the drive current can be further increased, and a high speed DTMOS can be realized with low power consumption.
[0090]
Further, according to the method of manufacturing a semiconductor device of the present invention, since the element isolation region and the second conductivity type well region having a high impurity concentration are formed, the semiconductor film to be the channel region is formed. A steep profile of impurity concentration distribution can be provided in the vicinity of the interface with the shallow well region. Therefore, it is easy to give a desired threshold value to a semiconductor device such as a MOS transistor or a DTMOS and to limit the depletion layer width by the well region of the second conductivity type.
[0091]
A single crystal semiconductor film is formed in a self-aligned manner on the region where the well region of the second conductivity type is exposed, and a polycrystalline semiconductor film is formed on the element isolation region, and the impurity of the first conductivity type is formed on the element isolation region. Since the source region and the drain region are formed by introducing and diffusing into the polycrystalline semiconductor film, the source region and the drain region and the second conductivity type can be formed without using a special device or process. The shallow well region can be prevented from contacting, and the junction capacitance associated with the source region and the drain region can be extremely reduced.
[0092]
Furthermore, before forming the gate insulating film, the source region and the drain region are formed by diffusing impurities of the first conductivity type, so that the gate insulating film formed on the source region and the drain region is formed. The portion can be formed thicker than the thickness of the portion of the gate insulating film formed on the channel region, so that the capacity of the gate electrode, the source region, and the drain region can be reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a diagram for explaining in detail an overlap capacitance between a gate electrode of the present invention and a source region and a drain region.
FIG. 3 is a plan view of a semiconductor device according to a second embodiment of the present invention.
4 is a cross-sectional view taken along section line A-A ′ of FIG. 3;
5 is a cross-sectional view taken along a cutting plane line B-B ′ in FIG. 3;
FIGS. 6A, 6B, and 6C are views for explaining a manufacturing procedure of the semiconductor device according to the second embodiment of the present invention.
FIGS. 7A, 7B, and 7C are views for explaining a manufacturing procedure of the semiconductor device according to the second embodiment of the present invention.
FIG. 8 is a diagram for explaining a relationship between a drive current and a channel thickness in a semiconductor device according to a second embodiment of the present invention.
FIG. 9 is a sectional view of a semiconductor device according to a third embodiment of the present invention.
FIG. 10 is a cross-sectional view of a conventional semiconductor device.
[Explanation of symbols]
101 Semiconductor substrate
102, 103 element isolation region
104 N-type deep well region
105 P-type deep well region
106 P-type shallow well region
107 N-type shallow well region
108, 108 ′ single crystal semiconductor film
109 Polycrystalline semiconductor film
110, 112 resist
111 N-type impurities
113 P-type impurities
114 N⁺Diffusion layer area
115, 132 P⁺Diffusion layer area
116 Gate insulating film
117 Gate electrode
118 Gate sidewall insulating film
119 Silicide layer
131 P-type shallow well exposed area
11 N-channel MOS
12 P-channel MOS
21 N-channel DTMOS
22 P-channel DTMOS

Claims (9)

A semiconductor substrate;
A second conductivity type well region formed in the semiconductor substrate;
An element isolation region;
A source region and a drain region of a first conductivity type formed on the element isolation region;
A second conductivity type channel region formed between the source region and the drain region and formed on the second conductivity type well region;
A gate insulating film formed on the channel region, source region and drain region;
A gate electrode formed on the gate insulating film,
The channel region is made of a single crystal semiconductor, the source region and the drain region are made of a polycrystalline semiconductor,
The thickness of the channel region is the same as the thickness of the source region and drain region,
A part of the channel region is on the element isolation region,
The source region and drain region have a junction with the part of the channel region, but have no junction with the well region,
The impurity concentration giving the second conductivity type in the well region is higher than the impurity concentration giving the second conductivity type in the channel region, and
The semiconductor device according to claim 1, wherein a portion of the gate insulating film formed on the source region and the drain region is thicker than a portion of the gate insulating film formed on the channel region. The semiconductor device according to claim 1,
A first conductivity type deep well region formed in the semiconductor substrate;
The second conductivity type well region is a second conductivity type shallow well region formed on the first conductivity type deep well region,
A semiconductor device, wherein the gate electrode and the second conductivity type shallow well region are electrically connected. The semiconductor device according to claim 2,
The element isolation region is
A deep isolation region having a depth deeper than a junction depth between the first conductivity type deep well region and the second conductivity type shallow well region;
A shallow element isolation region which is an insulating layer having a depth shallower than a junction depth between the first conductivity type deep well region and the second conductivity type shallow well region;
The shallow device isolation region is located between the source region and the drain region and the shallow well region of the second conductivity type. The semiconductor device according to claim 1,
A semiconductor device, wherein a part of the source region and the drain region is silicided. The semiconductor device according to claim 1 ,
A semiconductor device, wherein the polycrystalline semiconductor has a particle size of 50 nm or less. The semiconductor device according to claim 1,
The impurity concentration giving the second conductivity type in the well region of the second conductivity type is 10 ¹⁸ cm ⁻³ to 10 ²⁰ cm ⁻³ , which is 10 than the impurity concentration giving the second conductivity type in the channel region. A semiconductor device characterized by being darker than twice. Forming a second conductivity type well region and an element isolation region on a semiconductor substrate in a state where the second conductivity type well region and the element isolation region are exposed on the surface;
While the selectively-single crystalline semiconductor film in the second shallow well region conductivity type is exposed region is epitaxially grown, in the isolation region under the growing selectively polycrystalline semiconductor film, and the single the thickness of the crystalline semiconductor film is the same as the thickness of the polycrystalline semiconductor film, or one, the part of the single crystal semiconductor film, is on the element isolation region, the polycrystalline semiconductor film, the Depositing a semiconductor film on the surface so as to have a bond with the part of the single crystal semiconductor film but not with the well region ;
Introducing a first conductivity type impurity into the polycrystalline semiconductor film;
Diffusing the first conductivity type impurity to form a source region and a drain region;
And a step of forming a gate insulating film on the channel region, the source region, and the drain region made of the single crystal semiconductor film by a thermal oxidation method. In the manufacturing method of the semiconductor device according to claim 7 ,
The step of depositing the semiconductor film on the surface comprises forming the semiconductor film at a growth temperature of 650 ° C. or higher by chemical vapor deposition. In the manufacturing method of the semiconductor device according to claim 7 ,
The method of manufacturing a semiconductor device, wherein the step of diffusing the first conductivity type impurity to form the source region and the drain region is performed in an oxygen atmosphere.

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