JP4015968B2 - Ferroelectric memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a ferroelectric memory that stores data in a nonvolatile manner using a ferroelectric capacitor.
[0002]
[Prior art]
The ferroelectric memory stores binary data in a nonvolatile manner according to the magnitude of the remanent polarization of the ferroelectric capacitor. A memory cell of a conventional ferroelectric memory is configured by connecting a ferroelectric capacitor and a transistor in series like a DRAM, for example. However, unlike a DRAM, a ferroelectric memory retains data with the amount of remanent polarization, and therefore it is necessary to drive a plate line in order to read signal charges to a bit line. For this reason, in the conventional ferroelectric memory, the plate line driving circuit requires a large area.
[0003]
On the other hand, a ferroelectric memory cell array system capable of reducing the area of the plate line driving circuit has been proposed by Takashima et al. (Non-Patent Document 1). In this method, a memory cell is formed by connecting both ends of a ferroelectric capacitor to the source and drain of a cell transistor, and a plurality of memory cells are connected in series to form a memory cell block. In this TC parallel unit serial connection type ferroelectric memory, for example, the plate line driving circuit can be shared by eight memory cells, so that the memory cell array can be highly integrated.
[0004]
In the TC parallel unit serial connection type ferroelectric memory configured as described above, a dummy bit line is arranged outside the memory cell array, and the dummy bit line is fixed to a ground potential, for example, so as to function as a shield line. Preventing noise from the outside of the cell array has been put into practical use.
[0005]
In addition, a ferroelectric memory has been proposed in which dummy bit lines are arranged outside the memory cell array to compensate for capacitive coupling of bit lines at the ends of the memory cell array (Patent Document 1).
[0006]
[Non-Patent Document 1]
D. Takashima et al., “High-density chain feroelectric random memory (CFRAM)” in Proc. VSLI Symp., June 1997, pp. 83-84
[0007]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-200061
[0008]
[Problems to be solved by the invention]
Incidentally, when detecting data read to a bit line arranged in a memory cell array, the influence of noise (hereinafter referred to as coupling noise) generated by parasitic capacitance between wirings is known. When there are two bit lines arranged at the same pitch on both sides of a certain bit line, assuming that the coupling noise received from one bit line is δ, the coupling noise δ received from the other bit line is In total, 2δ coupling noise is generated.
[0009]
However, in the case of the bit line arranged at the end of the memory cell array, coupling noise is not received from the dummy bit line fixed to the ground potential. Therefore, the bit line arranged at the end of the memory cell array receives only the coupling noise δ from one bit line. For example, when data is detected by the two-transistor-two-capacitor (2T2C) method, when “1” is read to the bit line arranged at the end of the memory cell array and “0” is read to the adjacent bit line, the difference in read potential is As a result, the sense margin is reduced by δ.
[0010]
As described above, there is a problem that the sense margin is reduced due to an imbalance of coupling noise between the bit lines at the end of the memory cell array, leading to deterioration in retention characteristics and a decrease in yield rate.
[0011]
The present invention has been made in view of the circumstances as described above, and can prevent a decrease in the sense margin of the bit line arranged at the end of the memory cell array, thereby improving the retention characteristics and the yield rate. An object of the present invention is to provide a ferroelectric memory.
[0012]
[Means for Solving the Invention]
In the ferroelectric memory according to the first aspect of the present invention, each electrode of the ferroelectric capacitor is electrically connected to the source and drain regions of the cell transistor, and the memory cell is configured. A plurality of memory cells are electrically connected in series between two terminals, the first terminal is electrically connected to a bit line via a block selection transistor, and the second terminal is a plate A memory cell block is configured by being electrically connected to a line, the memory cell block being arranged in a matrix, and the bit line outside the bit line disposed at the end of the memory cell array To a first dummy bit line which is arranged at the same interval as the pitch between the bit lines in the memory cell array and has a wiring width equivalent to the bit line; It is electrically connected to the first dummy bit line, and comprises a first dummy memory cell blocks having the same structure as the memory cell block .
[0013]
In the ferroelectric memory according to the second aspect of the present invention, each of the electrodes of the ferroelectric capacitor is electrically connected to the source and drain regions of the cell transistor, and the memory cell is configured. A plurality of memory cells are electrically connected in series between two terminals, the first terminal is electrically connected to a bit line via a block selection transistor, and the second terminal is a plate A memory cell block is configured by being electrically connected to a line, and a bit line connected to the first memory cell array is shared with a first memory cell array in which the memory cell blocks are arranged in a matrix. A second memory cell array disposed adjacent to the first memory cell array and having the same structure as the first memory cell array, and the first memory cell array. A wiring width which is arranged outside the bit line arranged at the end portion of the array at the same interval as the pitch between the bit lines in the first memory cell array from the bit line, and equivalent to the bit line A first dummy bit line having a first dummy memory cell block electrically connected to the first dummy bit line and having the same structure as the memory cell block; and Outside the bit line arranged at the end portion, the bit line is arranged at the same interval as the pitch between the bit lines in the second memory cell array, and has the same wiring width as the bit line. A second dummy bit line; and a second dummy memory cell block electrically connected to the second dummy bit line and having the same structure as the memory cell block That .
[0014]
In the ferroelectric memory according to the third aspect of the present invention, each of the electrodes of the ferroelectric capacitor is electrically connected to the source and drain regions of the cell transistor, and the memory cell is formed. A plurality of memory cells are electrically connected in series between two terminals, the first terminal is electrically connected to a bit line via a block selection transistor, and the second terminal is a plate A memory cell block is configured by being electrically connected to a line, the memory cell block is arranged in a matrix, and a dummy arranged outside a bit line arranged at an end of the memory cell array A bit line, a capacitor having one electrode electrically connected to the dummy bit line, and an output side electrically connected to the other electrode of the capacitor; Side is electrically connected to the plate line, and includes a dummy bit line drive circuit for detecting the driving of said plate line .
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention configured based on such knowledge will be described with reference to the drawings. In the following description, components having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.
[0016]
(First embodiment)
FIG. 1 is a circuit diagram showing a memory cell block MCB constituting a TC parallel unit serial connection type ferroelectric memory in the first embodiment of the present invention.
[0017]
The memory cell MC is constituted by a parallel connection of a ferroelectric capacitor C and a cell transistor T. For example, eight memory cells MC are connected in series to form a memory cell block MCB. FIG. 1 shows two memory cell blocks MCB0 and MCB1 that are electrically connected to a pair of bit lines BL and / BL. In addition, the connection here means that it is electrically connected.
[0018]
One end of each of the memory cell blocks MCB0 and MCB1 is connected to the bit lines BL and / BL via the block selection transistors BST0 and BST1. The other ends of memory cell blocks MCB0 and MCB1 are connected to plate lines PL and / PL. The gate of the cell transistor T of each memory cell block MCB is connected to the word lines WL0 to WL7. The gates of the block selection transistors BST0 and BST1 are connected to the block selection signal lines BSL0 and BSL1.
[0019]
As a data holding method for a ferroelectric memory, a 2T2C method for holding 1-bit data using two cell transistors and two ferroelectric capacitors, and one cell transistor and one ferroelectric capacitor are used. There are two methods of 1T1C method that hold 1-bit data. The TC parallel unit serial connection type ferroelectric memory shown in FIG. 1 is configured to be shared between the 2T2C system and the 1T1C system.
[0020]
In the 1T1C method, a reference voltage generation circuit RVG that generates a reference voltage is generated by dummy word transistors DWT1 and DWT2 and a reference capacitor RC. One electrode of the reference capacitor RC is connected to the dummy plate line DPL. The other electrode of reference capacitor RC is connected to the source / drain of dummy word transistors DWT1 and DWT2. The drain / source of the dummy word transistor DWT1 is connected to the bit line / BL. The drain / source of the dummy word transistor DWT2 is connected to the bit line BL. The gate of the dummy word transistor DWT1 is connected to the dummy word line DWL1. The gate of the dummy word transistor DWT2 is connected to the dummy word line DWL2.
[0021]
A sense amplifier circuit SA for detecting and amplifying read data is connected to the bit lines BL and / BL.
[0022]
FIG. 2 is an operation timing chart in the 2T2C system of the memory cell block MCB configured as described above. The memory cell MC stores data “1” when the remanent polarization of the ferroelectric capacitor C is positive and data “0” when the remanent polarization is negative. During standby, all word lines WL are kept at “H”, block selection signal lines BSL0 and BSL1 are kept at “L”, and bit lines BL and / BL and plate lines PL and / PL are kept at VSS (ground potential). At this time, the ferroelectric capacitor C is short-circuited between the terminals by the on-state cell transistor, and holds the data stably.
[0023]
For example, when the memory cell MC on the bit line BL side is selected by the word line WL2 when active, for example, the bit line BL is floated, the word line WL2 is set to “L”, and then the block selection signal line BSL0 is set to “H”. And the plate line PL is raised from VSS (ground potential) to VAA (positive potential). As a result, a voltage is applied to the ferroelectric capacitor C of the selected memory cell MC, and a signal voltage is read to the bit line BL in accordance with the data “0” and “1”. Note that data complementary to the memory cell MC on the bit line BL side is stored in the memory cell MC on the bit line / BL side selected by the word line WL2, and the block selection signal line BSL1 is set to “H”. As a result, the signal voltage is similarly read to the bit line / BL in accordance with the data “0” and “1”.
[0024]
The signal voltages read to the bit line BL and the bit line / BL are compared and amplified by activating the sense amplifier circuit SA to detect data “0” and “1”. Thereafter, the read data is rewritten by deactivating the sense amplifier circuit SA.
[0025]
In this read and rewrite operation, “1” data is destructive read, and “0” data is nondestructive read. That is, in the case of “1” data, application of a positive voltage from the plate line greatly reduces the remanent polarization of the ferroelectric capacitor and causes polarization reversal. When the voltage of the plate line is lowered after reading, the bit line is at a higher potential due to the read data, and therefore, a reverse voltage is applied to the ferroelectric capacitor at the time of reading and rewriting is performed. In the case of “0” data, polarization inversion due to the plate line voltage does not occur, and no reverse voltage is applied after reading, and the original negative remanent polarization state is rewritten.
[0026]
On the other hand, FIG. 3 is an operation timing chart in the 1T1C system of the memory cell block MCB shown in FIG.
[0027]
For example, when the memory cell MC on the bit line BL side is selected by the word line WL2 when active, for example, the bit line BL is floated, the word line WL2 is set to “L”, and then the block selection signal line BSL0 is set to “H”. And the plate line PL is raised from VSS (ground potential) to VAA (positive potential). Further, the dummy word line DWL1 is set to “H”, and the reference potential is applied to the bit line / BL.
[0028]
The signal voltage read to the bit line BL is compared and amplified with the reference potential by activating the sense amplifier circuit SA, and data “0” and “1” are detected.
[0029]
FIG. 4 is a schematic circuit diagram showing a main configuration of the TC parallel unit serial connection type ferroelectric memory according to the first embodiment of the present invention.
[0030]
A memory cell array MCA is formed by arranging a plurality of memory cell blocks MCB0 and MCB1 shown in FIG.
[0031]
BL0 and / BL0 are connected to data lines DQ0 and / DQ0 via data selection transistors DST0 and DST1, respectively. A column decoder CD (not shown) is connected to each gate of the data selection transistors DST0 and DST1, and when a column selection signal is input from the column selection signal line CSL0, data is output from the data lines DQ0 and / DQ0. The
[0032]
On the outside of the memory cell array MCA, dummy bit lines DummyBL and Dummy / BL are spaced from the bit line BL0 arranged at the end of the memory cell array MCA at the same interval as the pitch of the bit line pairs in the memory cell array MCA. Is placed. The dummy bit lines DummyBL and Dummy / BL have a wiring width equivalent to that of the bit lines in the memory cell array MCA. The dummy bit lines DummyBL, Dummy / BL are connected to the memory cell block MCB, respectively, and further connected to the reference voltage generation circuit RVG and the sense amplifier circuit SA. Here, the data line and the column gate are not connected to the dummy bit lines DummyBL, Dummy / BL.
[0033]
The operation of the 2T2C system of the TC parallel unit serial connection type ferroelectric memory configured as described above will be described. FIG. 5 is a diagram illustrating the parasitic capacitance Cbb between the bit lines and the coupling noise δ generated by the parasitic capacitance Cbb.
[0034]
In order to read data stored in the memory cells MC connected to the word line WLn, VAA (positive potential) is applied to the plate lines PL and / PL. For example, it is assumed that data “1” is read to the dummy bit line DummyBL and the bit lines BL0 and BL1, respectively. In the case of the 2T2C system, data “0” is read into Dummy / BL, / BL0, and / BL1, respectively.
[0035]
When VAA (positive potential) is applied to the plate lines PL, / PL and data is read out to each bit line, coupling noise δ is instantaneously generated in each bit line due to the parasitic capacitance Cbb between the bit lines. Bit line / BL0 receives 2δ coupling noise from adjacent bit lines BL0 and BL1. In addition, since the dummy bit lines DummyBL and Dummy / BL are provided, the bit line BL0 arranged at the end of the memory cell array MCA also generates 2δ coupling noise from the adjacent dummy bit line Dummy / BL and bit line / BL0. To receive.
[0036]
Thereby, when the sense amplifier circuit SA detects the data read from the bit line pair BL0, / BL0, the read potentials of the data “0” of the bit line BL0 and the data “0” of the bit line / BL0 are both. Increase by 2δ. Therefore, as with the bit lines inside the memory cell array MCA, coupling noise imbalance does not occur.
[0037]
FIG. 6 is a diagram illustrating the parasitic capacitance Cbb between the bit lines in the 1T1C system and the coupling noise δ generated by the parasitic capacitance Cbb.
[0038]
For example, it is assumed that data “1” is read out to DummyBL, BL0, and BL1, respectively. In the case of the 1T1C system, the reference potential RV is applied to each of Dummy / BL, / BL0, and / BL1. When VAA (positive potential) is applied to the plate lines PL, / PL, coupling noise δ is instantaneously generated in each bit line due to the parasitic capacitance Cbb between the bit lines. Therefore, as in the case of the 2T2C method, the bit line BL0 arranged at the end of the memory cell array MCA receives 2δ coupling noise from the adjacent dummy bit line Dummy / BL and bit line / BL0. become.
[0039]
Next, in the 1T1C system, for example, data “0” is read to Dummy / BL, / BL0, and / BL1, respectively. FIG. 7 is a diagram illustrating the parasitic capacitance Cbb between the bit lines and the coupling noise δ generated by the parasitic capacitance Cbb in this case.
[0040]
In the case of the 1T1C method, when “0” data is read to each of Dummy / BL, / BL0, and / BL1, the reference potential RV is applied to each of DummyBL, BL0, and BL1. When VAA (positive potential) is applied to the plate lines PL, / PL, coupling noise δ is instantaneously generated in each bit line due to the parasitic capacitance Cbb between the bit lines. Therefore, as in the case of the 2T2C method, the bit line BL0 arranged at the end of the memory cell array MCA receives 2δ coupling noise from the adjacent dummy bit line Dummy / BL and bit line / BL0. become.
[0041]
As described in detail above, in the present embodiment, DummyBL and Dummy / BL are spaced outside the bit line BL0 arranged at the end of the memory cell array MCA with the same pitch as the pitch between the bit lines in the memory cell array MCA. Is arranged. Further, DummyBL and Dummy / BL have the same wiring width as the bit lines in the memory cell array MCA. Further, the sense amplifier circuit SA is connected to DummyBL, Dummy / BL, and the data line DQ is not connected.
[0042]
Therefore, according to the present embodiment, it is possible to suppress an imbalance of coupling noise that occurs in the bit line arranged at the end of the memory cell array MCA. As a result, a decrease in the sense margin of the sense amplifier circuit SA can be prevented, and data can be detected accurately.
[0043]
Further, since the sense amplifier circuit SA is connected to DummyBL and Dummy / BL, the same operation as the bit line in the memory cell array MCA is possible. Therefore, the same coupling noise as that of other bit lines can be generated for the bit line BL0.
[0044]
Further, since the data line DQ is not connected to DummyBL and Dummy / BL, an extra circuit can be omitted and the circuit space can be reduced.
[0045]
(Second Embodiment)
In the second embodiment, dummy bit line pairs are arranged outside the memory cell array MCA, and dummy bit lines connected to VSS (ground potential) are arranged outside the dummy bit line pairs.
[0046]
FIG. 8 is a schematic circuit diagram showing a main configuration of a TC parallel unit serial connection type ferroelectric memory according to the second embodiment of the present invention. The configurations of the memory cell array MCA and the dummy bit line pairs DummyBL1, Dummy / BL1 are the same as those in the first embodiment.
[0047]
On the outside of the dummy bit line DummyBL1, the dummy bit line Dummy / BL0 is arranged at the same interval as the pitch of the bit line pair in the memory cell array MCA from the dummy bit line DummyBL1. The potential of the dummy bit line Dummy / BL0 is fixed to VSS (ground potential).
[0048]
The TC parallel unit serial connection type ferroelectric memory configured as described above can eliminate the unbalance of the coupling noise generated in the bit line BL0 as in the first embodiment. Further, in order to prevent external noise to the memory cell array MCA and the dummy bit line pair DummyBL1, Dummy / BL1, a dummy bit line Dummy / BL0 fixed to VSS (ground potential) is provided.
[0049]
Therefore, according to the present embodiment, it is possible to eliminate an imbalance of coupling noise that occurs in the bit line arranged at the end of the memory cell array MCA. As a result, a decrease in the sense margin of the sense amplifier circuit SA can be prevented, and data can be detected accurately.
[0050]
Further, the dummy bit line Dummy / BL0 functions as a shield line, and noise from the outside of the memory cell array MCA can be prevented.
[0051]
The interval between the dummy bit lines DummyBL1 and Dummy / BL0 can be similarly applied even if the pitch between the bit line pairs in the memory cell array MCA is not the same.
[0052]
(Third embodiment)
FIG. 9 is a schematic circuit diagram showing a main configuration of a TC parallel unit serial connection type ferroelectric memory according to the third embodiment of the present invention. The configuration of the memory cell block MCB is the same as that in the first embodiment.
[0053]
Memory cell arrays MCA1 and MCA2 are formed by arranging a plurality of memory cell blocks MCB. Memory cell arrays MCA1 and MCA2 are connected by a common bit line pair. A sense amplifier circuit SA is connected between the memory cell arrays MCA1 and MCA2 of this common bit line pair. A column decoder CD is connected to the sense amplifier circuit SA.
[0054]
A cell array select transistor AST1 is connected between the memory cell array MCA1 of the bit line BL0 and the sense amplifier circuit SA. On the other hand, a cell array select transistor AST2 is connected between the memory cell array MCA2 of the bit line BL0 and the sense amplifier circuit SA. The gate of the cell array selection transistor AST1 is connected to the memory cell array selection line ASL1. The gate of the cell array selection transistor AST2 is connected to the memory cell array selection line ASL2. Similarly, cell array select transistors AST1 and AST2 are connected to other bit lines. The memory cell arrays MCA1 and MCA2 can be selected by the memory cell array selection lines ASL1 and ASL2, and one sense amplifier circuit SA and column decoder CD can be shared.
[0055]
On the outside of the memory cell array MCA1, dummy bit lines Dummy / BL are arranged with the same pitch as the bit line pairs in the memory cell array MCA1 from the bit line BL0 arranged at the end of the memory cell array MCA1. Dummy / BL has a wiring width equivalent to that of the bit line in the memory cell array MCA1. A memory cell block MCB and a reference voltage generation circuit RVG1 are connected to Dummy / BL. The reference voltage generation circuit RVG1 includes a dummy word transistor DWTn and a reference capacitor RCn. One electrode of the reference capacitor RCn is connected to the dummy plate line DPLn. The other electrode of reference capacitor RCn is connected to the source / drain of dummy word transistor DWTn. The drain / source of the dummy word transistor DWTn is connected to Dummy / BL.
[0056]
On the outside of the memory cell array MCA2, dummy bit lines DummyBL are arranged at the same pitch as the bit line pairs in the memory cell array MCA2 from the bit line BL0 arranged at the end of the memory cell array MCA2. DummyBL has a wiring width equivalent to that of the bit line in the memory cell array MCA2. A memory cell block MCB and a reference voltage generation circuit RVG2 are connected to this DummyBL. The reference voltage generation circuit RVG2 includes a dummy word transistor DWTm + 1 and a reference capacitor RCm. One electrode of the reference capacitor RCm is connected to the dummy plate line DPLm. The other electrode of reference capacitor RCm is connected to the source / drain of dummy word transistor DWTm + 1. The drain / source of the dummy word transistor DWTm + 1 is connected to DummyBL.
[0057]
This DummyBL and Dummy / BL are connected by a sense amplifier circuit SA. Incidentally, the memory cell block MCB connected to Dummy / BL is connected to a word line arranged in the memory cell array MCA1. The memory cell block MCB connected to DummyBL is connected to a word line arranged in the memory cell array MCA2. As described above, a memory cell block MCB connected to a dummy bit line pair composed of DummyBL and Dummy / BL is connected to a different word line is called an open bit line system (open bit line system).
[0058]
In the TC parallel unit serial connection type ferroelectric memory configured as described above, the bit line BL0 on the memory cell array MCA1 side receives 2δ coupling noise from the adjacent bit line / BL0 and dummy bit line Dummy / BL. .
[0059]
The bit line BL0 on the memory cell array MCA2 side receives 2δ coupling noise from the adjacent bit line / BL0 and the dummy bit line DummyBL.
[0060]
As described above in detail, in the present embodiment, in the TC parallel unit serial connection type ferroelectric memory in which the bit line and the sense amplifier circuit SA are shared and the two memory cell arrays MCA1 and MCA2 are selected to detect data, One of the bit line pairs DummyBL, Dummy / BL is arranged outside the memory cell array MCA1 at the same pitch as the bit line pairs in the memory cell array MCA1. The other dummy bit line is arranged outside the memory cell array MCA2 at the same pitch as the bit line pair in the memory cell array MCA2. The dummy bit lines DummyBL and Dummy / BL have the same wiring width as the bit lines in each memory cell array MCA.
[0061]
Therefore, according to the present embodiment, it is possible to eliminate an imbalance of coupling noise generated in the bit line arranged at the end of each memory cell array MCA. As a result, a decrease in the sense margin of the sense amplifier circuit SA can be prevented, and data can be detected accurately.
[0062]
In addition, since the dummy bit line pairs are opened and arranged in each memory cell array MCA, an increase in chip area can be suppressed as compared with the case where dummy bit line pairs are arranged in each memory cell array MCA.
[0063]
Further, a dummy bit line DummyBL0 whose potential is fixed to VSS (ground potential) may be arranged outside the dummy bit line pair DummyBL, Dummy / BL. FIG. 10 is a schematic circuit diagram showing a main configuration of the TC parallel unit serial connection type ferroelectric memory configured as described above.
[0064]
The dummy bit lines Dummy / BL0 are arranged outside the dummy bit line pairs DummyBL, Dummy / BL at the same pitch as the pitch of the bit line pairs arranged in the memory cell array MCA.
[0065]
With such a configuration, it is possible to prevent noise from the outside to the memory cell array MCA and the dummy bit line pair DummyBL, Dummy / BL.
[0066]
Note that the dummy bit line Dummy / BL0 may be arranged in the same manner even if the pitch is not the same as that of the other bit line pairs.
[0067]
(Fourth embodiment)
In the fourth embodiment, a dummy bit line is arranged outside the memory cell array MCA, and a reference potential is applied to the dummy bit line.
[0068]
FIG. 11 is a schematic circuit diagram showing a main configuration of a TC parallel unit serial connection type ferroelectric memory according to the fourth embodiment of the present invention. The configuration of the memory cell array MCA is the same as that in the first embodiment.
[0069]
On the outside of the memory cell array MCA, dummy bit lines Dummy / BL are arranged at the same interval as the pitch of the bit line pairs in the memory cell array MCA from the bit line BL0 arranged at the end of the memory cell array MCA. The Although the memory cell block MCB is disposed on the dummy bit line Dummy / BL, the connection between the dummy bit line and the plate line is disconnected.
[0070]
One electrode of the capacitor C1 is connected to the dummy bit line Dummy / BL. The other electrode of capacitor C1 is connected to plate lines PL, / PL via an OR circuit. Note that the capacitance of the capacitor C1 is set such that, for example, an intermediate value between read potentials of “1” data and “0” data is applied to the dummy bit line Dummy / BL.
[0071]
When the TC parallel unit serial connection type ferroelectric memory configured as described above is active, a reference potential is applied to the dummy bit line Dummy / BL. As a result, the coupling noise δ from the bit line / BL0 and the coupling noise δ ′ based on the reference voltage from the dummy bit line Dummy / BL are generated in the bit line BL0.
[0072]
Therefore, according to the present embodiment, it is possible to suppress an imbalance of coupling noise that occurs in the bit line arranged at the end of the memory cell array MCA.
[0073]
Further, since the number of dummy bit lines is one, it is possible to reduce the area of the chip compared to the case where dummy bit line pairs are arranged.
[0074]
In the above embodiment, the OR circuit is used as an example of the circuit that detects the driving of the plate line. However, the present invention is not limited to this, and any circuit that can detect the drive of the plate line may be used.
[0075]
(Fifth embodiment)
In the fifth embodiment, dummy memory cell blocks DMCB are arranged outside the memory cell array MCA.
[0076]
FIG. 12 is a schematic circuit diagram showing a main configuration of a TC parallel unit serial connection type ferroelectric memory according to the fifth embodiment of the present invention. The configuration of the memory cell array MCA is the same as that in the first embodiment.
[0077]
A dummy memory cell block DMCB is arranged outside the memory cell array MCA. Then, normally, the dummy bit line arranged outside the memory cell array MCA and having the potential fixed to VSS is removed.
[0078]
In the TC parallel unit serial connection type ferroelectric memory configured as described above, the bit line BL0 is not affected by the wiring capacity from the dummy bit line fixed to VSS. As a result, the capacity of the bit line BL0 becomes lighter than other bit lines in the memory cell array MCA.
[0079]
Therefore, according to the present embodiment, the coupling noise from the other bit lines in the memory cell array MCA with respect to the bit line BL0 increases. Therefore, the coupling noise imbalance of the bit line BL0 can be suppressed.
[0080]
(Sixth embodiment)
FIG. 13 is a plan view showing the main part of a TC parallel unit serial connection type ferroelectric memory according to the sixth embodiment of the present invention. 14 is a cross-sectional view taken along line 14-14 ′ in FIG.
[0081]
A stitch area is formed in the memory cell array MCA (between the bit line / BLn + 1 and the bit line BLn + 2 in this embodiment). This stitch region is provided in order to suppress the delay of the signal of the word line WL and the block selection signal line BSL, and is connected to a metal wiring (in this embodiment, a three-layer metal in parallel with the word line WL and the block selection signal line BSL). Wirings M1, M2, and M3) are arranged, and each time a predetermined memory cell block MCB is passed through, the gate wiring GC and the metal wiring are connected.
[0082]
The configuration of the stitch region will be described by taking the word line WL1 as an example. The gate wiring WL1 (GC) is connected to the first layer metal wiring WL1 (M1) 2 through the plug 1. WL1 (M1) 2 is connected to the second layer metal wiring WL1 (M2) 4 through the plug 3. WL 1 (M 2) 4 is connected to the third layer metal wiring WL 1 (M 3) through the plug 5.
[0083]
FIG. 15 is a schematic circuit diagram showing a main configuration of the TC parallel unit serial connection type ferroelectric memory shown in FIG.
[0084]
Dummy bit lines DummyBL, Dummy / BL are arranged on both sides of the stitch region. These DummyBL and Dummy / BL are arranged at the same pitch as the bit line pair in the memory cell array MCA from the adjacent bit lines / BLn + 1 and BLn + 2. The dummy bit lines DummyBL and Dummy / BL have a wiring width equivalent to that of the bit lines in the memory cell array MCA. The dummy bit lines DummyBL, Dummy / BL are connected to the memory cell block MCB, respectively, and further connected to the reference voltage generation circuit RVG and the sense amplifier circuit SA. Here, the data line and the column gate are not connected to DummyBL and Dummy / BL.
[0085]
In the TC parallel unit serial connection type ferroelectric memory configured as described above, the pitch between the bit line / BLn + 1 and the bit line BLn + 1 and the pitch between the bit line / BLn + 1 and the dummy bit line DummyBL are the same. Therefore, bit line / BLn + 1 receives the same coupling noise δ from the bit lines at both ends. The same applies to the bit line BLn + 2.
[0086]
As described above in detail, in the present embodiment, dummy bit lines DummyBL and Dummy / BL are provided on both sides of the stitch area in order to eliminate the imbalance between the bit lines caused by forming the stitch area in the memory cell array MCA. Deploy. Also, DummyBL and Dummy / BL have the same wiring width as the bit lines in the memory cell array MCA.
[0087]
Therefore, according to the present embodiment, the pitch of the bit lines arranged on both sides of the bit line / BLn + 1 and the bit line BLn + 2 can be made the same, and coupling noise generated on the bit line / BLn + 1 and the bit line BLn + 2 can be reduced. Balance can be suppressed. As a result, a decrease in the sense margin of the sense amplifier circuit SA can be prevented, and data can be detected accurately.
[0088]
Further, since the sense amplifier circuit SA is connected to DummyBL and Dummy / BL, the same operation as the bit line in the memory cell array MCA is possible. Therefore, the same coupling noise as that of other bit lines can be generated for the bit line BL0.
[0089]
Further, since the data line DQ is not connected to DummyBL and Dummy / BL, an extra circuit can be omitted and the circuit space can be reduced.
[0090]
(Seventh embodiment)
In the seventh embodiment, dummy bit line pairs are arranged on both sides of a stitch region formed in a memory cell array MCA so as to suppress an imbalance of coupling noise generated between the bit lines. .
[0091]
FIG. 16 is a schematic circuit diagram showing the main configuration of a TC parallel unit serial connection type ferroelectric memory according to the seventh embodiment of the present invention. The configuration of the stitch area is the same as that of the sixth embodiment.
[0092]
Dummy bit line pairs are arranged on both sides of the stitch region. The dummy bit line pair DummyBLn, Dummy / BLn is arranged between the stitch region and the bit line / BLn. Arranged at the same interval as the pitch of the bit line pairs in the MCA. The dummy bit lines DummyBLn and Dummy / BLn have the same wiring width as the bit lines in the memory cell array MCA. The dummy bit lines DummyBLn and Dummy / BLn are connected to the memory cell block MCB, respectively, and further connected to the reference voltage generation circuit RVG and the sense amplifier circuit SA. Here, the data line and the column gate are not connected to DummyBL and Dummy / BL.
[0093]
The dummy bit line pair DummyBLn + 1, Dummy / BLn + 1 is arranged between the stitch region and the bit line BLn + 1. Other configurations are the same as those of the dummy bit line pair DummyBLn, Dummy / BLn.
[0094]
In the TC parallel unit serial connection type ferroelectric memory configured as described above, the interval between the bit line / BLn and the dummy bit line pair DummyBLn and the interval between the dummy bit line pair DummyBLn and Dummy / BLn are determined by the memory cell array MCA. The bit lines are arranged at the same interval as the pitch of the bit line pairs. Therefore, the wiring parasitic capacitance between the bit line / BLn and the dummy bit line pair DummyBLn and the wiring parasitic capacitance between the dummy bit line pair DummyBLn and Dummy / BLn are the same. As a result, the same coupling noise as that of the bit line in the memory cell array MCA is generated from Dummy / BLn to the bit line / BLn.
[0095]
Therefore, according to the present embodiment, in addition to the effects of the sixth embodiment, coupling noise imbalance due to the parasitic parasitic capacitance between the dummy bit line pair DummyBLn and Dummy / BLn is further suppressed with respect to the bit line / BLn. can do. The same applies to the bit line BLn + 1.
[0096]
Note that the TC parallel unit serial connection type ferroelectric memory of each of the above embodiments is configured so that the 2T2C method and the 1T1C method can be shared. Is possible.
[0097]
In each of the above embodiments, the TC parallel unit serial connection type ferroelectric memory has been described as an example of the ferroelectric memory. However, the present invention is not limited to this. FIG. 17 is a diagram showing a main part of another example of the ferroelectric memory.
[0098]
The gate of the transistor T is connected to the word line WL. The source or drain region of the transistor T is connected to the bit line BL. The drain or source region of the transistor T is connected to one electrode of the ferroelectric capacitor C. The other electrode of the ferroelectric capacitor C is connected to a plate line to form a memory cell MC ′. That is, the transistor T and the ferroelectric capacitor C are connected in series. A plurality of the memory cells are arranged to form a memory cell array. The same effect can be obtained even when the ferroelectric memory configured as described above is applied to each of the above embodiments.
[0099]
The present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the scope of the present invention.
[0100]
【The invention's effect】
As described above in detail, according to the present invention, a ferroelectric memory capable of preventing a decrease in the sense margin of the bit line arranged at the end of the memory cell array and thereby improving the retention characteristics and the yield rate. Can be provided.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a memory cell block MCB constituting a TC parallel unit serial connection type ferroelectric memory according to a first embodiment of the present invention;
FIG. 2 is an operation timing chart in the 2T2C system of the memory cell block MCB shown in FIG.
3 is an operation timing chart in the 1T1C system of the memory cell block MCB shown in FIG.
FIG. 4 is a schematic circuit diagram showing a main configuration of a TC parallel unit serial connection type ferroelectric memory according to the first embodiment of the present invention;
5 shows an example representing a parasitic capacitance Cbb between bit lines and a coupling noise δ generated by the parasitic capacitance Cbb in the 2T2C system of the TC parallel unit serial connection type ferroelectric memory shown in FIG. 4; Figure.
6 shows an example representing a parasitic capacitance Cbb between bit lines and a coupling noise δ generated by the parasitic capacitance Cbb in the 1T1C system of the TC parallel unit serial connection type ferroelectric memory shown in FIG. 4; Figure.
7 is another example showing the parasitic capacitance Cbb between the bit lines and the coupling noise δ generated by the parasitic capacitance Cbb in the 1T1C system of the TC parallel unit serial connection type ferroelectric memory shown in FIG. 4; FIG.
FIG. 8 is a schematic circuit diagram showing a main configuration of a TC parallel unit serial connection type ferroelectric memory according to a second embodiment of the present invention;
FIG. 9 is a schematic circuit diagram showing a main configuration of a TC parallel unit serial connection type ferroelectric memory according to a third embodiment of the present invention.
10 is a schematic circuit diagram showing another embodiment of the TC parallel unit serial connection type ferroelectric memory shown in FIG. 9;
FIG. 11 is a schematic circuit diagram showing a main configuration of a TC parallel unit serial connection type ferroelectric memory according to a fourth embodiment of the present invention.
FIG. 12 is a schematic circuit diagram showing a main configuration of a TC parallel unit serial connection type ferroelectric memory according to a fifth embodiment of the present invention;
FIG. 13 is a plan view showing a main part of a TC parallel unit serial connection type ferroelectric memory according to a sixth embodiment of the present invention;
14 is a cross-sectional view taken along line 14-14 ′ in FIG.
15 is a schematic circuit diagram showing a main configuration of the TC parallel unit serial connection type ferroelectric memory shown in FIG. 13;
FIG. 16 is a schematic circuit diagram showing a main configuration of a TC parallel unit serial connection type ferroelectric memory according to a seventh embodiment of the present invention;
FIG. 17 is a diagram showing the main part of another example of a ferroelectric memory.
[Explanation of symbols]
MCB, MCB0, MCB1 ... memory cell block, MC, MC '... memory cell, C ... ferroelectric capacitor, T ... cell transistor, BSL0, BSL1 ... block selection signal line, BST0, BST1 ... block selection transistor, WL ... word Line, BL, / BL ... Bit line, PL, / PL ... Plate line, RVG, RVG1, RVG2 ... Reference voltage generation circuit, RC, RCn ... Reference capacitor, DWL1, DWL2 ... Dummy word line, DWT1, DWT2, DWTn ... Dummy word transistor, DPL ... dummy plate line, SA ... sense amplifier circuit, Cbb ... parasitic capacitance, MCA, MCA1, MCA2 ... memory cell array, CD ... column decoder, DummyBL, Dummy / BL ... dummy bit line, DQ ... data line, DST0, DST1 ... data selection transistor, CSL ... column selection signal line, AST1, AST2 ... cell array selection transistor, OR ... OR circuit, C1 ... capacitor, 1, 3, 5 ... plug, WL1 (GC) ... gate wiring, 2 ... first Layer metal wiring, 4... Second layer metal wiring, WL1 (M3)... Third layer metal wiring, Stitch Area.

Claims (14)

Each electrode of the ferroelectric capacitor is electrically connected to the source and drain regions of the cell transistor to form a memory cell, and a plurality of the memory cells are connected in series between the first terminal and the second terminal. The first terminal is electrically connected to a bit line via a block selection transistor, and the second terminal is electrically connected to a plate line to constitute a memory cell block; A memory cell array in which the memory cell blocks are arranged in a matrix;
Outside the bit line arranged at the end of the memory cell array, the bit line is arranged at the same interval as the pitch between the bit lines in the memory cell array, and the wiring width is equal to that of the bit line. A first dummy bit line having
A ferroelectric memory comprising: a first dummy memory cell block electrically connected to the first dummy bit line and having the same structure as the memory cell block . 2. The ferroelectric memory according to claim 1, further comprising a second dummy bit line that is arranged on the outer side of the first dummy bit line and is fixed to a predetermined potential . 3. A second dummy bit line arranged on the outer side of the first dummy bit line and spaced apart from the first dummy bit line and having a wiring width equivalent to the bit line;
A second dummy memory cell block electrically connected to the second dummy bit line and having the same structure as the memory cell block to which complementary data is transferred to the first dummy memory cell block; The ferroelectric memory according to claim 1, further comprising: A sense amplifier circuit electrically connected to the first dummy bit line and the second dummy bit line and detecting a signal from the first dummy bit line and the second dummy bit line; 4. The ferroelectric memory according to claim 3, further comprising: 5. The ferroelectric according to claim 3, further comprising a third dummy bit line which is arranged further outside the second dummy bit line and is fixed to a predetermined potential . 6. memory. Each electrode of the ferroelectric capacitor is electrically connected to the source and drain regions of the cell transistor to form a memory cell, and a plurality of the memory cells are connected in series between the first terminal and the second terminal. The first terminal is electrically connected to a bit line via a block selection transistor, and the second terminal is electrically connected to a plate line to constitute a memory cell block; A first memory cell array in which the memory cell blocks are arranged in a matrix;
A second memory cell array disposed adjacent to the first memory cell array so as to share a bit line connected to the first memory cell array and having the same structure as the first memory cell array;
Outside the bit lines arranged at the end of the first memory cell array, the bit lines are arranged at the same interval as the pitch between the bit lines in the first memory cell array from the bit lines. A first dummy bit line having a wiring width equivalent to
A first dummy memory cell block electrically connected to the first dummy bit line and having the same structure as the memory cell block;
Outside the bit lines arranged at the end of the second memory cell array, the bit lines are arranged at the same interval as the pitch between the bit lines in the second memory cell array from the bit lines. A second dummy bit line having an equivalent wiring width;
A second dummy memory cell block electrically connected to the second dummy bit line and having the same structure as the memory cell block;
A ferroelectric memory comprising: A sense amplifier circuit electrically connected to the first dummy bit line and the second dummy bit line and detecting a signal from the first dummy bit line and the second dummy bit line; 7. The ferroelectric memory according to claim 6, further comprising: A sense amplifier circuit electrically connected to the first dummy bit line and the second dummy bit line and detecting a signal from the first dummy bit line and the second dummy bit line; Equipped,
In the dummy bit line pair consisting of the first dummy bit line and the second dummy bit line, the first dummy memory cell block is connected to a word line of the first memory cell array, 7. The ferroelectric memory according to claim 6, wherein a dummy memory cell block is of an open bit line system in which the dummy memory cell block is connected to a word line of the second memory cell array . 7. The apparatus according to claim 6, further comprising a third dummy bit line disposed further outside the first dummy bit line and the second dummy bit line and fixed at a predetermined potential. The ferroelectric memory according to any one of Items 8 to 8 . Each electrode of the ferroelectric capacitor is electrically connected to the source and drain regions of the cell transistor to form a memory cell, and a plurality of the memory cells are connected in series between the first terminal and the second terminal. The first terminal is electrically connected to a bit line via a block selection transistor, and the second terminal is electrically connected to a plate line to constitute a memory cell block; A memory cell array in which the memory cell blocks are arranged in a matrix;
An auxiliary word line disposed on the memory cell array in parallel with the word line;
A stitch unit disposed inside the memory cell array and electrically connecting the word line and the auxiliary word line;
Between the stitch part and one of the two bit lines sandwiching the stitch part, the pitch part is arranged at the same interval as the pitch between the bit lines in the memory cell array from one of the two bit lines, and A first dummy bit line having a wiring width equivalent to the bit line;
A first dummy memory cell block electrically connected to the first dummy bit line and having the same structure as the memory cell block;
Between the stitch part and the other of the two bit lines sandwiching the stitch part, the second bit line is spaced from the other bit line and has a wiring width equivalent to that of the bit line. Two dummy bit lines;
A second dummy memory cell block electrically connected to the second dummy bit line and having the same structure as the memory cell block;
A ferroelectric memory comprising: A sense amplifier circuit electrically connected to the first dummy bit line and the second dummy bit line and detecting a signal from the first dummy bit line and the second dummy bit line; Equipped,
11. The ferroelectric memory according to claim 10, wherein data complementary to the first dummy memory cell block is transferred to the second dummy memory cell block . A third dummy bit line disposed between the stitch portion and the first dummy bit line at a distance from the first dummy bit line and having a wiring width equivalent to the bit line; ,
A third dummy memory cell block electrically connected to the third dummy bit line and having the same structure as the memory cell block;
A fourth dummy bit line disposed between the stitch portion and the second dummy bit line at a distance from the second dummy bit line and having a wiring width equivalent to the bit line; ,
11. The ferroelectric according to claim 10, further comprising a fourth dummy memory cell block electrically connected to the fourth dummy bit line and having the same structure as the memory cell block. memory. A first sense amplifier that is electrically connected to the first dummy bit line and the third dummy bit line and detects a signal from the first dummy bit line and the third dummy bit line Circuit,
A second sense amplifier that is electrically connected to the second dummy bit line and the fourth dummy bit line and detects a signal from the second dummy bit line and the fourth dummy bit line A circuit,
In the third dummy memory cell block, data complementary to the first dummy memory cell block is transferred,
13. The ferroelectric memory according to claim 12, wherein data complementary to the second dummy memory cell block is transferred to the fourth dummy memory cell block . Each electrode of the ferroelectric capacitor is electrically connected to the source and drain regions of the cell transistor to form a memory cell, and a plurality of the memory cells are connected in series between the first terminal and the second terminal. The first terminal is electrically connected to a bit line via a block selection transistor, and the second terminal is electrically connected to a plate line to constitute a memory cell block; A memory cell array in which the memory cell blocks are arranged in a matrix;
A dummy bit line disposed outside a bit line disposed at an end of the memory cell array;
A capacitor having one electrode electrically connected to the dummy bit line;
A dummy bit line driving circuit having an output side electrically connected to the other electrode of the capacitor, an input side electrically connected to the plate line, and detecting driving of the plate line;
A ferroelectric memory comprising:

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