JP4001221B2 - Inertial speed sensor and method with improved clock means - Google Patents

Description

[0001]
(Technical field to which the invention belongs)
The present invention relates generally to inertial speed sensors, and more precisely to an inertial speed sensor and method with improved clock means.
[0002]
(Background of the Invention)
Inertial speed sensors are used in a wide variety of applications including aircraft navigation, missile and spacecraft guidance, and automotive stability control systems. In many of these applications, safety is of paramount importance, and measures must be taken to guard against sensor failure.
[0003]
(Summary of Invention)
It is generally an object of the present invention to provide a new and improved inertial velocity sensor and method.
[0004]
Another object of the present invention is to provide an inertial velocity sensor and method with improved clock means.
[0005]
For these and other purposes, a drive signal is sent to the speed sensing element, a pickup circuit is coupled to the speed sensing element to provide an output signal corresponding to the motion of the vibration speed sensing element, and digital logic calibrates the speed sensor. The speed sensing element is used as a frequency reference for providing a system clock signal to the digital logic, and there is a fixed phase relationship between the vibration of the speed sensing element and the system clock signal. Inertia speed sensor where the system clock signal is filtered and digital logic is reset synchronously with the system clock signal for a period of time after the operating power is applied to the sensor to eliminate the response to the pseudo-transition And according to the present invention to provide a method.
[0006]
Detailed Description of Preferred Embodiments
As shown in FIG. 1, the speed sensor includes a quartz sensing element 11 in the form of a double-ended tuning fork. The tuning fork is made of a single crystal material, and has an H-shaped configuration, one of which is a drive tink 12 and the other is a pickup tink 13. Each pair of tines is arranged symmetrically around the longitudinal axis 14 of the tuning fork.
[0007]
When driven, the drive tines 12 vibrate in the plane of the tuning fork at the natural frequency of the tuning fork. When the tuning fork is rotated around the vertical axis, Coriolis force is applied to cause the two tines to come off the surface of the tuning fork and induce a pickup mode of vibration. The drive and pickup signals are connected to the tines using electrodes (not shown) in a conventional manner, the drive signals induce piezoelectric vibrations of the tines, and the pick-up signals are subjected to distortion caused by Coriolis forces. It takes the form of electric charges generated in response to piezoelectricity.
[0008]
Although the sensing element is illustrated as being a double-ended tuning fork, other types of vibration sensing elements may be used, including a single-ended tuning fork, if desired.
[0009]
The pickup signal passes through the charge amplifier 16 to the preamplifier 17 and then to the demodulator 18. The signal leaving the demodulator passes through the low-pass filter 19 to the compensation adder 21 and then to the output amplifier 22 and the speed output signal appears at the output of the output amplifier. When the voltage input is +5 volts and 0 volts, the speed output is biased to +2.5 volts for zero input and swings to a larger positive voltage for positive speed input, but for negative speed input Swings towards zero volts. A level of +2.5 volts is often referred to as substantial ground.
[0010]
As described in US Pat. No. 5,942,686, the compensation signal is applied to an adder so that the scale factor of the device changes in direct proportion to the applied power, and the output signal for factors such as temperature is Adjust to make the system ratiometric.
[0011]
The system includes digital logic 23 that operates in conjunction with an external EEPROM 24 so that the device can be calibrated electronically without having to manually solder the components. Digital logic also provides a built-in test function that detects when a device has failed. The signal from the digital logic is sent to the compensation adder 21 through the digital / analog converter 26 and to the output amplifier 22.
[0012]
The vibration sensing element, i.e., tuning fork 11, is used as a clock reference for digital logic so that a clock signal derived from a drive circuit or oscillator 28 is sent to digital logic via a clock filter 29. This eliminates the need for an external clock, thereby reducing the size and cost of the speed sensor, thereby reducing the total number of parts and circuit board area. In this way, monitoring the tuning fork integrity automatically monitors the integrity of the clock signal, thus simplifying the task of fault detection. In addition, since the clock signal is synchronized with the output signal, alias signals and beat tones at the total and difference frequencies are not generated.
[0013]
In the preferred embodiment, the fundamental frequency of the tuning fork is used as the clock reference for digital logic. Alternatively, a phase-locked loop can be used to generate multiple tuning fork drive frequencies for faster signal processing. In any case, the frequency determining element is the same tuning fork that acts as the sensing element.
[0014]
As shown in FIG. 2, the drive circuit or oscillator 28 includes a loop sometimes referred to as an AGC (automatic gain control) servo loop. When the drive tines are oscillating, current is generated across the drive electrodes. This current passes through the current-to-voltage amplifier 31 and produces a voltage that is applied to the input of the demodulator 32. A voltage comparator 33 connected to the output of the current-to-voltage amplifier generates a square wave at the drive frequency. This square wave is sent to the control input of the demodulator, and the demodulator is activated at the drive frequency, and its output includes the term dc.
[0015]
The dc term from the demodulator is sent to summing circuit 34 where it is combined with fixed scale factor reference voltage 36 and programmable scale factor reference voltage 37. The output of the adder circuit is connected to the input of the integrator 38.
[0016]
The integrator output will move towards either a larger positive voltage or a larger negative voltage if the input is non-zero. This means that in steady state, the input to the integrator is on average zero. Thus, the demodulator output must accurately cancel the sum of the two scale factor reference voltages. Since the output voltage of the demodulator represents the amplitude of the tuning fork drive mode vibration, the two scale factor reference voltages set the magnitude of the drive mode signal.
[0017]
The tuning fork's ability to sense speed depends on the Coriolis force that couples the input rotation about the axis of symmetry of the drive tines to an out-of-plane torsion mode. The Coriolis force is proportional to the product of the rotational speed and the tine speed, which is proportional to the amplitude of the tine vibration. Thus, as the tines are driven and vibrate with greater displacement amplitude and speed, the response to rotation via Coriolis forces increases proportionally.
[0018]
Thus, the scale factor or the response per unit rotation of the tuning fork increases in proportion to the drive amplitude.
[0019]
In determining the amplitude of the tuning fork drive mode vibration, the scale factor reference voltages 36 and 37 also determine the scale factor of the device. Set the reference scale factor using a fixed voltage and fine tune using a programmable voltage. As a result, the scale factor of each device can be corrected according to the fine differences in individual tuning fork characteristics so that each completed speed sensor has an appropriate scale factor output.
[0020]
Programmable data for setting the programmable scale factor reference voltage is derived from digital coefficients stored in the EEPROM 24 and accessed by the digital logic 23. The data is converted to an analog voltage and sent to the programmable bias voltage input of summing circuit 34. In a presently preferred embodiment, the scale factor based programmable component adjustment range is on the order of +/− 35 percent of the fixed component.
[0021]
The voltage level of the integrator output is monitored by a window comparator 39 that detects unacceptable conditions or faults in the drive loop. The window comparator includes a pair of comparators 41 and 42 and a negative sum gate 43, and the output of the comparator is connected to the input of the negative sum gate. The upper and lower voltage limits are set by reference voltages + REF and -REF defining circuit trip points. The other two comparator inputs are combined together to receive the signal from the integrator. The output of the negative sum gate passes through the low pass filter 44 and is monitored by the built-in test logic.
[0022]
As long as the integrator output is within the limits set by the reference voltage, the window comparator output is determined to be acceptable to the built-in test logic 46. If the integrator output falls outside the above limits, the test logic detects a fault and triggers the output stage 22 to quickly switch to the positive voltage rail, which is interpreted as a fault condition.
[0023]
The types of faults that can be detected in the oscillator loop are caused by a defective or broken tuning fork, an open electrical trace leading to or coming out of the tuning fork, and a leak of filling gas in the package in which the tuning fork is enclosed. Changes in tuning fork mode “Q” factor, and feedback components across the integrator are shorted or open.
[0024]
In order for the integrator failure to be detected by the built-in test logic, the integrator output is combined with the bias voltage 48 of the summing circuit 49 to bring the integrator steady state output to a substantial ground, ie, a positive supply voltage. Move from the midpoint between the negative supply voltages to the required value. This is necessary because if the feedback path across the integrator is shorted, the integrator output will remain at essentially ground, ie +2.5 volts if the system is supplied with +5 and 0 volts. It is. In order to detect this failure, the acceptable range of integrator output voltage must be biased away from substantial ground, typically in the range of about +2.6 volts to +4 volts, for standard operating conditions.
[0025]
When the feedback path across the integrator becomes open, the integrator amplifier will pass all the double frequency components created by the demodulator. When this double frequency signal passes through the window comparator, the amplifier output transitions past the trip limit, resulting in a digital “1” and “0” stream. The low-pass filter 44 lowers this pulse stream to the dc voltage, and the built-in test logic detects this dc voltage as a failure.
[0026]
The output of the adder circuit 49 is amplified by the amplifier 51 and sent to the amplitude modulator 52 to modulate the output voltage from the voltage comparator 33. The output of the voltage comparator is a rail-to-rail square wave and the modulator adjusts the peak-to-peak amplitude of the square wave to provide a variable drive voltage to the drive fork of the tuning fork.
[0027]
The square wave from the modulator is sent to the drive tines via a multiplexer 53 controlled by signals from the logic circuit. The square wave is also sent to the input of the bandpass filter 54 with a gain of 1.0 at a center frequency approximately equal to the natural frequency of the tuning fork drive mode. This filter significantly attenuates the harmonic component of the square wave, creating another drive signal that is close to a pure sine wave. The signal is sent to the second input of the multiplexer.
[0028]
Since the peak-to-peak voltage of the square wave drive signal rises more quickly and consequently turns on faster than the sine wave, it is sent to the drive tines during the initial phase of turn-on to minimize turn-on time. Once the tuning fork vibration amplitude reaches a certain level and the output of the integrator 38 exceeds the lower control limit of the window comparator 39, the built-in test logic switches its output from a square wave to a sine wave to the multiplexer. Generate a command signal. A relatively harmonic-free sine wave is used here to drive the tuning fork for the remainder of the operation until the next turn-on sequence.
[0029]
This provides the advantages of both types of drive signals without suffering from either type of drawback. A square wave provides tuning fork vibration at the amplitude control level and a faster rise in stability. However, square waves also have harmonic components that, in some cases, can be combined with higher order modes of the tuning fork structure and cause undesirable bias shifts in the sensor output. A sine wave has relatively few such harmonics and rises more slowly, which results in slower turn-on than a square wave and is not very good for start-up operation.
[0030]
It is important that the clock reference is generated in such a way that it has a fixed phase relationship to the phase of the tuning fork motion. If the phase relationship changes from one turn-on to the next, the logic will still function properly, but if there is a phase difference, the finite coupling of the clock signal to the output signal path Because of this, the sensor bias offset tends to vary. With a fixed clock phase relationship, even if there is a coupling, it will certainly have a fixed value from turn-on to turn-on.
[0031]
The fixed phase relationship is provided by the clock filter 29 that passes when the clock signal is sent to the logic circuit. As shown in FIG. 3, the clock filter has a pair of D-type flip-flops 56, 57 that are simultaneously reset to erase their outputs, indicated as QA and QB, respectively. The When these flip-flops trigger on a positive clock edge, the input clock signal is derived from the output of voltage comparator 33, the non-inverted clock input signal is sent to flip-flop 56, and the inverted clock input signal is inverter 58. To the flip-flop 57.
[0032]
A feedback loop including an integrator 59, a Schmitt trigger 60, and an inverter 61 is connected between the Q output and the D input of the flip-flop 57. As a result, the clock input is divided by 2, so that the signal QB output from the flip-flop 57 is a square wave with a frequency equal to exactly half the clock input.
[0033]
The flip-flop 56 is a slave of the flip-flop 57, and the delayed QB output signal from the flip-flop 57 is sent to the D input of the flip-flop 56 via the inverter 62. Thus, the signal QA at the output of the flip-flop 56 is also a square wave with a frequency equal to exactly half of the clock input, so that the outputs of the two flip-flops are always out of phase with each other by half the input clock period. Become.
[0034]
Integrators and Schmitt triggers introduce a delay in the feedback that prevents such transitions from occurring in the clock output signal when multiple transitions are present in the input clock signal. The delay prevents the flip-flop from making further transitions during a certain period after the first transition at the first positive clock edge. This delay is shown in FIG. 4 and is about 10 to 25 percent of the clock period. By suppressing the flip-flops in this way, the output signal from the clock input, which may contain many transitions within a short period after the first transition, is clean. Such transitions arise, for example, from elements such as comparators used to generate clock inputs, but they can occur at any time during sensor operation, not just at startup.
[0035]
There are no pseudo transitions in the outputs QA and QB of the flip-flops 56 and 57, and these outputs are input to the exclusive OR gate 63. Since these two signals are both half the frequency of the clock input signal, they combine to produce a new clock signal with the same frequency as the clock input signal. Since the two flip-flops are slaved to each other and their QA and QB outputs are always out of phase with each other by half the input clock period, the phase of the output signal from the filter is always the clock signal input to the filter. Have a fixed relationship to This phase relationship is shown in FIG.
[0036]
FIG. 5 shows a reset circuit 64 that prevents an incorrect clock signal from being derived from spurious vibrations that occur between the moment power is applied to the sensor and the rise of sufficient tuning fork drive vibration. The circuit includes a precision oscillator 66 with a voltage comparator 67 with a resistor 68 and a capacitor 69 that determines the frequency of the oscillator. This frequency is much lower than the system clock frequency, and in one currently preferred embodiment, the system clock operates at a frequency of 10 KHz and the oscillator 66 operates at a frequency of 1 Khz.
[0037]
As shown in FIG. 6, a certain finite period is required for the drive oscillator signal 71 to transition from a certain indeterminate frequency to a standard operating frequency. Waveform 72 illustrates how the input voltage gradually increases as power is applied. When the input voltage reaches a threshold level, typically 3.8 volts, a power-on reset pulse 73 is generated to reset the logic circuit to its initial state.
[0038]
The output of the oscillator 66 is connected to the input of a 9-bit (512 division) counter 74. The output of the counter is sent to control logic 77, which also receives an asynchronous reset signal from power-on reset circuit 78. Upon receipt of a signal from counter 74, control logic toggles comparator enable signal 79 to shut off voltage comparator 67, which now stops oscillating until another power-on reset occurs. The control logic also enables a reset pulse synchronizer 81, which delivers a synchronous reset signal that is synchronized with the clock signal from the clock filter 29 that is known to be valid. The synchronous reset signal is combined with the asynchronous reset signal at the OR gate 82 to provide the system reset signal 83. As shown in FIG. 6, this signal transitions to a low state and returns to the next high state when synchronized with the main system clock. This delayed delivery of the reset signal ensures that a final reset can be applied to the all digital logic circuit after a clock known to be valid is derived from the tuning fork.
The control logic performs its function within two periods of the signal from the oscillator 66, producing a total of 514 periods for the operation of the oscillator, at which point it is completely disabled. This typically requires about 0.5 seconds.
[0039]
The lower two waveforms show the system clock and system reset signal on an enlarged scale. As shown by these two waveforms, the negative transition of the system reset signal is asynchronous to the system clock and can produce several clock periods before the positive transition, Synchronized with the system clock.
[0040]
This reset circuit initializes the digital logic when power is applied to the sensor. Until the timing sequence is complete, the built-in test logic holds the signal from the output stage 22 at the positive rail voltage. Thereafter, the output can assume a value corresponding to the rotational speed of the sensor. When the output goes off the rail, it is an indication that the sensor is ready for use and gives valid data. The output is now returned to the positive rail only when a fault is detected.
[0041]
When a fault is detected and the output goes to the positive voltage rail, the BIT flag is latched and remains latched until another power turn-on sequence occurs. However, latching of the BIT flag is prohibited until the turn-on sequence is completed so that the BIT flag is not latched due to the transition state during activation.
[0042]
If the power applied to the device falls below the power-on reset circuit threshold, the circuit is automatically triggered again. In the case of retrigger, it is indicated that a loss of power has occurred.
[0043]
In a preferred embodiment, the circuit for the sensor is built in one piece as an application specific integrated circuit (ASIC). The tuning fork and EEPROM are external to the ASIC, and the compensation values can be loaded into the EEPROM via the ASIC digital logic via the computer interface. In one presently preferred embodiment, the ASIC has only three connector terminals: +5 volts, ground (0 volts), and output signal terminals.
[0044]
The present invention has many important attributes and advantages. By using the sensing element itself as the system clock reference, the need for a separate clock is eliminated, thereby reducing the size and cost of the unit. The clock filter prevents an inaccurate clock signal from being applied in response to the pseudo oscillation at start-up. The clock filter also ensures that the same phase relationship always exists between the system clock and the tuning fork oscillation. The power on reset circuit provides a reset signal that is accurately synchronized with the system clock.
[0045]
From the foregoing, it is apparent that a new and improved inertial velocity sensor and method have been provided. While only certain preferred embodiments of the present invention have been described in detail, changes and modifications may be made without departing from the scope of the invention as defined in the claims, as will be apparent to those skilled in the art. it can.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating one embodiment of an inertial velocity sensor incorporating the present invention.
FIG. 2 is a block diagram of a drive oscillator in the embodiment of FIG.
FIG. 3 is a block diagram of a clock filter in the embodiment of FIG.
4 is a timing diagram showing waveforms at different positions of the clock filter of FIG. 3; FIG.
5 is a block diagram of the reset circuit of the embodiment of FIG.
6 is a timing diagram showing waveforms at different positions of the reset circuit of FIG. 5. FIG.

Claims (19)

In an inertial speed sensor, a vibration speed sensing element, a drive circuit for sending a drive signal to the speed sensing element, and coupled to the speed sensing element to provide an output signal corresponding to the movement of the speed sensing element. A pickup circuit for driving, a digital logic circuit driven by a system clock signal for calibrating the speed sensor and detecting the occurrence of a fault in the speed sensor, and using the speed sensing element as a frequency reference, Means for providing said system clock signal to a circuit . Means for maintaining a fixed phase relationship between the oscillation of the speed sensing element and the system clock signal, and the system to eliminate a response to a pseudo-transition during the subsequent period after actuation power is applied to the sensor. inertial velocity sensor according to claim 1, characterized in that it comprises means for filtering the clock signal, and means for resetting the digital logic in synchronization with the system clock signal.   The inertial speed sensor of claim 1, further comprising means for maintaining a fixed phase relationship between the vibration of the speed sensing element and the system clock signal.   The means for maintaining the fixed phase relationship includes means for providing an input clock signal that is in phase with the vibration of the speed sensing element, and in response to the input clock signal, the frequency is half of the input clock signal. Means for generating a first signal whose rising edge is equally synchronized with either the rising edge or falling edge of the input clock signal, the frequency being equal to half the frequency of the input clock signal but the first signal being input Means for generating a second signal that is out of phase by half of the clock signal; and means for combining the first and second signals to provide the system clock signal. The inertial velocity sensor according to claim 2 or 3, wherein   5. The inertial velocity sensor according to claim 1, further comprising means for inhibiting the sending of a clock signal during a period after the operating power is applied to the sensor.   Responsive to the initial transition of the clock signal, further comprising means for inhibiting further transitions of the clock signal during a period of about 10 to 25 percent of the period of the clock signal. The inertial velocity sensor according to any one of claims 1 to 5.   The system of claim 1, further comprising means for filtering the system clock signal to eliminate response to spurious transitions during a period of time after actuation power is applied to the sensor. The inertial velocity sensor according to 4, or 6. 8. The inertial velocity sensor according to claim 1, 3, 4, 5, 6, or 7, further comprising means for resetting the digital logic circuit in synchronization with the system clock signal. The means for resetting the digital logic circuit includes an oscillator that operates for a predetermined number of periods after receiving a power-on reset signal, and means for generating a reset signal in response to a signal from the oscillator; 9. The method of claim 1, further comprising: means for synchronizing the reset signal with the system clock signal; and means for sending the synchronized reset signal to the digital logic circuit . Inertia speed sensor as described in A method of sensing inertial speed with a speed sensor, comprising: a vibration speed sensing element; and a digital logic circuit driven by a system clock to calibrate the speed sensor and detect speed sensor failure. Sending to the speed sensing element; monitoring a signal from the speed sensing element to provide an output signal corresponding to the movement of the speed sensing element; and utilizing the speed sensing element as a frequency reference; Providing a clock signal to the digital logic circuit . Maintaining a fixed phase relationship between the vibration of the speed sensing element and the system clock signal, and the system clock signal to eliminate a response to a pseudo-transition during a period subsequent to actuation power being applied to the sensor. 11. The method of claim 10, further comprising: filtering and resetting the digital logic circuit in synchronization with the system clock signal.   The method of claim 10, further comprising maintaining a fixed phase relationship between the vibration of the speed sensing element and the system clock signal.   The fixed phase relationship provides an input clock signal that is in phase with the vibration of the speed sensing element, the frequency is equal to half the frequency of the input clock signal, and the rising edge is the rising edge of the input clock signal or Generating a first signal that is synchronized with any of the falling edges, and a second that is equal in frequency to half the frequency of the input clock signal but out of phase with the first signal by half the input clock period. 13. A method according to claim 11 or 12, wherein the method is maintained by generating a signal and combining the first and second signals to provide the system clock signal.   14. A method according to any one of claims 10 to 13, further comprising the step of prohibiting the sending of a clock signal during a period after operating power is applied to the sensor.   15. A method as claimed in any of claims 10 to 14, further comprising the step of inhibiting transitions following the first transition during a period of about 10 to 25 percent of the clock period.   Providing an input clock signal that is in phase with the oscillation of the speed sensing element, the frequency is equal to half the frequency of the input clock signal, and the rising edge is synchronized with either the rising edge or the falling edge of the input clock signal; Generating a first signal having a frequency equal to half the frequency of the input clock signal but generating a second signal that is out of phase with the first signal by half the input clock period, the system 16. A method according to any of claims 10 to 15, further comprising the step of combining the first and second signals to provide a clock signal.   16. The method of claim 10, further comprising filtering the system clock signal to eliminate a response to a pseudo-transition during a period after operating power is applied to the sensor. Or the method in any one of 16. 18. A method according to any of claims 10 or 12 to 17, further comprising the step of resetting the digital logic circuit in synchronization with the system clock signal. The digital logic circuit operates an oscillator for a predetermined number of periods after receiving a power-on reset signal, generates a reset signal in response to a signal from the oscillator, and outputs the reset signal to the system The method of claim 18, wherein the method is reset by synchronizing with a clock signal and sending the synchronized signal to the digital logic circuit .

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