JP3998403B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a transistor having a nitride film in the vicinity of a gate insulating film, and more particularly to a semiconductor device that performs a high-temperature process after the nitride film is formed and a method for manufacturing the same.
[0002]
[Prior art]
In semiconductor devices that are becoming increasingly integrated year by year, circuit design rules have been reduced as a requirement for miniaturization. As the gate electrode of a MOS transistor for a logic device, phosphorus-doped polycrystalline silicon is generally used for an NMOS transistor and boron-doped polycrystalline silicon is used for a PMOS transistor. Around this gate electrode, a silicon nitride film Si ₃ N ₄ is provided above and on the side wall. An oxide film or an oxynitride film is used for the gate insulating film. The diffusion coefficient of boron in the silicon oxide film is larger than that of phosphorus. Due to the thinning of the gate oxide film due to the miniaturization of the element, boron diffuses in the gate oxide film after a high temperature process after adding boron to the gate electrode. Then, boron diffuses into the silicon semiconductor substrate. For example, in the case of a transistor having a gate width of about 0.13 μm, the gate oxide film is thinned to about 4 nm. Since the PMOS transistor is usually formed on the N-type well, the threshold value varies as boron diffuses into the semiconductor substrate.
[0003]
In addition, the dispersion of the threshold value increases because the diffusion method of boron varies from cell to cell. That is, as the miniaturization progresses and the gate width approaches the interval between the crystal grain boundaries constituting the gate electrode and becomes smaller, there is a variation that the crystal grain boundary exists or does not exist for each gate. For example, in the case where 10 million transistors are included in one semiconductor device, the variation affects the variation in threshold values of many transistors.
[0004]
The reason is that boron existing in the gate is easily segregated at the crystal grain boundary of the polycrystalline silicon layer, and the boron concentration is high at the crystal grain boundary part. If there is a nitride film on the gate or the side wall of the gate, hydrogen is desorbed from the nitride film and reaches the gate insulating film by a high-temperature thermal process, and defects are formed in the gate insulating film. Boron in the polycrystalline silicon gate electrode diffuses into the semiconductor substrate through this defect. At this time, as described above, high-concentration boron is precipitated at the crystal grain boundaries in the polycrystalline silicon layer, and boron diffusion into the semiconductor substrate is noticeable at the crystal grain boundaries. Therefore, the presence or absence of crystal grain boundaries causes variations in transistor thresholds.
[0005]
Here, when the semiconductor substrate is an N type, the boron concentration of the substrate is about 10 ¹⁷ cm ⁻³ , and the threshold value fluctuates even if a slight boron of about 10 ¹⁶ cm ⁻³ diffuses.
[0006]
Incidentally, FIG. 1 of Japanese Patent Application Laid-Open No. 10-22396 discloses a technique for performing a heat treatment at a bonding temperature of boron and hydrogen in order to prevent a boron penetration diffusion phenomenon due to the presence of a silicon nitride film. Japanese Patent Application Laid-Open No. 11-97558 discloses a technique for forming a tunnel oxide film by using SiH ₂ Cl ₂ at 800 to 900 ° C.
[0007]
[Problems to be solved by the invention]
The conventional method for manufacturing a semiconductor device as described above has the following problems.
[0008]
It has been found that the boron diffusion is accelerated when a silicon nitride film is present in the vicinity of the MOS transistor. In order to prevent such accelerated diffusion of boron, it has been attempted to add nitrogen to the silicon oxide film. However, the addition of a high concentration of nitrogen reduces the mobility and deteriorates the transistor characteristics. There's a problem.
[0009]
On the other hand, the diffusion layers formed in the source and drain need to be shallow as the element is miniaturized. In the NMOS transistor, the source and drain diffusion layers are formed of arsenic. In particular, in a fine transistor having a gate width of about 0.15 μm, when a silicon nitride film is present in the vicinity of the source and drain diffusion layers, it has been reported that it is difficult to form a shallow junction due to accelerated diffusion of arsenic. ing.
[0010]
In the flash memory, data is written, read, and erased by moving electrons through the tunnel oxide film. When electrons move through the tunnel oxide film, if the characteristics of writing, reading, and erasing change with each movement, it is not preferable as a semiconductor memory device. For example, when a silicon nitride film is present in the vicinity of the tunnel oxide film, hydrogen in the silicon nitride film is taken into the tunnel oxide film by a high temperature process, causing a defect in the oxide film, and the oxide film is thinned. This shortens the dielectric breakdown lifetime and increases the amount of electron traps generated when stress is applied. In particular, rapid thermal annealing (RTA) is heated at 1000 ° C. for 10 seconds, and furnace furnace is heated at 900 ° C. for about 30 minutes. Has been confirmed to form. As described above, when the characteristics of the tunnel oxide film, in particular, the electron trap density is increased, the number of rewrites is limited.
[0011]
An object of the present invention is to solve the above-described problems of the prior art.
[0012]
In particular, an object of the present invention is to provide a method for manufacturing a fine semiconductor device in which a nitride film with few Si—H bonds is formed, and the characteristics of the gate insulating film are maintained even after a subsequent high-temperature thermal process. is there.
[0013]
Still another object of the present invention is to provide a method of manufacturing a semiconductor device that prevents accelerated diffusion of boron from a polycrystalline silicon layer to a semiconductor substrate in a thermal process when manufacturing a PMOS transistor.
[0014]
Another object of the present invention is to provide a method of manufacturing a semiconductor device that prevents the accelerating diffusion of arsenic in a semiconductor substrate during a thermal process when manufacturing an NMOS transistor.
[0015]
Another object of the present invention is to prevent deterioration of a tunnel oxide film when manufacturing an EEPROM.
[0016]
[Means for Solving the Problems]
Forming a gate insulating film on the semiconductor substrate; forming a gate electrode through the gate insulating film; forming a silicon oxide film so as to cover the gate electrode; and on the silicon oxide film , A step of forming a silicon nitride film using Si ₂ Cl ₆ as a source gas at a temperature of 650 ° C. or lower, and a heat treatment at a temperature of 150 to 250 ° C. and 800 ° C. or lower from the silicon nitride film forming temperature. A manufacturing method of a semiconductor device in which a nitride film with few Si—H bonds is formed can be provided.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Accordingly, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, the part from which the relationship and ratio of a mutual dimension differ also in between drawings is contained.
(First embodiment)
As shown in FIG. 2A, a resist mask 2 is provided on a part of a P-type silicon substrate 1. Using this resist mask 2, ion implantation is performed in a P-type silicon substrate to form an N-type well 3. Thereafter, the resist is removed.
[0022]
Next, as shown in FIG. 2B, a thermal oxynitride film 4 to be a gate oxide film is formed to a thickness of 2.0 nm using NO gas. Thereafter, a polycrystalline silicon layer 5 to be a gate electrode is formed so as to have a film thickness of 200 nm. Thereafter, as shown in FIG. 3A, patterning is performed using a normal lithography process to process the polycrystalline silicon layer 5, thereby forming the gate electrode 6 of the PMOS transistor and the gate electrode 7 of the NMOS transistor. Thereafter, an oxide film 8 is formed to a thickness of 5 nm by a thermal oxidation method.
[0023]
Next, as shown in FIG. 3B, a resist mask 9 is provided on the P-type silicon substrate except for the PMOS transistor formation region, and boron is ionized by ion implantation using the gate electrode 6 of the PMOS transistor as a mask. P type diffusion layer 10 is formed by implantation.
[0024]
Next, after removing the resist mask 9 as shown in FIG. 4A, this time, a resist mask 11 is provided on an area other than the NMOS transistor formation region on the P-type silicon substrate, and the gate electrode 7 of the NMOS transistor is formed. As a mask, arsenic is ion-implanted by ion implantation to form the N-type diffusion layer 12.
[0025]
Next, as shown in FIG. 4B, a silicon nitride film Si ₃ N ₄ 13 having a film thickness of 20 nm is formed at a temperature of 700 ° C. using silicon tetrachloride SiCl ₄ and ammonia NH ₃ as source gases.
[0026]
Next, as shown in FIG. 5A, the silicon nitride film 13 is removed by RIE, leaving only the side walls of the gate electrodes of the PMOS transistor and NMOS transistor. Thereafter, a resist mask 14 is formed on the P-type silicon substrate 1 except for the region where the PMOS transistor is to be formed, and boron is ion-implanted using the gate electrode 6 of the PMOS transistor and the silicon nitride film 13 formed on the sidewall thereof as a mask. Then, a P-type diffusion layer 15 serving as a source and a drain is formed.
[0027]
Next, as shown in FIG. 5B, after removing the resist mask 14, a resist mask 16 is formed on the P-type silicon substrate 1 except for the region where the PMOS transistor is to be formed, and the gate electrode 7 of the NMOS transistor. Then, arsenic is ion-implanted using the silicon nitride film 13 formed on the side wall as a mask to form an N-type diffusion layer 17 serving as a source and a drain.
[0028]
Next, as shown in FIG. 1, after removing the resist mask 16, heat treatment is performed at 1050 ° C. for 30 seconds by a rapid heat treatment method to activate the ion-implanted impurities, and silicon nitride is formed around each gate. A PMOS transistor and an NMOS transistor provided with a film are obtained.
[0029]
By forming a silicon nitride film using SiCl ₄ as a source gas as in the present embodiment, penetration of boron into the silicon substrate in the gate electrode can be significantly suppressed. Further, the accelerated diffusion of the N-type diffusion layer 17 formed of arsenic can be prevented, and a shallow junction can be easily formed.
[0030]
In the formation of the thermal oxynitride film 4, at 850 ° C., NO is used as a source gas, and thermal oxide is used as SiO _x N _y having an intermediate property between the silicon oxide film SiO ₂ and the silicon nitride film Si ₃ N _4. The vaginalized membrane 4 is generated.
[0031]
Here, in order to improve the characteristics of the silicon oxide film, nitrogen is included to form a strong bond that is hardly affected even if hydrogen is mixed later. However, it is known that the addition of nitrogen to the gate oxide film increases the fixed charge in the gate oxide film and the interface state at the oxide film / Si interface, which degrades the transistor characteristics. In the case where a nitride film with little Si—H is used for the gate sidewall or the like as in the present embodiment, the oxynitride film may not be used for the gate insulating film. In that case, the characteristics of the transistor can be further improved.
[0032]
Here, FIG. 6A shows CV characteristics of a MOS capacitor using a polycrystalline silicon electrode in which boron is added to an N well on a P-type silicon substrate. The characteristics shown in FIG. 6A are measured in a MOS capacitor as shown in FIG. In the MOS capacitor shown in FIG. 7, a polycrystalline silicon layer 23 to which boron is added is formed in an N well 21 on a P-type semiconductor substrate 20 through a silicon oxide film 22. A silicon nitride film Si ₃ N ₄ 24 is formed on the polycrystalline silicon layer 23. Hydrogen in the silicon nitride film 24 penetrates the polycrystalline silicon layer 23 and enters the silicon oxide film 22, thereby forming a defect in the silicon oxide film 22. Through this defect, boron in the polycrystalline silicon layer 23, particularly boron segregated at the grain boundary, enters the N well 21.
[0033]
In FIG. 6B, the flat band voltage V _FB corresponds to the voltage value when the characteristic rises in FIG. 6A and corresponds to the threshold value of the transistor. Here, Cox indicates a capacity corresponding to the film thickness when the silicon oxide film is optically measured. Cg is a capacity according to the actual measurement value of the silicon oxide film. Therefore, it is preferable that the value of Cg / Cox is close to 1.
[0034]
Here, when a conventional SiH ₂ Cl ₂ indicated as DCS in FIG. 6A is reacted with ammonia NH ₃ as a silicon source gas to form a nitride film at 780 ° C., V _FB is greatly shifted. It can be seen that B is diffused in the silicon substrate. On the other hand, when the nitride film is formed at 700 ° C. by reacting SiCl ₄ shown by TCS in FIG. 6A with ammonia NH ₃ as a silicon source gas as shown in FIG. You can see that nothing has happened.
[0035]
Here, when the distribution of DCS and TCS is compared in FIG. 6A, the value of Cg / Cox is clearly larger in TCS while the value of Vg is smaller than that in DCS, and TCS is preferable in terms of characteristics. Results are shown. Further, as shown in FIG. 6B, according to the characteristic diagram showing the relationship between the hydrogen concentration and V _FB , it can be seen that the shift amount of V _FB increases as the Si—H concentration in the nitride film increases. . That is, when SiCl ₄ and NH ₃ are reacted, V _{FB of} about 0.18 V is observed at 700 ° C. and about 0.15 V is observed at 780 ° C. Further, when SiH ₂ Cl ₂ and NH ₃ are reacted, V _{FB of} about 0.35 V is observed at 700 ° C. and about 0.23 V is observed at 780 ° C. When Si ₂ Cl ₆ (indicated by HCD in the figure) is reacted with NH ₃ , V _{FB of} about 0.7 V is observed at 650 ° C.
[0036]
The variation in threshold value is suppressed to + −0.01 V or less with respect to 0.175 V that is a contact point with the vertical axis of the measurement value line when the SiH concentration is 0 in FIG. 6B. It is preferable in terms of characteristics. Therefore, since the position where the straight line of the measured value is added to +0.01 V with respect to 0.175 V is 1 × 10 ²⁰ cm ⁻³ on the horizontal axis, the film forming temperature in that case should be about 850 ° C. or more. Has been confirmed.
[0037]
Further, as a result of evaluating the variation of the threshold voltage with the transistor, the variation in the threshold is smaller in the present embodiment than in the conventional example. This is presumably because the threshold value fluctuates because the manner of penetration of B differs depending on the transistor. Further, when formed by the conventional method, the diffusion depth of the N-type diffusion layer 12 is 25 nm, but in the present invention, the depth can be about 20 nm. This is also because the accelerated diffusion of arsenic by hydrogen in the nitride film was suppressed.
[0038]
The mechanism of the enhanced diffusion is considered that hydrogen in the nitride film is desorbed by a high-temperature process after the nitride film is formed, and the hydrogen causes the above-described deterioration. Hydrogen in the nitride film is incorporated in the form of Si-H or NH, but the behavior of hydrogen is greatly different between Si-H and NH, with respect to the above-mentioned enhanced diffusion and tunnel oxide film degradation. In particular, it became clear that H bonded to Si plays a dominant role.
[0039]
Therefore, it is important to form a nitride film having no or few Si—H bonds. Therefore, when SiH ₂ Cl ₂ is used as a source gas, a nitride film with few Si—H bonds can be formed by performing film formation at a high temperature. Further, a nitride film having no Si—H bond can be formed by using silicon tetrachloride as a source gas. Further, by using Si ₂ Cl ₆ as a source gas and forming a nitride film at a low temperature of 700 ° C. or lower, annealing is performed at a temperature higher than the film forming temperature and at a temperature of 850 ° C. or lower, thereby forming hydrogen in the nitride film. Can be removed once and a nitride film with few Si—H bonds can be formed, and the influence of Si—H bonds can be suppressed.
[0040]
In addition, the film-forming temperature of the silicon nitride film and the temperature of the high-temperature heating after the film-forming are measured using, for example, a thermocouple provided in the film-forming apparatus and the heating apparatus, respectively, and based on the measured temperature. Temperature control is performed. The Si—H bond concentration can be measured using, for example, an infrared absorbance spectrum by the FT-IR method (Fourier transform infrared spectroscopy).
(Second Embodiment)
A second embodiment in which the present invention is applied to an EEPROM will be described. FIG. 8 is a diagram showing an upper plane of the EEPROM. 9A to 13A are shown as drawings in the control electrode direction, which is a cross-sectional view in the direction of AA ′ in FIG. 9B to 13B are cross-sectional views in the direction perpendicular to the control electrode direction, which is a cross-sectional view taken along the line BB ′ in FIG. .
[0041]
As shown in FIGS. 9A and 9B, a silicon oxide film 32 to be a tunnel oxide film is formed on the silicon substrate 31 with a film thickness of 8 nm. Thereafter, a polycrystalline silicon film 33 to be a floating gate electrode is formed on the silicon oxide film 32 with a film thickness of 200 nm by a normal CVD method. Thereafter, a silicon nitride film 34 serving as a processing mask is formed with a film thickness of 200 nm. At this time, the silicon nitride film 34 is formed at 850 ° C. using SiH ₂ Cl ₂ and NH ₃ as source gases. Thereafter, a groove 35 for element isolation is formed using a normal lithography process using a resist, and the resist is removed. In addition, the groove | channel 35 is not shown in the direction shown by FIG.9 (b).
[0042]
Next, as shown in FIGS. 10A and 10B, an oxide film 36 having a film thickness of 6 nm is formed by, for example, a rapid thermal oxidation method at 1050 ° C. for 10 to 20 seconds, and then the groove 35 is formed to have a film thickness of 500 nm. The silicon oxide film 37 is embedded. Thereafter, the upper portion of the silicon oxide film 37 is removed using a chemical mechanical planarization method, and then the silicon nitride film 34 is removed with hot phosphoric acid. In FIG. 10B, only the process of removing the silicon nitride film 34 is shown.
[0043]
Next, as shown in FIGS. 11A and 11B, a polycrystalline silicon film 38 to be a second floating gate electrode is formed with a film thickness of 100 nm by the CVD method, and then floating by a normal lithography process. Process into gate electrode.
[0044]
Next, as shown in FIGS. 12A and 12B, an ONO film 39 is formed as an interelectrode insulating film by the CVD method so that the film thickness becomes an oxide film 6 nm, a nitride film 8 nm, and an oxide film 6 nm, respectively. Formed continuously. Here, the ONO film 39 has a shape in which the upper surface is recessed in accordance with the shape of the recess on the silicon oxide film 37 that is embedded in the trench 35 and is used for element isolation. Further, a polycrystalline silicon film 40 serving as a control electrode is deposited to a thickness of 300 nm. The lower surface of the polycrystalline silicon film 40 has a convex shape depending on the shape of the depression on the silicon oxide film 37 for element isolation, and covers the depression on the upper surface of the ONO film 39. A silicon nitride film 41 is formed on the polycrystalline silicon film 40 by a CVD method using SiCl ₄ and NH ₃ as source gases, for example, at a temperature of 700 ° C. to a thickness of 200 nm, and then using a normal lithography process. The control electrode 40, the second control electrode 38, and the first control electrode 33 are patterned and separated by the groove 42.
[0045]
Finally, as shown in FIGS. 13A and 13B, an oxide film 43 of 10 nm is formed on the surface of the groove 42 and the upper surface of the silicon nitride film 41 by a rapid thermal oxidation method at 1050 ° C. Further, the silicon nitride film 44 is formed to have a film thickness of 20 nm at a film forming temperature of 700 ° C., for example, using SiCl ₄ and NH ₃ as source gases. Next, a diffusion layer 45 is formed by ion implantation in the semiconductor substrate 31, and impurity activation annealing is performed by a rapid heat treatment method at 1000 ° C. or higher for 10 to 20 seconds to lower the resistance of the diffusion layer. This diffusion layer 45 functions as the source and drain of the EEPROM. In FIG. 13A, the same shape as in FIG. 12A is shown, and only the features in the manufacturing process are shown in FIG. 13B.
[0046]
It can be seen that an increase in trap density can be significantly suppressed by using a film with less Si—H as described above as the nitride film. As described above, when the silicon nitride film is formed using SiH ₂ Cl ₂ as a source gas at a high temperature, particularly at 850 ° C., Si—H bonds can be greatly reduced as shown in FIG.
[0047]
In particular, when the film is formed at 850 ° C., it has been confirmed that the Si—H bond concentration is 1.0 × 10 ²⁰ cm ⁻³ and the NH concentration is 4.0 × 10 ²¹ cm ⁻³ . In addition, when the film is formed at 780 ° C., it is confirmed that the Si—H concentration is 2.5 × 10 ²⁰ cm ⁻³ and the NH concentration is 5.0 × 10 ²¹ cm ⁻³ . Further, when the film is formed at 700 ° C., it is confirmed that the Si—H concentration is 8.0 × 10 ²⁰ cm ⁻³ and the NH concentration is 6.0 × 10 ²¹ cm ⁻³ . By changing the film formation temperature from 700 ° C. to 850 ° C. in this way, the Si—H concentration is 8.0 × 10 ²⁰ cm ⁻³ , 2.5 × 10 ²⁰ cm ⁻³ , 1.0 × 10 ²⁰ cm. ^The NH concentration decreases linearly to 6.0 × 10 ²¹ cm ⁻³ , 5.0 × 10 ²¹ cm ⁻³ , and 4.0 × 10 ²¹ cm ⁻³ , while it decreases sharply to ⁻³ . is decreasing.
[0048]
As described above, the N—H bond concentration that does not affect the behavior of hydrogen in the silicon nitride film does not change so much at each film formation temperature, but the Si—H bond concentration significantly decreases by increasing the film formation temperature. ing. By using such a silicon nitride film, the Si-H bond concentration can greatly suppress the deterioration of the tunnel oxide film as compared with the case of using a normal nitride film, and can provide an EEPROM having stable characteristics. .
[0049]
The film formation temperature of the silicon nitride film, the temperature of the high-temperature heating after the film formation, and the Si—H bond concentration can be measured as in the first embodiment. Further, when the hydrogen concentration in the tunnel insulating film was measured by SIMS (Secondary Ion Mass Spectroscopy), the hydrogen in the tunnel insulating film increased as the Si-H concentration in the silicon nitride film increased. The amount was found to increase. Thus, the effect of this embodiment can also be confirmed by measuring the hydrogen concentration in the oxide film.
(Modification of the second embodiment)
Here, when the silicon nitride film 34 shown in FIGS. 9A and 9B is formed, SiCl ₄ is used in place of SiH ₂ Cl ₂ that is used, so that it can be formed at a low temperature of about 700 ° C. Even if it forms, the film | membrane without Si-H can be formed. In such a case, the same material gas SiCl ₄ used for forming the silicon nitride film 41 shown in FIGS. 12A and 12B and for forming the silicon nitride film 44 shown in FIG. 13B is used. The source gas is used, and the production method is made efficient by preparing one kind of gas for forming the silicon nitride film. By using the silicon nitride film formed in this way, deterioration of the tunnel oxide film can be significantly suppressed as compared with the case of using a normal silicon nitride film.
(Third embodiment)
Si—H bonds can be greatly reduced by performing a heat treatment at 800 ° C. after depositing a nitride film at 700 ° C. or less, preferably 550 ° C. using Si ₂ Cl ₆ as a source gas for forming the nitride film. . By forming a nitride film at a low temperature using Si ₂ Cl ₆ as a source gas, the Si—H bond concentration immediately after the film formation becomes high, but hydrogen bonded to silicon at a relatively low temperature in the subsequent thermal process is converted into a nitride film. Can be desorbed from. For example, a nitride film formed at 550 ° C. using Si ₂ Cl ₆ as a source gas is heat-treated at 800 ° C., so that the Si—H bond concentration, which was 6 × 10 ²⁰ cm ⁻³ immediately after the film formation, is 2 × 10 ²⁰ cm. Can be reduced to ^-3 .
[0050]
The Si—H bond is desorbed by heat treatment and affects the device characteristics, but if the heat treatment temperature is 800 ° C. or less, the influence can be reduced. Moreover, it becomes easy to desorb hydrogen in the nitride film by lowering the deposition temperature of the silicon nitride film. In the NMOS and PMOS transistors, by providing the silicon nitride film according to this embodiment around the gate electrode, it is possible to prevent boron from penetrating into the substrate and accelerating diffusion of arsenic into the substrate.
[0051]
If the silicon nitride film formation temperature is too high, a high temperature is required to remove hydrogen bonded to silicon, and if a high temperature is applied, the gate insulating film will be adversely affected. It is preferable to lower the deposition temperature. However, when the film formation temperature is lowered, the growth rate of the nitride film becomes slow. Here, by using Si ₂ Cl ₆ , film formation is performed at a higher speed at the same film formation temperature than when SiH ₂ Cl ₂ is used as a source gas. Thus, after forming a film at a low temperature and using Si ₂ Cl ₆ at a high speed, the film is heated at a temperature set to 150 ° C. to 250 ° C. higher than the film forming temperature, so that the gate insulating film is not deteriorated. Is detached. That is, by using Si ₂ Cl ₆ as a source gas, a silicon nitride film is formed at a film formation temperature of 650 ° C. or lower, and heat treatment is performed at a temperature of 800 ° C. or higher. A nitride film can be formed.
[0052]
Further, in the EEPROM, by providing the silicon nitride film on the gate electrode according to this embodiment, it is possible to prevent the boron from penetrating into the substrate and maintain the characteristics of the tunnel oxide film. In the EEPROM, by using a thermal nitride film as a tunnel oxide film, it is possible to prevent boron from penetrating into the semiconductor substrate and improve the characteristics of the tunnel oxide film.
[0053]
Here, as shown in FIG. 15, by performing a heat treatment in N ₂ gas at 800 ° C. for 30 minutes after forming a nitride film in the range of 550 ° C. to 650 ° C. using Si ₂ Cl ₆ and NH ₃ as source gases. The CV characteristics of a MOS capacitor having boron-added polycrystalline silicon as a gate electrode when a thermal process at 1000 ° C. is performed after removing hydrogen from the nitride film once are shown. Here, the area of the capacitor is 0.1 mm ² , and when the nitride film is not used, the relationship between the voltage and the capacitance distribution when the nitride film is used and formed at 550 ° C., 600 ° C., and 650 ° C. is shown. ing.
[0054]
As the deposition temperature of the nitride film decreases, the Si—H bond increases, and the shift amount of V _FB increases. However, by performing heat treatment at a low temperature of 800 ° C. for 30 minutes in an N ₂ atmosphere, H bonded to Si can be desorbed without deteriorating the characteristics of the element (MOS capacitor). Thereafter, when heat treatment is performed at a high temperature of 1000 ° C., the Si—H bond has already decreased, and the deterioration of the characteristics of the device can be suppressed. Desorption of H bonded to Si in the nitride film during the heat treatment at 800 ° C. becomes easier as the deposition temperature of the nitride film decreases, and as shown in FIG. . That is, the lower the film formation temperature, the closer to the characteristics when the nitride film is not used.
[0055]
As a result, it is possible to maintain the characteristics of the tunnel oxide film without adopting an oxynitride film, which has previously contained nitrogen in order to improve the characteristics of the silicon oxide film to prevent the influence of hydrogen incorporation in the subsequent process, as the tunnel oxide film. .
[0056]
The film formation temperature of the silicon nitride film, the temperature of the high-temperature heating after the film formation, and the Si—H bond concentration can be measured as in the first embodiment.
[0057]
【The invention's effect】
According to the present invention, it is possible to provide a method for manufacturing a fine semiconductor device that maintains the characteristics of a gate insulating film even when a nitride film with few Si—H bonds is formed and a subsequent high-temperature thermal process is performed.
[0058]
Furthermore, according to another aspect of the present invention, a method of manufacturing a semiconductor device can be provided that prevents accelerated diffusion of boron from a polycrystalline silicon layer to a semiconductor substrate in a thermal process when manufacturing a PMOS transistor.
[0059]
Furthermore, according to another aspect of the present invention, a method of manufacturing a semiconductor device can be provided that prevents accelerated diffusion of arsenic in a semiconductor substrate during a thermal process when manufacturing an NMOS transistor.
[0060]
According to another aspect of the present invention, the deterioration of the tunnel oxide film can be prevented when manufacturing the EEPROM.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
FIG. 2A is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention. (B) is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which is the 1st Embodiment of this invention.
FIG. 3A is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention. (B) is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which is the 1st Embodiment of this invention.
FIG. 4A is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention. (B) is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which is the 1st Embodiment of this invention.
FIG. 5A is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention. (B) is sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which is the 1st Embodiment of this invention.
FIG. 6A is a diagram showing capacitance-voltage characteristics of a MOS capacitor showing the effect of the present invention. (B) is a figure which shows the relationship between the hydrogen concentration which shows the effect of this invention, and Vfb.
FIG. 7 is a configuration diagram of a MOS capacitor showing the effect of the present invention.
FIG. 8 is a top view showing a second embodiment of the present invention.
FIG. 9A is a cross-sectional view taken along the line AA ′ in FIG. 8, showing one step in the method for manufacturing a semiconductor device according to the second embodiment of the present invention. (B) is sectional drawing of the BB 'direction in FIG. 8 which shows 1 process of the manufacturing method of the semiconductor device which is the 2nd Embodiment of this invention.
FIG. 10A is a cross-sectional view taken along the line AA ′ in FIG. 8, showing one step in the method for manufacturing a semiconductor device according to the second embodiment of the present invention. (B) is sectional drawing of the BB 'direction in FIG. 8 which shows 1 process of the manufacturing method of the semiconductor device which is the 2nd Embodiment of this invention.
FIG. 11A is a cross-sectional view taken along the line AA ′ in FIG. 8, showing one step in the method for manufacturing a semiconductor device according to the second embodiment of the present invention. (B) is sectional drawing of the BB 'direction in FIG. 8 which shows 1 process of the manufacturing method of the semiconductor device which is the 2nd Embodiment of this invention.
FIG. 12A is a cross-sectional view taken along the line AA ′ in FIG. 8, showing one step in the method for manufacturing a semiconductor device according to the second embodiment of the present invention. (B) is sectional drawing of the BB 'direction in FIG. 8 which shows 1 process of the manufacturing method of the semiconductor device which is the 2nd Embodiment of this invention.
FIG. 13A is a cross-sectional view taken along the line AA ′ in FIG. 8, showing one step in the method for manufacturing a semiconductor device according to the second embodiment of the present invention. (B) is sectional drawing of the BB 'direction in FIG. 8 which shows 1 process of the manufacturing method of the semiconductor device which is the 2nd Embodiment of this invention.
FIG. 14 is a temperature concentration characteristic diagram showing the film formation temperature dependence of the hydrogen concentration in the nitride film.
FIG. 15 is a characteristic diagram showing the relationship between the voltage and capacitance of a MOS capacitor.
[Explanation of symbols]
1,20 P-type silicon substrate 2,9,11,14,16 Resist mask 3,21 N-type well 4 Thermal oxynitride film 5 Polycrystalline silicon layer 6,7 Gate electrode 8, 36,43 Oxide film 10,15 P Type diffusion layers 12, 17 N type diffusion layers 20, 13, 24, 34, 41, 44 Silicon nitride film 22 Silicon oxide films 23, 33, 38, 40 Polycrystalline silicon film 31 Silicon substrates 32, 37 Silicon oxide film 35, 42 groove 39 ONO film 45 diffusion layer

Claims (4)

Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode through the gate insulating film;
Forming a silicon oxide film so as to cover the gate electrode;
Forming a silicon nitride film on the silicon oxide film at a temperature of 650 ° C. or less using Si ₂ Cl ₆ as a source gas;
A method of manufacturing a semiconductor device, comprising a step of performing a heat treatment at a temperature of 150 to 250 degrees higher than the deposition temperature of the silicon nitride film and at a temperature of 800 degrees or less . Forming a gate insulating film on the semiconductor substrate;
Forming a polycrystalline silicon film through the gate insulating film;
Forming a silicon nitride film on the polycrystalline silicon film at a temperature of 650 ° C. or less using Si ₂ Cl ₆ as a source gas;
A method of manufacturing a semiconductor device, comprising a step of performing a heat treatment at a temperature of 150 to 250 degrees higher than the deposition temperature of the silicon nitride film and at a temperature of 800 degrees or less . Forming a gate insulating film on the semiconductor substrate;
Forming a polycrystalline silicon film through the gate insulating film;
Forming an interelectrode insulating film on the polycrystalline silicon film;
Forming a polycrystalline silicon film on the interelectrode insulating film;
Forming a silicon nitride film on the polycrystalline silicon film formed on the interelectrode insulating film at a temperature of 650 ° C. or less using Si ₂ Cl ₆ as a source gas;
A method of manufacturing a semiconductor device, comprising a step of performing a heat treatment at a temperature of 150 to 250 degrees higher than the deposition temperature of the silicon nitride film and at a temperature of 800 degrees or less . 4. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon nitride film is formed by reacting NH ₃ with Si ₂ Cl ₆ that is a source gas. 5.

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