JP3994703B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
Japanese Patent Application Laid-Open No. 2001-144292 discloses a silicon carbide semiconductor device having a super junction. Specifically, as shown in FIG. 14, an N-type layer 101 is formed on an N ⁺ -type SiC substrate 100, and P-type base regions 102a and 102b, an N-type source region are formed on the surface layer portion of the N-type layer 101. 103, an N-type channel layer 104 is formed, and a gate electrode 106 is disposed on the upper surface of the substrate via a gate oxide film 105. On the other hand, a P-type region 107 is arranged in parallel inside the N-type layer 101, and the N-type region 101a and the P-type region 107 are alternately buried in the lateral direction to form a super junction. With this super junction, a high breakdown voltage can be achieved. However, there is a demand for flexible design of the super junction.
[0003]
[Problems to be solved by the invention]
The present invention has been made under such a background, and an object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing the same that can further increase the degree of freedom in design.
[0004]
[Means for Solving the Problems]
The invention described in claim 1 is characterized in that the impurity region in the super junction is thinnest in the deepest region in the depth direction and darkest in the shallowest region . Thus, the degree of freedom in design is increased by making the concentration gradient in the depth direction desired.
[0005]
According to a second aspect of the present invention, the impurity region at the super junction is characterized in that the lateral width is widest in the deepest region in the depth direction and narrowest in the shallowest region . Thus, the degree of freedom in design is increased by allowing the width to be changed as desired in the depth direction.
[0006]
According to a third aspect of the present invention, the impurity region at the super junction is characterized in that the lateral width is narrowest in the deepest region in the depth direction and widest in the shallowest region . As described above, the concentration gradient in the depth direction can be made desired, and the width can be changed in the depth direction as desired, thereby increasing the degree of freedom in design.
[0007]
As a manufacturing method, as claimed in claim 4, to form a drift layer of a first conductivity type on a SiC substrate of a first conductivity type by epitaxial growth. Then, by ion implantation of first time by using a mask to drift layer, burying the first impurity region of a second conductivity type in the drift layer below the mask opening. Furthermore, by ion implantation of second time using another mask to the drift layer, a second impurity of the first higher than the impurity concentration of the impurity region of the second conductivity type in the drift layer below the mask opening The region is embedded on the first impurity region so as to be connected to the first impurity region by the first ion implantation.
[0008]
Thus, the silicon carbide semiconductor device according to the first, second, and third aspects can be manufactured.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a longitudinal sectional view of a silicon carbide semiconductor device in the present embodiment.
[0010]
In FIG. 1, on an N ⁺ type (first conductivity type) SiC substrate 1 serving as a drain region, an N ⁻ type (low concentration first conductivity type) drift layer 2 composed of an epitaxial layer, and an epitaxial layer A P ⁺ -type (second conductivity type) first gate layer 3 and an N ⁺ -type (first conductivity type) source layer 4 made of an epitaxial layer are sequentially stacked. A trench 5 that penetrates the source layer 4 and the first gate layer 3 and reaches the drift layer 2 is formed. Further, an N ⁻ type (first conductivity type) channel layer 6 made of an epitaxial layer is formed on the inner wall of the trench 5, and a P ⁺ type (second conductivity type) first made of an epitaxial layer is formed on the inside thereof. Two gate layers 7 are formed.
[0011]
An insulating film (LTO film) 8 is formed on the upper surface of the substrate, and the first gate electrodes 11 and 12 are connected to the first gate layer 3 and the second gate electrodes 9 and 10 through contact holes provided in the insulating film 8. Is connected to the second gate layer 7 and the source electrode 13 is connected to the N ⁺ source layer 4. Aluminum is used for the electrode materials 9 and 11, and nickel is used for the electrode materials 10 and 12. Note that the metal materials 9 and 11 are not necessary when contacting the N-type SiC layer. A drain electrode 14 is formed on the entire back surface (lower surface) of the substrate 1.
[0012]
As the transistor operation, the drain current is adjusted by changing the channel width by adjusting the width of the depletion layer in the channel layer 6 sandwiched between the gate layers 3 and 7 by the voltages to the first and second gate terminals. .
[0013]
Further, a trench 20 that penetrates the source layer 4 and the first gate layer 3 and reaches the drift layer 2 is formed in the outer peripheral portion (chip outer peripheral portion) of the transistor cell formation region. A P ⁺ type SiC layer 21 is formed on the inner wall of the trench 20, and the P ⁺ type SiC layer 21 functions as a guard ring. The upper surface of the P ⁺ -type SiC layer 21 (chip outer peripheral portion) is covered with an insulating film (LTO film) 8.
[0014]
On the other hand, in the drift layer 2 in the transistor cell formation region, a P-type (second conductivity type) impurity region 30 is juxtaposed, so that the drift layer 2 has an N-type (first conductivity type). Impurity regions and P-type impurity regions 30 are alternately buried in the lateral direction to form a super junction.
[0015]
Here, in the present embodiment, the buried P-type impurity region 30 has a different concentration in the depth direction and a lateral width in the depth direction. Specifically, the concentration has three levels in the depth direction, the thinnest in the deepest region 31 (P ⁻ ), and the intermediate concentration in the intermediate depth region 32 (P). In the shallowest region 32, it is the darkest (P ⁺ ). On the other hand, the lateral width is the widest in the deepest region 31, the intermediate width in the intermediate depth region 32, and the narrowest in the shallowest region 32.
[0016]
Regarding the concentrations of the regions 31, 32, and 33, when aluminum is used as an impurity, for example, the P ⁻ region 31 is 5 × 10 ¹⁶ to 1 × 10 ¹⁸ atms / cm ³ and the P region 32 is 5 × 10 ^17. ˜1 × 10 ¹⁹ atoms / cm ³ and the P ⁺ region 33 is 5 × 10 ^{18 to} 5 × 10 ²⁰ atoms / cm ³ .
[0017]
As described above, with respect to the impurity region 30 in the super junction, the concentration gradient in the depth direction can be made desired, and the width is changed in the depth direction as desired, thereby increasing the degree of freedom in designing the super junction.
[0018]
Note that the potential of the P-type impurity region 30 constituting the super junction may be floating or may be a ground potential together with the source. FIG. 1 shows the case of floating, and FIG. 2 shows the case of ground potential.
[0019]
On the other hand, a super junction due to the P-type impurity region 30 is not formed in the guard ring portion in the outer peripheral portion (chip outer peripheral portion) of the transistor cell. That is, the super junction structure is adopted only in the transistor cell formation region, and the super junction structure is not adopted in the outer periphery of the transistor cell formation region. This can prevent the breakdown voltage from decreasing.
[0020]
Next, a manufacturing method will be described.
As shown in FIG. 3A, an N ⁻ drift layer 2 is formed on an N ⁺ type SiC substrate 1 by epitaxial growth. Then, a masked mask 40 is disposed on the N ⁻ drift layer 2. That is, the mask 40 having the opening 41 is formed. In this state, aluminum ions are implanted. This ion implantation is performed with a high implantation energy (for example, 400 keV) and a low implantation amount. As a result, the P-type region (P ⁻ region) 31 having the deepest super junction and the low concentration is formed.
[0021]
Subsequently, as shown in FIG. 3B, a masked mask 42 is disposed on the mask 40. At this time, the opening 41 of the mask 40 is closed by the mask 42 and an opening 43 having a smaller area than the opening 41 is formed in the region. The center of the opening 41 is coincident with the center of the opening 42. In this state, aluminum ions are implanted. This ion implantation is performed with a medium implantation energy (for example, 200 keV) and with a medium implantation amount. As a result, a P-type region 32 having an intermediate depth and a medium concentration of the super junction is formed.
[0022]
Subsequently, as shown in FIG. 4A, a masked mask 44 is disposed on the mask 42. At this time, the opening 43 of the mask 42 is blocked by the mask 44 and an opening 45 having a smaller area than the opening 43 is formed in the region. The center of the opening 43 and the center of the opening 45 coincide. In this state, aluminum ions are implanted. This ion implantation is performed with a low implantation energy (for example, 100 keV) and a high implantation amount. As a result, the shallowest and high-concentration P-type region (P ⁺ region) 33 of the super junction is formed.
[0023]
Thereafter, as shown in FIG. 4B, a first gate layer (P ⁺ layer) 3 and an N ⁺ source layer 4 are formed on the N ⁻ drift layer 2 by continuous epitaxial growth.
Then, as shown in FIG. 5A, trenches 5 and 20 that penetrate the source layer 4 and the first gate layer 3 and reach the drift layer 2 are formed.
[0024]
Thereafter, as shown in FIG. 5B, an N ⁻ type epitaxial layer 6 is formed on the substrate including the inside of the trenches 5 and 20 by epitaxial growth. Then, as shown in FIG. 6A, the N ⁻ -type epitaxial layer 6 in the outer peripheral portion of the transistor cell formation region is thinned by etching by a predetermined amount t1 by RIE. Further, as shown in FIG. 6B, a P ⁺ layer 7 is formed on the surface layer portion of the N ⁻ -type epi layer 6 by thermal diffusion. As a result, all of the guard ring formation region in the outer peripheral portion of the transistor cell formation region becomes the P ⁺ layer 7. Although the formation of the P ⁺ layer 7 by thermal diffusion, may be formed the P ⁺ layer 7 by epitaxial growth or ion implantation.
[0025]
Subsequently, as shown in FIG. 7A, the N ⁻ type epi layer 6 and the P ⁺ layer 7 in the source contact region A1 in the transistor cell formation region are removed by RIE. Further, as shown in FIG. 7B, the source layer 4 in the first gate contact region A2 in the transistor cell formation region is removed by RIE.
[0026]
Thereafter, as shown in FIG. 1, after depositing the insulating film 8 and forming a contact hole, the gate electrodes 9 and 10, the gate electrodes 11 and 12, and the source electrode 13 are formed. Further, the drain electrode 14 is formed on the back surface of the substrate.
[0027]
In this way, the first ion implantation is performed on the drift layer 2 of FIG. 3A using the mask 40 to obtain a P ⁻ type to a predetermined depth in the drift layer 2 below the mask opening 41. The impurity region 31 is buried, and the drift layer 2 shown in FIG. 3B is ion-implanted a second time using another mask 42, so that a predetermined value in the drift layer 2 below the mask opening 43 is obtained. And a step of burying the P-type impurity region 32 in a state of being connected to the P-type impurity region 31 by the first ion implantation (the same applies to the third ion implantation for the second ion implantation). The mask opening 41 in the second ion implantation and the mask opening 43 in the second ion implantation have the same center, the area, the implantation energy in the first ion implantation, and the ion implantation in the second ion implantation. Injection energy And chromatography were both varied amount of injected ions. As a result, the impurity regions 30 can have different concentrations in the depth direction, and can have different lateral widths in the depth direction.
[0028]
As another example instead of FIG. 1, as shown in FIG. 8, the lateral width is the narrowest in the deepest P ⁻ region 51, the intermediate width in the intermediate depth P region 52, and the shallowest. The P ⁺ region 52 may be widest.
[0029]
In manufacturing, as shown in FIGS. 9A, 9B, and 9C, implantation is performed when ions are implanted while the widths of the openings 61, 63, 65 of the masks 60, 62, 64 are narrowed. What is necessary is just to adjust energy and injection amount.
[0030]
Moreover, although applied to JFET in FIG. 1, you may apply not only to this but to MOSFET as shown in FIG. That is, an N type epi layer 71 is formed on an N ⁺ type SiC substrate 70, and P type base regions 72 and 73, an N ⁺ type source region 74, an N ⁻ type channel are formed on the surface layer portion of the N type epi layer 71. A layer 75 is formed, and a gate electrode 77 is disposed on the upper surface of the substrate via a gate oxide film 76. Source electrode 78 is in contact with N ⁺ source region 74 and P ⁺ base region 73. A drain electrode 79 is formed on the back surface of the substrate 70. In this MOSFET, a P-type region 30 in which a P ⁻ region 31, a P region 32, and a P ⁺ region 33 are stacked is embedded in the N-type drift layer 71 side by side. As a manufacturing method, as shown in FIG. 11, after growing an N-type epi layer 71 by a predetermined thickness on an N ⁺ -type SiC substrate 70, a P-type region 30 is formed by ion implantation, and thereafter The N-type epi layer 71 may be continuously grown.
[0031]
Further, in FIG. 1, the impurity region 30 has a different concentration in the depth direction and a lateral width in the depth direction. However, the present invention is not limited to this, and the impurity region 30 has a lateral width as shown in FIG. The width in the direction is the same in the depth direction, and the concentration is different in the depth direction. Alternatively, as shown in FIG. 13, the impurity region 30 has the same concentration in the depth direction and the width in the lateral direction is the depth. The directions may be different.
[0032]
Furthermore, although the trench 5 has an oblique side surface in FIG. 1, it may be vertical .
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view of a silicon carbide semiconductor device in an embodiment.
FIG. 2 is a longitudinal sectional view of a silicon carbide semiconductor device.
FIG. 3 is a longitudinal sectional view for illustrating a process for manufacturing a silicon carbide semiconductor device.
FIG. 4 is a longitudinal sectional view for illustrating a process for manufacturing a silicon carbide semiconductor device.
FIG. 5 is a longitudinal sectional view for illustrating a process for manufacturing a silicon carbide semiconductor device.
FIG. 6 is a longitudinal sectional view for illustrating a process for manufacturing a silicon carbide semiconductor device.
FIG. 7 is a longitudinal sectional view for illustrating a process for manufacturing a silicon carbide semiconductor device.
FIG. 8 is a longitudinal sectional view of another example of a silicon carbide semiconductor device.
FIG. 9 is a longitudinal sectional view for illustrating the manufacturing process for the silicon carbide semiconductor device.
FIG. 10 is a longitudinal sectional view of another example of a silicon carbide semiconductor device.
FIG. 11 is a longitudinal sectional view for illustrating a manufacturing step for another example silicon carbide semiconductor device.
FIG. 12 is a longitudinal sectional view of another example of a silicon carbide semiconductor device.
FIG. 13 is a longitudinal sectional view of another example of a silicon carbide semiconductor device.
FIG. 14 is a longitudinal sectional view of a silicon carbide semiconductor device for illustrating a conventional technique.
[Explanation of symbols]
1 ... N ⁺ -type SiC substrate, 2 ... N ^- drift layer, 3 ... first gate layer (P ⁺ layer), 4 ... N ⁺ source layer, 5 ... trench, 6 ... N ^- channel layer, 7 ... second gate layer (P ⁺ layer), 30 ... P-type impurity region, 31 ... P ^- area, 32 ... P region, 33 ... P ⁺ region.

Claims (5)

A low-concentration first conductivity type drift layer (2) made of SiC is formed on the first conductivity type SiC substrate (1) to be a drain region, and the drift layer (2) or the drift layer is formed. By arranging the first conductivity type source layer (4) made of SiC on the surface layer portion of (2), and further arranging the second conductivity type impurity region (30) inside the drift layer (2). In the silicon carbide semiconductor device in which the first conductivity type impurity region and the second conductivity type impurity region are alternately buried in the drift layer (2) in the lateral direction to form a super junction,
The impurity concentration of the impurity region (30) is the thinnest in the deepest region in the depth direction and the highest in the shallowest region . A low-concentration first conductivity type drift layer (2) made of SiC is formed on the first conductivity type SiC substrate (1) serving as a drain region, and the drift layer (2) or the drift layer is formed. By arranging the first conductivity type source layer (4) made of SiC on the surface layer portion of (2), and further arranging the second conductivity type impurity region (30) inside the drift layer (2). In the silicon carbide semiconductor device in which the first conductivity type impurity region and the second conductivity type impurity region are alternately buried in the drift layer (2) in the lateral direction to form a super junction,
The silicon carbide semiconductor device characterized in that the impurity region (30) is widest in the deepest region in the depth direction and narrowest in the shallowest region . A low-concentration first conductivity type drift layer (2) made of SiC is formed on the first conductivity type SiC substrate (1) to be a drain region, and the drift layer (2) or the drift layer is formed. By arranging the first conductivity type source layer (4) made of SiC on the surface layer portion of (2), and further arranging the second conductivity type impurity region (30) inside the drift layer (2). In the silicon carbide semiconductor device in which the first conductivity type impurity region and the second conductivity type impurity region are alternately buried in the drift layer (2) in the lateral direction to form a super junction,
The impurity region (30) has a lateral width that is the narrowest in the deepest region in the depth direction and the widest in the shallowest region . A low-concentration first conductivity type drift layer (2) made of SiC is formed on the first conductivity type SiC substrate (1) serving as a drain region, and the drift layer (2) or the drift layer is formed. By arranging the first conductivity type source layer (4) made of SiC on the surface layer portion of (2), and further arranging the second conductivity type impurity region (30) inside the drift layer (2). A method of manufacturing a silicon carbide semiconductor device having a super junction by burying first conductivity type impurity regions and second conductivity type impurity regions alternately in a lateral direction in a drift layer (2),
  Forming a low-concentration first conductivity type drift layer (2) on the first conductivity type SiC substrate (1) by epitaxial growth;
  A first ion implantation is performed on the drift layer (2) using the mask (40), and the first impurity region (second conductivity type) (in the drift layer (2) below the mask opening (41) ( 31) burying;
  A second ion implantation is performed on the drift layer (2) using another mask (42), and the first impurity region (31) is formed in the drift layer (2) below the mask opening (43). On the first impurity region (31), the second impurity region (32) of the second conductivity type higher than the impurity concentration is connected to the first impurity region (31) by the first ion implantation. Burying process,
The manufacturing method of the silicon carbide semiconductor device characterized by the above-mentioned. The mask opening (41) in the first ion implantation and the mask opening (43) in the second ion implantation have the same center, the area, the implantation energy in the first ion implantation, and the two. The method for manufacturing a silicon carbide semiconductor device according to claim 4 , wherein an implantation energy in the second ion implantation and an ion implantation amount are both different.

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