JP3991705B2 - Digital / analog conversion circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to a DAC (Digital to Analog Converter) that converts a digital signal into an analog signal, and more particularly, uses a PWM (Pulse Width Modulation) to convert an analog signal into an analog signal. It relates to a DAC to be converted.
[0002]
[Prior art]
Conventionally, a DAC that converts a digital signal into an analog signal using PWM is used. Such a DAC includes a PWM circuit that modulates the pulse width (duty) of an output signal based on input data, and a low-pass filter that smoothes the output signal of the PWM circuit. As the low-pass filter, a CR-type low-pass filter in which a resistor and a capacitor are combined is generally used for a predetermined number of stages. In order to stabilize the output waveform of the DAC, it is necessary to increase the CR time constant or increase the number of stages of the low-pass filter.
[0003]
On the other hand, in a printer, a DAC is used in a motor driver circuit that drives a motor for feeding printing paper and moving a print head. In such a DAC, it is required to shorten the response time. However, if the CR time constant or the number of stages of the low-pass filter is large, there is a problem that the response of the DAC becomes slow and a necessary speed cannot be obtained.
[0004]
[Problems to be solved by the invention]
Therefore, in view of the above points, an object of the present invention is to shorten a response time while keeping an output waveform stable in a DAC using PWM.
[0006]
[Means for Solving the Problems]
  To solve the above problemsOf the present inventionOneThe DAC according to the above aspect generates a pulse width modulation circuit that modulates the pulse width of the output signal according to the control signal, a control signal to be supplied to the pulse width modulation circuit based on the input data, and a pulse width modulation circuit And pulse generation control means for replacing the output signal of the pulse width modulation circuit with a high level or low level signal during the settling period when the absolute value of the change amount of the pulse width to be output exceeds a predetermined value, and pulse generation control The low-pass filter for smoothing the signal output from the means to generate an analog output voltage, the analog / digital conversion circuit for analog / digital conversion of the analog output voltage generated by the low-pass filter, and the analog / digital conversion circuit The settling period is set by comparing the data to be input with the input data. ; And a regulator.
[0007]
  In the above, the pulse generation control means outputs a high level signal in the settling period when the change amount of the pulse width to be output by the pulse width modulation circuit is positive and the value exceeds a predetermined value. And an OR circuit for obtaining a logical sum of the output signal of the pulse width modulation circuit and the output signal of the control unit.
[0008]
  Alternatively, the pulse generation control means outputs a low level signal in the settling period when the change amount of the pulse width to be output by the pulse width modulation circuit is negative and the absolute value thereof exceeds a predetermined value. And an AND circuit that obtains a logical product of the output signal of the pulse width modulation circuit and the output signal of the control unit.
[0009]
  Alternatively, the pulse generation control means selects a control unit that outputs a high-level or low-level signal based on the amount of change in pulse width that the pulse width modulation circuit should output, and an output signal of the control unit during the settling period. A selection circuit that selects an output signal of the pulse width modulation circuit in other periods may be included.
[0011]
According to the present invention, in a DAC using PWM, in the settling period in which the pulse width changes when the absolute value of the change amount of the pulse width to be output by the pulse width modulation circuit exceeds a predetermined value, the pulse width modulation is performed. By supplying a high-level or low-level signal to the low-pass filter instead of the circuit output signal, the response time can be shortened while the output waveform remains stable.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same constituent elements are denoted by the same reference numerals, and the description thereof is omitted.
FIG. 1 is a block diagram showing a configuration of a DAC according to the first embodiment of the present invention, and FIG. 2 is a timing chart showing signal waveforms of respective parts of the DAC according to the first embodiment of the present invention. .
[0013]
As shown in FIG. 1, this DAC generates a control signal supplied to the PWM circuit 11 based on the PWM circuit 11 that modulates the pulse width (duty) of the output signal in accordance with the control signal and the input data. When the change amount of the pulse width to be output by the PWM circuit 11 is positive and the value exceeds a predetermined value, the output signal of the PWM circuit 11 is set to the settling period T._SThe pulse generation control means 12 to be replaced with a high level signal in FIG. 5 and the signal output from the pulse generation control means 12 are smoothed to obtain an analog output voltage V_OUTAnd a low-pass filter 13 for generating.
[0014]
The pulse generation control unit 12 includes a control unit 14, an OR circuit 15, and a lookup table 16. The control unit 14 generates a control signal to be supplied to the PWM circuit 11 based on the input data. In addition, when the amount of change in the pulse width to be output by the PWM circuit 11 is positive and the value exceeds a predetermined value, the control unit 14 determines the pulse width τ before the predetermined change.₁And the pulse width τ after a predetermined change₂And the settling period T corresponding to this value is output to the look-up table 16._SIs input from the lookup table 16 and the settling period T_SA high level signal is output at. The OR circuit 15 obtains and outputs a logical sum of the output signal of the PWM circuit 11 and the output signal of the control unit 14.
[0015]
Settling period T_SIs the pulse width τ₁And τ₂Function f (τ₁, Τ₂). This value may be calculated by the pulse generation control means 12 each time, but in this embodiment, the response time is shortened by using the lookup table 16. The lookup table 16 has a pulse width τ₁And τ₂Settling period T corresponding to the value of_SThe value of is stored.
[0016]
As the low-pass filter 13, a CR-type low-pass filter in which a resistor and a capacitor are combined is used in a predetermined number of stages. In the present embodiment, a two-stage low-pass filter including resistors R1 and R2 and capacitors C1 and C2 is used.
[0017]
Next, the operation of the DAC according to the present embodiment will be described with reference to FIGS.
Prior to the predetermined change in the pulse width, the control unit 14 determines that the pulse width τ has a constant period T.₁Pulse P_AA control signal is supplied to the PWM circuit 11 so as to generate. Pulse P generated by the PWM circuit 11_AIs input to the input terminal A of the OR circuit 15. Further, the control unit 14 maintains the input terminal B of the OR circuit 15 at a low level. The OR circuit 15 has a pulse P input to the input terminal A because the input terminal B is at a low level._APulse P from output terminal X_XOutput as. Pulse P_XIs smoothed by the low-pass filter 13 and the analog output voltage V_OUTThe value of V₁become.
[0018]
During the predetermined change in the pulse width, the control unit 14 determines that the pulse width τ has a constant period T.₂Pulse P_AA control signal is supplied to the PWM circuit 11 so as to generate. In addition, the control unit 14 determines the pulse width τ before and after the predetermined change.₁, Τ₂Settling period T corresponding to the value of_SIs previously read from the look-up table 16 and its settling period T_SHigh level pulse P during_BIs output to the input terminal B of the OR circuit 15. The OR circuit 15 receives the pulse P input to the input terminal B._BIs high level, so the pulse P_BPulse P from output terminal X_XOutput as. Pulse P_XIs smoothed by the low-pass filter 13 and the analog output voltage V_OUTRises rapidly.
[0019]
Settling period T_SAfter the elapse of time, the control unit 14 determines the pulse width τ at a constant period T.₂Pulse P_AA control signal is supplied to the PWM circuit 11 so as to generate. Pulse P generated by the PWM circuit 11_AIs input to the input terminal A of the OR circuit 15. Further, the control unit 14 maintains the input terminal B of the OR circuit 15 at a low level. The OR circuit 15 has a pulse P input to the input terminal A because the input terminal B is at a low level._APulse P from output terminal X_XOutput as. Pulse P_XIs smoothed by the low-pass filter 13 and the analog output voltage V_OUTThe value of V₂become.
[0020]
In this way, in a transition period in which the analog output voltage must be increased rapidly, a high level signal is supplied to the low-pass filter 13 for a predetermined period instead of the output signal of the PWM circuit 11, thereby reducing the DAC response time. It can be shortened.
[0021]
Next, a second embodiment of the present invention will be described. FIG. 3 is a block diagram showing a configuration of a DAC according to the second embodiment of the present invention, and FIG. 4 is a timing chart showing signal waveforms of respective parts of the DAC according to the second embodiment of the present invention. .
[0022]
As shown in FIG. 3, the DAC generates a control signal to be supplied to the PWM circuit 21 based on the PWM circuit 21 that modulates the pulse width (duty) of the output signal according to the control signal, and the input data. When the change amount of the pulse width to be output by the PWM circuit 21 is negative and the absolute value thereof exceeds a predetermined value, the output signal of the PWM circuit 21 is set to the settling period T._SThe pulse generation control means 22 to be replaced with a low level signal in FIG. 5 and the signal output from the pulse generation control means 22 are smoothed to obtain an analog output voltage V_OUTAnd a low-pass filter 23 for generating.
[0023]
The pulse generation control means 22 includes a control unit 24, an AND circuit 25, and a lookup table 26. The control unit 24 generates a control signal to be supplied to the PWM circuit 21 based on the input data. Further, the control unit 24, when the pulse width to be output by the PWM circuit 21 is negative and the absolute value thereof exceeds a predetermined value, the pulse width τ before the predetermined change.₁And the pulse width τ after a predetermined change₂And the settling period T corresponding to this value is output to the look-up table 26._SIs input from the lookup table 26 and the settling period T_SA low level signal is output at. The AND circuit 25 calculates and outputs a logical product of the output signal of the PWM circuit 21 and the output signal of the control unit 24.
[0024]
Settling period T_SIs the pulse width τ₁And τ₂Function f (τ₁, Τ₂). Although this value may be obtained by calculation each time in the pulse generation control means 22, in this embodiment, the response time is shortened by using the lookup table 26. The lookup table 26 has a pulse width τ₁And τ₂Settling period T corresponding to the value of_SThe value of is stored.
[0025]
As the low-pass filter 23, a CR-type low-pass filter in which a resistor and a capacitor are combined is used in a predetermined number of stages. In the present embodiment, a two-stage low-pass filter including resistors R1 and R2 and capacitors C1 and C2 is used.
[0026]
Next, the operation of the DAC according to the present embodiment will be described with reference to FIGS.
Before the predetermined change in the pulse width, the control unit 24 determines that the pulse width τ₁Pulse P_CA control signal is supplied to the PWM circuit 21 so as to generate. Pulse P generated by the PWM circuit 21_CIs input to the input terminal C of the AND circuit 25. In addition, the control unit 24 maintains the input terminal D of the AND circuit 25 at a high level. The AND circuit 25 has a pulse P input to the input terminal C because the input terminal D is at a high level._CPulse P from output terminal Y_YOutput as. Pulse P_YIs smoothed by the low-pass filter 23 and the analog output voltage V_OUTThe value of V₁become.
[0027]
During the predetermined change in the pulse width, the control unit 24 determines that the pulse width τ has a constant period T.₂Pulse P_CA control signal is supplied to the PWM circuit 21 so as to generate. Further, the control unit 24 determines the pulse width τ before and after the predetermined change in the pulse width.₁, Τ₂Settling period T corresponding to the value of_SIs previously read from the look-up table 26 and the settling period T_SDuring this period, the low level pulse P_DIs output to the input terminal D of the AND circuit 25. The AND circuit 25 receives the pulse P input to the input terminal D._DIs low level, so the pulse P_DPulse P from output terminal Y_YOutput as. Pulse P_YIs smoothed by the low-pass filter 23 and the analog output voltage V_OUTFalls rapidly.
[0028]
Settling period T_SAfter the elapse of time, the control unit 24 sets the pulse width τ at a constant period T.₂Pulse P_CA control signal is supplied to the PWM circuit 21 so as to generate. Pulse P generated by the PWM circuit 21_CIs input to the input terminal C of the AND circuit 25. In addition, the control unit 24 maintains the input terminal D of the AND circuit 25 at a high level. The AND circuit 25 has a pulse P input to the input terminal C because the input terminal D is at a high level._CPulse P from output terminal Y_YOutput as. Pulse P_YIs smoothed by the low-pass filter 23 and the analog output voltage V_OUTThe value of V₂become.
[0029]
In this way, in a transition period in which the analog output voltage must be drastically lowered, a low level signal is supplied to the low pass filter 23 in place of the output signal of the PWM circuit 21 to thereby reduce the DAC response time. It can be shortened.
[0030]
Next, a third embodiment of the present invention will be described. FIG. 5 is a block diagram showing a configuration of a DAC according to the third embodiment of the present invention, and FIG. 6 is a timing showing a signal waveform in an increase mode of each part of the DAC according to the third embodiment of the present invention. FIG. 7 is a timing chart showing signal waveforms in a decreasing mode of each part of the DAC according to the third embodiment of the present invention.
[0031]
As shown in FIG. 5, the DAC generates a control signal to be supplied to the PWM circuit 31 based on the PWM circuit 31 that modulates the pulse width (duty) of the output signal according to the control signal and the input data. When the change amount of the pulse width to be output by the PWM circuit 31 exceeds a predetermined value, the output signal of the PWM circuit 31 is set to the settling period T_SThe pulse generation control means 32 to be replaced with a high level or low level signal in FIG._OUTAnd a low-pass filter 33 for generating.
[0032]
The pulse generation control unit 32 includes a control unit 34, a forced pulse generation circuit 35, a lookup table 36, and a selection circuit 37. The control unit 34 generates a control signal to be supplied to the PWM circuit 31 based on the input data. Further, the control unit 34, when the absolute value of the pulse width to be output by the PWM circuit 31 exceeds a predetermined value, the pulse width τ before the predetermined change.₁And the pulse width τ after a predetermined change₂And the settling period T corresponding to this value is output to the look-up table 36._SAre input from the lookup table 36, and an output value change trigger pulse is generated. Output value change trigger pulse, settling period T_SValue, pulse width τ₁And τ₂Is supplied to the forced pulse generation circuit 35.
[0033]
Settling period T_SIs the pulse width τ₁And τ₂Function f (τ₁, Τ₂). Although this value may be obtained by calculation each time in the pulse generation control means 32, in this embodiment, the response time is shortened by using the lookup table 36. The look-up table 36 has a pulse width τ₁And τ₂Settling period T corresponding to the value of_SThe value of is stored.
[0034]
The forced pulse generation circuit 35 responds to the output value change trigger pulse and sets the settling period T_SGenerate a forced pulse and a pulse width τ₁Value and pulse width τ₂A high / low switching signal is generated based on the magnitude relationship with the value of. In other words, the forced pulse generation circuit 35₁<Τ₂In this case, the high / low switching signal is set to high level and τ₁> Τ₂In this case, the high / low switching signal is set to low level.
[0035]
The selection circuit 37 selects and outputs one of the output signal of the PWM circuit 31 and the output signal of the forced pulse generation circuit 35. When the output signal of the forced pulse generation circuit 35 is selected, the polarity of the output pulse is determined according to the high / low switching signal. That is, when the high / low switching signal is at a high level, the selection circuit 37 outputs a high level output pulse. On the other hand, when the high / low switching signal is at a low level, the selection circuit 37 outputs an output pulse at a low level.
[0036]
As the low-pass filter 33, a CR-type low-pass filter in which a resistor and a capacitor are combined is used in a predetermined number of stages. In the present embodiment, a two-stage low-pass filter including resistors R1 and R2 and capacitors C1 and C2 is used.
[0037]
Next, the operation of the DAC according to the present embodiment will be described with reference to FIGS.
First, the increase mode shown in FIG. 6 will be described.
Before the predetermined change in the pulse width, the control unit 34 determines that the pulse width τ₁Stationary pulse P_EA control signal is supplied to the PWM circuit 31 so as to generate. Stationary pulse P generated by the PWM circuit 31_EIs input to the input terminal E of the AND circuit 38 included in the selection circuit 37. Further, the control unit 34 determines the pulse width τ before and after the predetermined change.₁, Τ₂Settling period T corresponding to the value of_SIs obtained from the lookup table 36 and the settling period T_SAnd pulse width τ before and after the transition period₁, Τ₂Are supplied to the forced pulse generation circuit 35.
[0038]
At this time, since the control unit 34 has not generated an output value change trigger pulse, the forced pulse generation circuit 35 has not output a forced pulse. Therefore, the selection circuit 37 has a steady pulse P output from the PWM circuit 31._ESelect to output. Stationary pulse P_EIs smoothed by the low-pass filter 33 and the analog output voltage V_OUTThe value of V₁become.
[0039]
Upon a predetermined change in the pulse width, the control unit 34 generates an output value change trigger pulse. In response to this, the forced pulse generation circuit 35 responds to the settling period T._SForced pulse P that goes high during_FGIs supplied to the inverting input terminal F of the AND circuit 38 and the input terminal G of the AND circuit 39 included in the selection circuit 37. Further, the forced pulse generation circuit 35 has a pulse width τ before a predetermined change.₁And the pulse width τ after a predetermined change₂And the value of τ₁<Τ₂In this case, it is determined that the mode is the increase mode, and the high / low switching signal is set to the high level. Therefore, the OR circuit 40 included in the selection circuit 37 outputs a high level output pulse P during the settling period._ZIs output. Output pulse P_ZIs smoothed by the low-pass filter 33 and the analog output voltage V_OUTRises rapidly.
[0040]
Settling period T_SAfter the elapse of time, the control unit 34 determines the pulse width τ at a constant period T.₂Stationary pulse P_EA control signal is supplied to the PWM circuit 31 so as to generate. Stationary pulse P generated by the PWM circuit 31_EIs input to the input terminal E of the AND circuit 38 included in the selection circuit 37.
[0041]
At this time, the forced pulse generation circuit 35 has finished outputting the forced pulse, so that the selection circuit 37 outputs the steady pulse P output from the PWM circuit 31._ESelect to output. Stationary pulse P_EIs smoothed by the low-pass filter 33 and the analog output voltage V_OUTThe value of V₂become.
[0042]
Next, the decrease mode shown in FIG. 7 will be described.
Before the predetermined change in the pulse width, the control unit 34 determines that the pulse width τ₂Stationary pulse P_EA control signal is supplied to the PWM circuit 31 so as to generate. Stationary pulse P generated by the PWM circuit 31_EIs input to the input terminal E of the AND circuit 38 included in the selection circuit 37. Further, the control unit 34 determines the pulse width τ before and after the predetermined change.₂, Τ_ThreeSettling period T corresponding to the value of_SIs obtained from the lookup table 36 and the settling period T_SAnd pulse width τ before and after the transition period₂, Τ_ThreeAre supplied to the forced pulse generation circuit 35.
[0043]
At this time, since the control unit 34 has not generated an output value change trigger pulse, the forced pulse generation circuit 35 has not output a forced pulse. Therefore, the selection circuit 37 has a steady pulse P output from the PWM circuit 31._ESelect to output. Stationary pulse P_EIs smoothed by the low-pass filter 33 and the analog output voltage V_OUTThe value of V₂become.
[0044]
Upon a predetermined change in the pulse width, the control unit 34 generates an output value change trigger pulse. In response to this, the forced pulse generation circuit 35 responds to the settling period T._SForced pulse P that goes high during_FGIs supplied to the inverting input terminal F of the AND circuit 38 and the input terminal G of the AND circuit 39 included in the selection circuit 37. Further, the forced pulse generation circuit 35 has a pulse width τ before a predetermined change.₂And the pulse width τ after a predetermined change_ThreeAnd the value of τ₂> Τ_ThreeIn this case, it is determined that the mode is the decrease mode, and the high / low switching signal is set to the low level. Therefore, the OR circuit 40 included in the selection circuit 37 outputs a low-level output pulse P during the settling period._ZIs output. Output pulse P_ZIs smoothed by the low-pass filter 33 and the analog output voltage V_OUTFalls rapidly.
[0045]
Settling period T_SAfter the elapse of time, the control unit 34 determines the pulse width τ at a constant period T._ThreeStationary pulse P_EA control signal is supplied to the PWM circuit 31 so as to generate. Stationary pulse P generated by the PWM circuit 31_EIs input to the input terminal E of the AND circuit 38 included in the selection circuit 37.
[0046]
At this time, the forced pulse generation circuit 35 has finished outputting the forced pulse, so that the selection circuit 37 outputs the steady pulse P output from the PWM circuit 31._ESelect to output. Stationary pulse P_EIs smoothed by the low-pass filter 33 and the analog output voltage V_OUTThe value of V_Threebecome.
[0047]
In this way, by supplying a high level or low level signal to the low-pass filter 33 for a predetermined period in place of the output signal of the PWM circuit 31 in the transition period in which the analog output voltage must be suddenly increased or decreased, The response time of the DAC can be shortened.
[0048]
Next, a modification of the third embodiment of the present invention will be described. In this modification, instead of using a preset settling period value, the DAC output voltage is converted back to digital data using an ADC (analog / digital conversion circuit) and compared with the input data. Thus, the settling period is determined.
[0049]
FIG. 8 shows the configuration of a DAC according to a modification of the third embodiment of the present invention. As shown in FIG. 8, the pulse generation control means 42 in the DAC includes an analog output voltage V V in addition to the control unit 44, the forced pulse generation circuit 45, and the selection circuit 37._OUTIs further converted to a digital signal, and a comparator 47 that provides a settling period by comparing data (output value) output from the ADC 46 with input data (target value).
[0050]
The comparator 47 outputs a high level comparison signal when the output value is smaller than the target value, and outputs a low level comparison signal when the output value is larger than the target value. The comparison operation in the comparator 47 may be performed based on a predetermined number of upper bits in the output value.
[0051]
First, the operation of the DAC in the increase mode will be described.
Before the predetermined change in the pulse width, the control unit 44 determines that the pulse width τ₁A control signal is supplied to the PWM circuit 31 so as to generate a steady pulse. The steady pulse generated by the PWM circuit 31 is input to the selection circuit 37. At this time, the control unit 44 has not generated an output value change trigger pulse, and therefore the forced pulse generation circuit 45 has not output a forced pulse. Therefore, the selection circuit 37 outputs the steady pulse input from the PWM circuit 31. This steady pulse is smoothed by the low-pass filter 33 and the analog output voltage V_OUTThe value of V₁become.
[0052]
Upon a predetermined change in the pulse width, the control unit 44 generates an output value change trigger pulse. When the output value is smaller than the target value, the comparator 47 outputs a high level comparison signal. The compulsory pulse generation circuit 45 generates a compulsory pulse and supplies it to the selection circuit 37 during a settling period in which the comparison signal is at a high level after the output value change trigger pulse is supplied. The forced pulse generation circuit 45 sets the high / low switching signal to a high level. Therefore, the selection circuit 37 outputs an output pulse that becomes high level during the settling period. The output pulse is smoothed by the low-pass filter 33 and the analog output voltage V_OUTRises rapidly.
[0053]
After the settling period has elapsed, the control unit 44 determines that the pulse width τ has a constant period T.₂A control signal is supplied to the PWM circuit 31 so as to generate a steady pulse. The steady pulse generated by the PWM circuit 31 is input to the selection circuit 37. At this time, the forced pulse generation circuit 45 has finished outputting the forced pulse, and therefore the selection circuit 37 outputs the steady pulse input from the PWM circuit 31. This steady pulse is smoothed by the low-pass filter 33 and the analog output voltage V_OUTThe value of V₂become.
[0054]
Next, the operation of the DAC in the decrease mode will be described.
Before the predetermined change in the pulse width, the control unit 44 determines that the pulse width τ₂A control signal is supplied to the PWM circuit 31 so as to generate a steady pulse. The steady pulse generated by the PWM circuit 31 is input to the selection circuit 37. At this time, the control unit 44 has not generated an output value change trigger pulse, and therefore the forced pulse generation circuit 45 has not output a forced pulse. Therefore, the selection circuit 37 outputs the steady pulse input from the PWM circuit 31. This steady pulse is smoothed by the low-pass filter 33 and the analog output voltage V_OUTThe value of V₂become.
[0055]
Upon a predetermined change in the pulse width, the control unit 44 generates an output value change trigger pulse. When the output value is larger than the target value, the comparator 47 outputs a low level comparison signal. The compulsory pulse generation circuit 45 generates a compulsory pulse and supplies it to the selection circuit 37 during a settling period in which the comparison signal is at a low level after the output value change trigger pulse is supplied. The forced pulse generation circuit 45 sets the high / low switching signal to a low level. Therefore, the selection circuit 37 outputs a low level output pulse during the settling period. The output pulse is smoothed by the low-pass filter 33 and the analog output voltage V_OUTFalls rapidly.
[0056]
Settling period T_SAfter the elapse of time, the control unit 44 determines that the pulse width τ has a constant period T._ThreeA control signal is supplied to the PWM circuit 31 so as to generate a steady pulse. The steady pulse generated by the PWM circuit 31 is input to the selection circuit 37. At this time, the forced pulse generation circuit 45 has finished outputting the forced pulse, and therefore the selection circuit 37 outputs the steady pulse input from the PWM circuit 31. The steady pulse is smoothed by the low-pass filter 33 and the analog output voltage V_OUTThe value of V_Threebecome.
[0057]
In this way, the settling period is set by comparing the output value with the target value, and in a transition period in which the analog output voltage must be rapidly increased or decreased, the output signal of the PWM circuit 31 is changed to a high level for a predetermined period. By supplying a low or high level signal to the low pass filter 33, the response time of the DAC can be shortened.
[0058]
Note that the method of setting the settling period using the ADC 46 and the comparator 47 can be applied not only to the third embodiment but also to the first embodiment or the second embodiment.
[0059]
【The invention's effect】
As described above, according to the present invention, in a DAC using PWM, it is possible to shorten the response time while keeping the output waveform stable.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a DAC according to a first embodiment of the present invention.
FIG. 2 is a timing chart showing signal waveforms of respective parts of the DAC according to the first embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a DAC according to a second embodiment of the present invention.
FIG. 4 is a timing chart showing signal waveforms of respective parts of the DAC according to the second embodiment of the present invention.
FIG. 5 is a block diagram showing a configuration of a DAC according to a third embodiment of the present invention.
FIG. 6 is a timing chart showing signal waveforms of respective parts in a DAC increase mode according to a third embodiment of the present invention.
FIG. 7 is a timing chart showing signal waveforms of respective parts in a DAC reduction mode according to a third embodiment of the present invention.
FIG. 8 is a block diagram showing a configuration of a DAC according to a modification of the third embodiment of the present invention.
[Explanation of symbols]
11, 21, 31 PWM circuit
12, 22, 32, 42 Pulse generation control means
13, 23, 33 Low-pass filter
14, 24, 34, 44 Control unit
15 OR circuit
16, 26, 36 Look-up table
25 AND circuit
35, 45 Forced pulse generation circuit
37 selection circuit
46 ADC
47 Comparator

Claims (4)

A pulse width modulation circuit that modulates the pulse width of the output signal in accordance with the control signal;
A control signal to be supplied to the pulse width modulation circuit is generated based on input data, and the pulse width is changed when the absolute value of the change amount of the pulse width to be output by the pulse width modulation circuit exceeds a predetermined value. Pulse generation control means for replacing the output signal of the modulation circuit with a high level or low level signal in the settling period;
A low-pass filter that smoothes the signal output from the pulse generation control means and generates an analog output voltage;
An analog / digital conversion circuit for analog / digital conversion of the analog output voltage generated by the low-pass filter;
A comparator that sets the settling period by comparing data output from the analog / digital conversion circuit with input data;
A digital / analog conversion circuit comprising: The pulse generation control means is
A control unit that outputs a high-level signal in the settling period when the amount of change in pulse width to be output by the pulse width modulation circuit is positive and the value exceeds a predetermined value;
An OR circuit for obtaining a logical sum of the output signal of the pulse width modulation circuit and the output signal of the control unit;
Including, claim 1 Symbol placement of digital / analog converter. The pulse generation control means is
A control unit that outputs a low level signal in the settling period when the amount of change in pulse width to be output by the pulse width modulation circuit is negative and the absolute value thereof exceeds a predetermined value;
An AND circuit for obtaining a logical product of the output signal of the pulse width modulation circuit and the output signal of the control unit;
Including, claim 1 Symbol placement of digital / analog converter. The pulse generation control means is
Based on the amount of change in pulse width to be output by the pulse width modulation circuit, a control unit that outputs a high level or low level signal;
A selection circuit that selects an output signal of the control unit in the settling period and selects an output signal of the pulse width modulation circuit in the other period;
Including, claim 1 Symbol placement of digital / analog converter.

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