JP3991588B2 - Method for manufacturing printed wiring board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a printed wiring board on which surface-mounted components, particularly electronic components such as bare chips, are mounted.
[0002]
[Prior art]
Conventional patterning methods for printed wiring boards can be broadly divided into subtractive methods and additive methods. Subtractive methods are frequently used as patterning methods for printed wiring boards because of their high mass productivity and reduced manufacturing costs. ing.
[0003]
FIG. 8 shows a manufacturing process procedure for pattern formation by the subtractive method.
[0004]
After forming an etching resist 4 on the surface of a copper-clad laminate 1 (see FIG. 8A) made of a base material 2 and copper foil 3 (see FIG. 8B), cupric chloride, etc. After removing unnecessary copper foil with the etching solution to form a predetermined pattern 5 (see FIG. 8C), the etching resist is removed to complete pattern formation (see FIG. 8D). .
[0005]
Then, as shown in FIG. 9A, the solder resist 14 is applied leaving the component mounting portion on the surface of the wiring board.
[0006]
Finally, as a finishing process, as shown in FIG. 9B, an electroless nickel plating layer 6 is formed on a pattern to be a connection electrode, and an electroless gold plating layer 7 is further formed thereon, as shown in FIG. .
[0007]
[Problems to be solved by the invention]
However, in the above-described conventional manufacturing method, as shown in FIG. 5A, the solder resist 14 may not be deposited 15 or voids 16 may occur due to printing blur in the pattern gap. In particular, it will become more prominent as fine patterning progresses and the pattern gap becomes narrower.
[0008]
In recent years, mounting of electronic components for surface mounting onto a printed wiring board has increased by a mounting method called flip chip mounting as shown in FIG. 6A, and the connection reliability is improved in the gap between the bare chip 8 and the substrate 10. Therefore, the sealing resin 17 is often injected.
[0009]
In this implantation process, as the pitch of the pattern is narrowed, how to eliminate the void entrainment and to be implanted quickly becomes a big problem. In the conventional substrate, it is difficult to suppress the generation of voids 18.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the present invention has the following configuration.
[0011]
According to a first aspect of the present invention includes the steps of selectively forming a plating resist on the copper-clad laminate, and forming the electroless nickel plating layer on the non-formation portion of the plating resist, the plating resist An insulating substrate including a step of peeling, a step of etching a portion of the copper foil where the electrolytic nickel plating layer is not formed to form a wiring substrate having a conductive pattern, and a space between the conductive pattern and the electrolytic nickel plating layer A process of forming an insulating resin layer on the entire upper surface, and polishing the insulating resin layer smoothly by belt sander polishing or buffing until the surface of the electrolytic nickel plating layer is exposed, and simultaneously polishing the surface of the electrolytic nickel plating layer A step of forming a mark, a step of forming an electroless nickel plating layer on the electrolytic nickel plating layer having a polishing mark on the surface, This is a method of manufacturing a printed wiring board including a step of forming an electroless gold plating layer on an electroless nickel plating layer. With this, when forming a solder resist, the solder resist is formed in the pattern gap as in the prior art. It can be applied thinly and evenly without any adhesion or voids. Further, in order to improve the connection reliability in the gap between the component and the substrate, there is an effect that the void can be prevented from being entrained even when the sealing resin is injected.
[0012]
The present invention, the metal conductive layer is a layer called forming by electrolytic gold plating on the electroless nickel plating, or electroless nickel plating, thereby, to solder joining metal conductive layer as a connection electrode, a metal conductive Since the nickel film that is the layer does not contain phosphorus, high solder joint strength can be maintained, and electrolytic gold plating has no pinholes compared to electroless gold plating with many pinholes. Since a dense layer is formed, corrosion does not occur, and an effect that long-term storage is good is obtained.
[0013]
The present invention has referred to as performing electroless gold plating on the exposed surface of the metal conductive layer, thereby, since the lead wire for current supply required for the electrolytic gold plating is not required, wire The effect of increasing the density and the component mounting density can be obtained.
[0014]
The present invention has referred to as performed on the surface of the metal conductive layer exposed electroless nickel plating immediately before the electroless gold plating, thereby, the metal conductive generated when polishing smooth the insulating resin layer The effect that the grinding | polishing trace of a layer can be relieve | moderated and the adhesion | attachment of a gold plating layer can be improved is acquired.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
1 and 2 are manufacturing process diagrams of the printed wiring board according to Embodiment 1 of the present invention.
[0016]
1 and 2, in this embodiment, a copper-clad laminate obtained by attaching copper foil 3 as a conductive layer on both surfaces of a glass epoxy substrate, for example, is used as the substrate 10 as the wiring substrate 10 (FIG. 1). 1 (A)).
[0017]
A plating resist 11 is formed on the wiring substrate 10 by a photo process (see FIG. 1B).
[0018]
Next, an electrolytic nickel plating layer 12 having a rectangular cross section as a metal conductive layer is formed in a portion where the plating resist 11 is not formed (see FIG. 1C). Then, the plating resist 11 is peeled off with a solution such as sodium hydroxide (see FIG. 1D).
[0019]
Next, using the electrolytic nickel plating layer 12 as an etching resist, unnecessary copper foil is removed with an alkaline etching solution mainly composed of copper ammonium complex ions to form a predetermined pattern 5 (see FIG. 2E). .
[0020]
Next, the insulating resin layer 13 is formed on the surface of the wiring substrate 10. As this insulating resin material, a thermosetting epoxy resin is used, applied with a screen printing machine, a curtain coater, a slot coater, etc., and then dried in the touch in a thermosetting furnace. Similarly, an insulating resin material is applied to the back side of the resin and cured at the same time in a thermosetting furnace (see FIG. 2 (F)).
[0021]
Next, the cured insulating resin layer 13 is polished. The polishing apparatus using, for example, a belt sander or a buffing machine, electrolytic nickel plating layer 12 is smoothly polished until surface exposed (see FIG. 2 (G)). Thereafter, if necessary, a solder resist may be applied to the surface of the wiring board leaving a component mounting portion (FIG. 5B).
[0022]
Finally, as a finishing treatment, a gold plating treatment is performed on a portion where the electrolytic nickel plating layer is exposed, such as a component mounting portion. This gold plating layer 7 is performed by electroless plating, and the surface of the exposed electrolytic nickel plating layer is sufficiently activated by combining chemical polishing such as acid treatment, alkali treatment, and cyan treatment with mechanical polishing such as buffing. Then, gold plating is performed (see FIG. 2H). In addition, when the polishing performed in FIG. 2G has a large polishing mark on the surface of the electrolytic nickel plating layer, or in order to improve the adhesion of the gold plating layer, the electroless nickel plating layer is replaced with the electrolytic nickel plating layer immediately before the gold plating. May be implemented above.
[0023]
<Advantages of this embodiment>
As described above, according to the configuration and the manufacturing method of the printed wiring board in the present embodiment, the following effects can be obtained.
[0024]
(1) An underfill material can be easily injected when a bare chip is flip-chip mounted on a substrate, and voids are not generated (FIG. 6B).
[0025]
In the present embodiment, since the substrate surface is flattened by the insulating resin layer 13, the generation of voids is remarkably reduced, and the implantation time is greatly shortened. In addition, in the case of the pressure welding method that maintains the electrical connection between the bare chip and the substrate using the curing shrinkage of the resin instead of this sealing resin, the resin is a film in addition to the paste, or the resin contains conductive particles The same effect can be obtained when the one not included is used.
[0026]
(2) Even when the solder resist is formed on the insulating resin layer 13 as shown in the above embodiment, the solder resist 14 is not deposited 15 or the void 16 is generated due to the printing blur in the pattern gap, which is a problem of the conventional substrate. There is no.
[0027]
In this embodiment, since the substrate is flattened by the insulating resin layer 13, the solder resist can be thinly and uniformly applied as well as the occurrence of unattached 15 and voids 16.
[0028]
(3) The width on the pattern necessary for component mounting can be secured, and the tolerance for positional deviation during mounting is increased. The upper width of the pattern for mounting the component is determined by the width of the electrolytic nickel plating layer 12, and this width is controlled by the pattern width of the mask film used for the photo process, and depends on the etching state of the pattern 5. Therefore, a constant and stable pattern width can be obtained.
[0029]
(4) Since the substrate is flat, components to be mounted do not fall off the substrate pattern and do not tilt. As shown in FIGS. 7 (a) and 7 (b), if the substrate is a conventional substrate, the bump 9 as a connection electrode with the substrate disposed on the bare chip 8 is displaced from the pattern 5 by the pressure at the time of mounting, and the bare chip is inclined. Problems such as poor contact occurred. As shown in FIGS. 7C and 7D, in this embodiment, even if the bump 9 is disposed at the end of the electrolytic nickel plating layer 12, the bare chip 8 is inclined because it is flattened by the insulating resin layer 13. Connection is maintained.
[0030]
(5) Since the nickel plating performed as the finishing surface treatment is formed by electrolytic plating, the nickel coating does not contain phosphorus, so that the solder joint strength is improved. For high-density substrates and bare chip mounting substrates, nickel and gold plating are frequently used as finishing surface treatments. There are two types of nickel and gold plating: electroplating and electroless plating. In the case of electrolytic plating, a lead wire is required for energization, but a high-density board does not have enough space to accommodate the lead wire. Many are due to plating. However, since electroless nickel plating uses sodium hypophosphite as a reducing agent, the nickel film necessarily contains phosphorus. When the portion of the nickel plating layer containing phosphorus is soldered as a connection electrode, an alloy layer is formed by tin and nickel in the solder, and a layer having a high phosphorus concentration is formed at the joint interface. It has been found that the formation of this high phosphorus concentration layer reduces the solder joint strength. Since the connection electrode portion of the substrate fabricated according to this embodiment is formed by electrolytic nickel plating, it does not contain phosphorus and can maintain high solder joint strength. Therefore, it is effective when the surface-mounted component is connected to the substrate with solder, or when the substrate is used as a bare chip mounting substrate and BGA mounting is performed on the mother substrate with solder balls.
[0031]
(6) Since the build-up wiring board, which is widely used as a high-density board or bare chip board, forms a wiring pattern and a component mounting pattern by a copper plating layer deposited on an insulating resin, a copper foil peel Since the strength and the pull strength are low, component drop-off from the board is a problem. Since the side surface of the copper foil is covered with the insulating resin layer, the peel strength and pull strength of the substrate according to the present embodiment are greatly improved.
[0032]
(Embodiment 2)
3 and 4 are manufacturing process diagrams of the printed wiring board according to Embodiment 2 of the present invention.
[0033]
In this embodiment, the plating resist 11 is formed by a photo process up to FIG. 3B as in FIG. 1B of the first embodiment (see FIG. 3B).
[0034]
Next, an electrolytic nickel plating layer 12 is formed on a portion where the plating resist 11 is not formed, and an electrolytic gold plating layer 19 is further formed thereon (see FIG. 3C). Then, the plating resist 11 is peeled off with a solution such as sodium hydroxide (see FIG. 3D).
[0035]
Next, using the electrolytic nickel plating layer 12 and the electrolytic gold plating layer 19 as an etching resist, unnecessary copper foil is removed with an alkaline etching solution mainly composed of copper ammonium complex ions to form a predetermined pattern 5 (FIG. 5). 4 (E)). Thereafter, if necessary, a solder resist may be applied leaving a component mounting portion on the surface of the wiring board.
[0036]
Finally, as a finishing treatment, treatment is performed with a water-soluble heat-resistant preflux 20 for the purpose of rust-proofing the exposed copper portion on the side surface of the pattern 5 (see FIG. 4F). This water-soluble heat-resistant preflux 20 is mainly composed of an alkylbenzimidazole derivative, and the rust preventive component is chemically adsorbed only on the copper surface, and does not adsorb and react with the gold plating part or the solder resist.
[0037]
<Advantages of this embodiment>
(1) Similar to the first embodiment, it is possible to secure a pattern width necessary for component mounting, and a tolerance for mounting displacement is increased.
[0038]
(2) Since the nickel plating layer used as a connection electrode is formed by electroplating similarly to Embodiment 1, the board by this embodiment does not contain phosphorus in a nickel layer, Therefore Solder joint strength improves. . Further, the gold plating on the nickel layer is also by electrolytic plating, and a dense layer without pinholes is formed, so that long-term storage is good.
[0039]
Conventionally, gold plating is often performed by electroless plating, and therefore there are many pinholes in the gold plating layer. In this pinhole portion, a local battery is formed by contact between gold and nickel, and a very large potential difference is generated between gold and nickel, causing corrosion. Since this corrosion progresses with time, it cannot be stored for a long time.
[0040]
In addition, the nickel layer is exposed on the surface of the pinhole portion existing in the gold plating layer, but since nickel is combined with the water-soluble heat-resistant preflux component of the finishing treatment, not only the copper surface but also nickel plating and gold plating An organic film is also formed on the connection electrode portion that has been subjected to. When an organic film is formed on the connection electrode part, there is a big problem such as difficulty in wire bonding connection at the time of bare chip mounting. However, in this embodiment, the gold plating layer is formed by electrolytic plating. In addition to forming a dense layer, the thickness of the gold plating can be easily controlled by the plating conditions.
[0041]
【The invention's effect】
As described above, according to the present invention, the metal conductive layer having a rectangular cross section is formed on the conductor pattern formed on the insulating substrate, and is formed on the insulating substrate between the conductor pattern and the metal conductive layer. When the solder resist is formed by a printed wiring board formed substantially flat with the same thickness as the metal conductive layer, the insulating resin layer is formed in the pattern gap as in the prior art. Solder resist is not deposited and voids are not generated and can be applied thinly and uniformly. Further, in order to improve the connection reliability in the gap between the component and the substrate, it is possible to realize a highly reliable printed wiring board that can prevent voids from being entrained even when a sealing resin is injected.
[Brief description of the drawings]
1 is a process cross-sectional view illustrating a method for manufacturing a printed wiring board according to Embodiment 1 of the present invention. FIG. 2 is a process cross-sectional view illustrating a method for manufacturing a printed wiring board according to Embodiment 1. FIG. 4 is a process cross-sectional view showing a method for manufacturing a printed wiring board according to Embodiment 2 of the present invention. FIG. 4 is a process cross-sectional view showing a method for manufacturing a printed wiring board according to Embodiment 2. FIG. FIG. 6 is a cross-sectional view showing a solder resist formation state and a gold plating treatment state in Embodiment 1 of the present invention. FIG. 6A is a view showing a mounting state of a conventional electronic component. Sectional view (b) Sectional view showing the mounting state of the electronic component according to the first embodiment of the present invention. FIG. 7 is a sectional view for comparing the mounting state of the electronic component according to the first embodiment of the present invention. Traditional print Cross-sectional view showing a method for manufacturing a wiring board [FIG. 9] Cross-sectional view showing a conventional method for manufacturing a printed wiring board [Explanation of symbols]
1 Copper-clad laminate 2 Base material 3 Copper foil (conductor layer)
4 Etching resist 5 Pattern 6 Electroless nickel plating layer 7 Electroless gold plating layer 8 Bare chip 9 Bump 10 Wiring board 11 Plating resist 12 Electrolytic nickel plating layer 13 Insulating resin layer 14 Solder resist 15 Solder resist not attached 16 In solder resist Void 17 Sealing resin 18 Void in sealing resin 19 Electrolytic gold plating layer 20 Water-soluble heat-resistant preflux

Claims (1)

A step of selectively forming a plating resist on a copper clad laminate, a step of forming an electrolytic nickel plating layer on a portion where the plating resist is not formed, a step of peeling off the plating resist, and forming the electrolytic nickel plating layer Etching a portion of the copper foil that has not been formed to form a wiring board having a conductor pattern; and forming an insulating resin layer on the entire surface of the insulating substrate including between the conductor pattern and the electrolytic nickel plating layer; Polishing the insulating resin layer smoothly by belt sander polishing or buffing until the surface of the electrolytic nickel plating layer is exposed, and simultaneously forming a polishing mark on the surface of the electrolytic nickel plating layer, and having a polishing mark on the surface Forming an electroless nickel plating layer on the electrolytic nickel plating layer; and forming an electroless nickel plating layer on the electroless nickel plating layer. Method for manufacturing a printed wiring board comprising the steps of forming a Kaikin plating layer.

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