JP3991413B2 - Liquid crystal display device and driving circuit thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device (hereinafter referred to as an LCD (Liquid Crystal Display)) and a driving circuit thereof, and in particular, an active device that sequentially selects a plurality of liquid crystal cells (pixels) arranged two-dimensionally in rows and columns. The present invention relates to a matrix type LCD and its driving circuit.
[0002]
[Prior art]
In the LCD panel, when the number of pixels calculated from the effective period of the video signal to be displayed is less than the number of pixels of the LCD panel, the blanking signal is displayed as it is on the pixels where no video is displayed. This is a problem that may occur when an image signal having undergone pixel number conversion by a scan converter or the like is displayed on the LCD panel in order to display a signal in a format different from the panel's own format.
[0003]
This is because when the format conversion is performed by the scan converter, the format conversion ratio is often set to a simple integer ratio in order to simplify the interpolation operation. For example, when an 800 dot × 600 dot SVGA (Super Video Graphics Array) format is changed to a 1024 dot × 768 dot XGA (eXtended Graphics Array) format, the conversion ratio is set to 4: 5 and converted to 1000 dots × 750 dots. Is done.
[0004]
In this way, when the video signal format-converted to 1000 dots × 750 dots is displayed on the LCD panel having the number of pixels of 1024 dots × 768 dots, as shown in FIG. 13, the images are displayed 12 dots at the left and right of the screen and 9 dots at the top and bottom. There is a place where there is not enough signal. At this time, the pedestal signal of the blanking period is displayed as it is on the peripheral frame portion of the screen.
[0005]
[Problems to be solved by the invention]
However, the level of the pedestal signal displayed on the LCD panel fluctuates in conjunction with the adjustment of image quality such as bright, gain, gamma, and limiter in the signal processing system. Then, when this video signal is projected by the projector, the surroundings of the video become brighter or darker together according to these adjustments. This is undesirable in appearance.
[0006]
The present invention has been made in view of the above problems, and the object of the present invention is to adjust the image quality such as brightness, gain, gamma, and limiter when the level of the pedestal signal displayed on the LCD panel during the blanking period. It is an object of the present invention to provide an LCD and its driving circuit which are not affected.
[0007]
[Means for Solving the Problems]
The LCD and its driving circuit according to the present invention have a signal processing system for performing various image quality adjustments on an input video signal, and drive an LCD panel (display unit) based on the video signal that has passed through this signal processing system. When the number of pixels calculated from the effective period of the video signal is less than the number of pixels of the LCD panel, the display level of the blanking period displayed on the LCD panel is fixed to a certain level , have a frame processing block for outputting switching between the video signal and the frame display level signal in response to a select signal generated by 1 dot units based on the frame display range data in the last stage of the signal processing system,
N processing systems in which the video signal is demultiplexed 1: n (n is an integer of 2 or more), and the signal processing system performs parallel processing using a 1 / n divided clock of a master clock. The frame processing block performs a switching process according to the select signal given to each of the n processing systems,
The select signal includes a decoding value of each count value of the H counter that performs a counting operation with a 1 / n frequency-divided clock of a master clock and a V counter that uses a vertical synchronizing signal as a reset pulse, and the frame. It is generated based on the comparison result with the coefficient data indicating the display range, and the comparison result between the count value of the H counter and the upper bit of the coefficient data is set to the 1 / n according to the value of the lower bit of the coefficient data. The output is provided with an offset of one stage of the divided clock .
[0008]
A frame processing block for fixing the display level of the blanking period to a fixed level at the last stage of the signal processing system that performs image quality adjustment such as gain adjustment, brightness adjustment, gamma adjustment, and limit adjustment in the LCD and its driving circuit having the above configuration By placing, the display level of the frame is not affected by the result of any other signal processing. Therefore, even if various image quality adjustments are performed, the display level of the frame is always fixed at a constant level (for example, an absolute black level) without changing in conjunction with the adjustment.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0010]
FIG. 1 is a block diagram showing an outline of a basic configuration of an LCD display system according to the present invention. In FIG. 1, the timing generator 11 performs all timing control of this system. That is, the timing generator 11 generates a master clock mclk and various timing pulses based on the input horizontal synchronization signal hd and vertical synchronization signal vd, and performs timing control by supplying these to each block.
[0011]
Analog video signals (R-in, G-in, B-in) of R (red), G (green), and B (blue) are A / D converted by A / D converters 12R, 12G, and 12B, and After being demultiplexed at 1: 2, it is input to the driver IC 13 as 8-bit × 2 digital data. The driver IC 13 performs signal processing such as gain adjustment, bright adjustment, gamma adjustment, and limiter adjustment on the input digital data with 10 bits. A specific configuration inside the driver IC 13 will be described later.
[0012]
The driver IC 13 outputs 10 bits × 2 digital data for each color of R, G, and B after performing internal arithmetic processing and various signal processing. These digital data are multiplexed by D / A converters 14R, 14G, and 14B, and D / A converted to be output as R, G, and B analog video signals.
[0013]
The analog video signals of R, G, and B are amplified and inverted by the analog drivers 15R, 15G, and 15B, processed into a form that can be displayed on the LCD panels 16R, 16G, and 16B, and further subjected to sample / hold processing. Then, the video is displayed by being input to the LCD panels 16R, 16G, and 16B. Here, although not particularly limited, description will be made assuming that the number of output channels of the analog drivers 15R, 15G, and 15B is 6, and the number of signal lines of the LCD panels 16R, 16G, and 16B is 6.
[0014]
FIG. 2 is a block diagram showing an example of a specific configuration inside the driver IC 13 which is a feature of the present invention. As described above, the 8-bit × 2 R / G / B digital data R1in, R2in / G1in, G2in / B1in, and B2in demultiplexed 1: 2 are input to the driver IC 13 as described above. .
[0015]
The driver IC 13 is not particularly limited, but the data to be set at the time of arithmetic processing is 3-wire serial data sctl, sdat, sclk, and these data are taken in via a serial I / F (interface) 21. Will be described. Further, the master clock mclk of the entire system is divided by ½ by a D-type flip-flop (hereinafter referred to as D-FF) 22, and this half-divided clock (½ clk) is used to divide the internal clock. The arithmetic processing is configured to be processed in parallel.
[0016]
The R digital data R1in and R2in are gain adjusted by the gain block 23R, bright adjusted by the bright block 24R, gamma adjusted by the gamma block 25R, limit adjusted by the limit block 26, and then supplied to the black frame processing block 27R. The The same applies to the G digital data G1in and G2in and the B digital data B1in and B2in.
[0017]
Here, the coefficients used in each arithmetic processing block are set based on serial data sctl, sdat, and sclk input from the outside of the IC via the serial I / F 21. Also, the black frame processing blocks 27R, 27G, and 27B are placed at the last stage of the signal processing system inside the driver IC 13 because the black level of the black frame is always influenced by any other signal processing result. This is because it is desirable that the black level be fixed. In this example, the display level is fixed to the black level. However, the display level is not limited to this and may be other display levels.
[0018]
The timing generator 28 receives the positive phase output Q of the D-FF 22, that is, the clock ½ clk obtained by dividing the master clock mclk by ½, the horizontal synchronization signal hd, and the vertical synchronization signal vd, and the serial I / F 21. To the black frame display range coefficient. The timing generator 28 generates a select pulse for selecting the display range of the black frame from the decode value of the internal counter and the display range coefficient. This select pulse is “1” in the black frame display range and “0” in the video signal display range.
[0019]
The select pulse output from the timing generator 28 is input to the black frame processing blocks 27R, 27G, and 27B. In the black frame processing blocks 27R, 27G, and 27B, the black frame and black level coefficients of the video signal are selected and output using a select pulse. As a result, the level of the pedestal signal during the blanking period of the video signal output from the driver IC 13 is influenced by the adjustment level of image quality adjustment such as gain adjustment, bright adjustment, gamma adjustment, and limit adjustment, as shown in FIG. Without being fixed at a certain black level.
[0020]
Next, specific examples of the black frame processing blocks 27R, 27G, and 27B and the timing generator 28 will be described. In the black frame processing blocks 27R, 27G, and 27B, black frame processing is performed by switching between input data (video signal) and black frame black level data (coefficient fb) by a select pulse generated by the timing generator 28.
[0021]
The display range of the black frame is set based on the coefficients h1 and h2 and the coefficients v1 and v2 given to the timing generator 28. The relationship between these coefficients is h1 <h2 and v1 <v2. As shown in the waveform diagram of FIG. 4, the first edge of the horizontal synchronizing signal hd and the vertical synchronizing signal vd, that is, the negative polarity input, stands. For a falling edge or positive polarity input, the rising edge is set as a reference.
[0022]
FIG. 5 is a block diagram showing an example of the configuration of the black frame processing block. Here, the R black frame processing block 27R will be described as an example, but the G / B black frame processing block 27G / 27B has the same configuration.
[0023]
As is clear from FIG. 5, the black frame processing block 27R is provided with two processing blocks 27Re and 27Ro of an even dot processing system and an odd dot processing system. The processing blocks 27Re and 27Ro are selectors 29e and 29o for switching between input data (video signal) and black frame black level data (coefficient fb) by a select pulse supplied from the timing generator 28. It consists of 10-bit flip-flops (FF) 30e and 30o that latch the data selected by 29e and 29o.
[0024]
The timing generator 28, which will be described in detail later, generates separate select pulses (even select pulses / odd select pulses) for the even dot processing system and the odd dot processing system. The selectors 29e and 29o select and output the input data (video signal) when these select pulses are “0” (“L” level), and when they are “1” (“H” level). Selects and outputs black level data (coefficient fb) of the black frame.
[0025]
FIG. 6 is a block diagram illustrating an example of the configuration of the timing generator 28. Although the coefficient and the number of bits of the counter are not particularly limited, here, the coefficient is assumed to be 11 bits, the H counter is assumed to be 10 bits, and the V counter is assumed to be 11 bits. The timing generator 28 generates a select pulse (even number select pulse / odd number select pulse) for switching the display range of the black frame by decoding the count values of the H counter 31 and the V counter 32.
[0026]
In FIG. 6, the H counter 31 counts at 1/2 clk using the horizontal synchronization signal hd as a reset pulse. Here, 1 / 2clk corresponds to a 1/2 frequency-divided clock of the master clock mclk, as is apparent from the timing chart of FIG. As a result, the H counter 31 counts the video signal in units of 2 dots. Therefore, in order to control the display range of the black frame in units of one dot, as described above, separate select pulses (even select pulses / even pulses are separately used for the even-numbered dot processing block 27Re and the odd-numbered dot processing block 27Re in the black frame processing block 27R. (Odd select pulse) is generated.
[0027]
Specifically, first, the comparators 33 and 34 compare the count value of the H counter 31 with the upper 10 bits of the coefficient (h1 or h2). At this time, the comparators 33 and 34 output “1” (“H” level) if the two values are the same, and output “0” (“L” level) otherwise. The comparison results of the comparators 33 and 34 are latched by the D-FFs 35 and 36.
[0028]
From this point, in order to generate select pulses for even dots, on the coefficient h1 side, the output a of the D-FF 35 is delayed by one clock by the D-FF 37, and the delayed output b is further reduced by 1 by the D-FF 38. Delayed output c is obtained with a delay of the clock. The timing relationship at this time is shown in the timing chart of FIG.
[0029]
In the timing charts of FIGS. 8 to 12 described below, waveforms a to k indicate the waveforms of the units a to k in FIG. 6 with a corresponding relationship. Similarly, on the coefficient h2 side, the output of the D-FF 36 is delayed by one clock at each of the D-FFs 39 and 40 connected in two stages to obtain a delayed output e for a total of two clocks.
[0030]
On the other hand, in order to generate a select pulse for odd dots, the output a of the D-FF 35 and the output b of the D-FF 37 are input to the selector 41, and these two inputs are supplied through a coefficient h1. Select based on LSB logic. In the selector 41, if the LSB logic of the coefficient h1 is “0”, that is, if the set value is an even number, the output a of the D-FF 35 is selected, and the selected output d is set via the D-FF 43, and the LSB logic is “1”. "In other words, if the coefficient is an odd number, the output b of the D-FF 37 is selected and set as the selected output d 'via the D-FF 43.
[0031]
Similarly, on the coefficient h2 side, each output of the D-FFs 36 and 39 is set as two inputs of the selector 44, and these two inputs are selected based on the LSB logic of the coefficient h2 supplied via the D-FF 45, When the LSB logic of h2 is “0”, the output of the D-FF 36 is selected and selected as the selected output f through the D-FF 46, and when the LSB logic is “1”, the output of the D-FF 39 is selected. To select output via the D-FF 46.
[0032]
The output c of the D-FF 38 becomes the J input of the JK-FF 47, the output e of the D-FF 40 becomes the K input of the JK-FF 47, and the positive phase output Q of the JK-FF 47 becomes the select pulse g. The output d of the D-FF 43 is the J input of the JK-FF 48, the output f of the D-FF 46 is the K input of the JK-FF 48, and the positive phase output Q of the JK-FF 48 is the select pulse h.
[0033]
In this way, for example, in the odd-dot processing block 27Ro in the R black frame processing block 27R, the select pulse is offset by 1/2 clk stage when the coefficients are even and odd. As a result, when even numbers are set to the coefficient h1 and the coefficient h2, the select pulse g and the select pulse h are offset by 1/2 clk stages, and the relationship between the video signals R1 and R2 and the select pulse is shown in FIG. As shown in the timing chart of FIG. Further, when odd numbers are set for the coefficient h1 and the coefficient h2, the result is as shown in the timing chart of FIG.
[0034]
The V counter 32 operates using the vertical synchronization signal vd as a reset pulse and the horizontal synchronization signal hd as a clock. Specifically, similarly to the processing in the H direction, the comparators 49 and 50 compare the count value of the V counter 32 with the coefficient (v1 or v2). At this time, the comparators 49 and 50 output “1” if the values are the same, and output “0” otherwise.
[0035]
The comparison results of the comparators 49 and 50 are latched by the D-FFs 51 and 52. The outputs i and j of these D-FFs 51 and 52 become the J and K inputs of the JK-FF 53, respectively. The positive phase output Q of the JK-FF 53 becomes the select pulse k in the black frame display range in the V direction. The timing relationship of the select pulse k in the V direction is shown in the timing chart of FIG.
[0036]
The H direction select pulses g and h generated in this way are separately input to the decoders 54 and 55, and the V direction select pulse k is input to the decoders 54 and 55 in common. As shown in the timing chart of FIG. 12, the decoder 54 outputs “0” when both the select pulse g in the H direction and the select pulse k in the V direction are “1”, and when either is “0”. Outputs “1”. That is, it operates as a NAND gate. The same applies to the decoder 55.
[0037]
The decode output of the decoder 54 passes through the D-FF 56 and becomes a select pulse for even dots. The decode output of the decoder 55 becomes a select pulse for odd dots via the D-FF 57. This select pulse for even / odd dots is input to the selectors 29e and 29o shown in FIG. 5 to select input data (video signal) and black frame black level data (coefficient fb).
[0038]
As described above, the black frame processing block 27R, the last stage of the driver IC (signal processing system) 13 that performs various image quality adjustments such as gain adjustment, brightness adjustment, gamma adjustment, and limit adjustment in the drive system of the LCD display system. By arranging 27G and 27B, when the number of pixels calculated from the effective period of the video signal to be displayed is less than the number of pixels of the LCD panel, the display level of the blanking period displayed on the LCD panel is set. Regardless of the level of image quality adjustment, it can always be fixed at an arbitrary level (in this example, the black level).
[0039]
Since the timing generator 28 is used to output the select pulse at an arbitrary timing, a black frame can be displayed in units of one dot regardless of the input format of the video signal. In particular, in the case of a parallel processing system, select pulses are generated separately for black frame processing blocks (in this example, even / odd two systems) that exist in parallel, so that even in a parallel processing system, one dot unit. That is, the display range of the black frame can be controlled by the master black period of the system.
[0040]
Furthermore, since the timing generator is operated only by the horizontal synchronization signal hd, the vertical synchronization signal vd, and the clock clk, signal processing independent of a specific system can be performed. Further, since all the coefficients are set from the outside of the signal processing block (driver IC), the user can arbitrarily set the display range and display level of the black frame. In addition, since the display range of the black frame can be arbitrarily changed, the overscan percentage can be changed without changing the roundness ratio when displaying a video signal of a television format such as NTSC, PAL, or HDTV.
[0041]
In the above embodiment, the case where the present invention is applied to an LCD display system that processes digital data demultiplexed 1: 2 has been described. However, the ratio is not limited to 1: 2.
[0042]
【The invention's effect】
As described above, according to the present invention, there is a signal processing system that performs various image quality adjustments on an input video signal, and driving that drives an LCD panel based on the video signal that has passed through this signal processing system. In the circuit, when the number of pixels calculated from the effective period of the video signal is less than the number of pixels of the LCD panel, a frame processing block for fixing the display level of the blanking period displayed on the LCD panel to a certain level is signaled. Since the display level of the frame is not affected by the result of any other signal processing because it is arranged at the last stage of the processing system, the display level of the frame can always be fixed at a constant level.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a basic configuration of an LCD display system according to the present invention.
FIG. 2 is a block diagram showing an example of a configuration of a driver IC according to the present invention.
FIG. 3 is an operation explanatory diagram according to the present invention.
FIG. 4 is a waveform diagram showing a relationship between horizontal synchronization signal vd and vertical synchronization signal vd and coefficients h1, h2, v1, and v2.
FIG. 5 is a block diagram illustrating an example of a configuration of a black frame processing block.
FIG. 6 is a block diagram illustrating an example of a configuration of a timing generator.
FIG. 7 is a timing chart showing the relationship between a clock and data.
FIG. 8 is a timing chart for explaining the operation of the timing generator;
FIG. 9 is a timing chart for explaining an operation of generating a select pulse when coefficients h1 and h2 are even.
FIG. 10 is a timing chart for explaining an operation of generating a select pulse when coefficients h1 and h2 are odd numbers.
FIG. 11 is a timing chart for explaining an operation of generating a select pulse in the V direction.
FIG. 12 is a timing chart for explaining the operation of generating select pulses for the entire H and V.
FIG. 13 is a diagram showing a relationship between LCD panels having different formats and black frame display areas.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11,28 ... Timing generator, 13 ... Driver IC, 16R, 16G, 16B ... LCD panel, 21 ... Serial I / F, 27R, 27G, 27B ... Black frame processing block, 29e, 29o, 41, 44 ... Selector, 31 ... H counter, 32... V counter, 33, 34, 49, 50... Comparator, 54, 55.

Claims (4)

A liquid crystal display device having a signal processing system for performing various image quality adjustments on an input video signal, and driving a display unit based on the video signal that has passed through the signal processing system,
When the number of pixels calculated from the effective period of the video signal is less than the number of pixels of the display unit, the display level of the blanking period displayed on the display unit is fixed to a constant level, and the frame display range data a frame processing block for outputting switching between the video signal and the frame display level signals possess in the last stage of the signal processing system in response to a select signal generated by 1 dot units based on,
N processing systems in which the video signal is demultiplexed 1: n (n is an integer of 2 or more), and the signal processing system performs parallel processing using a 1 / n divided clock of a master clock. The frame processing block performs a switching process according to the select signal given to each of the n processing systems,
The select signal includes a decoding value of each count value of the H counter that performs a counting operation with a 1 / n frequency-divided clock of a master clock and a V counter that uses a vertical synchronizing signal as a reset pulse, and the frame. It is generated based on the comparison result with the coefficient data indicating the display range, and the comparison result between the count value of the H counter and the upper bit of the coefficient data is set to the 1 / n by the value of the lower bit of the coefficient data. A liquid crystal display device characterized by being output with an offset corresponding to one stage of a divided clock . It said frame display range data and the frame display level signal, the liquid crystal display device according to claim 1, wherein the set from an external driving circuit. A driving circuit for a liquid crystal display device having a signal processing system for performing various image quality adjustments on an input video signal, and driving a display unit based on the video signal that has passed through the signal processing system;
When the number of pixels calculated from the effective period of the video signal is less than the number of pixels of the display unit, the display level of the blanking period displayed on the display unit is fixed to a constant level, and the frame display range data a frame processing block for outputting switching between the video signal and the frame display level signals possess in the last stage of the signal processing system in response to a select signal generated by 1 dot units based on,
N processing systems in which the video signal is demultiplexed 1: n (n is an integer of 2 or more), and the signal processing system performs parallel processing using a 1 / n divided clock of a master clock. The frame processing block performs a switching process according to the select signal given to each of the n processing systems,
The select signal includes a decoding value of each count value of the H counter that performs a counting operation with a 1 / n frequency-divided clock of a master clock and a V counter that uses a vertical synchronizing signal as a reset pulse, and the frame. It is generated based on the comparison result with the coefficient data indicating the display range, and the comparison result between the count value of the H counter and the upper bit of the coefficient data is set to the 1 / n by the value of the lower bit of the coefficient data. A drive circuit for a liquid crystal display device, characterized in that an output corresponding to one stage of a divided clock is added and output . The drive circuit of the liquid crystal display device according to claim 3, wherein the frame display range data and the frame display level signal are set from outside the drive circuit.

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