JP3987652B2 - Image processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image processing apparatus applied to a scanner, a facsimile, a copying machine, and the like, and more particularly to a high-speed image processing technique.
[0002]
[Prior art]
In recent years, the speed of digital copying machines and scanners has been increased. In order to achieve high speed, it is necessary to read a document at high speed and perform high-speed image processing on the image data. However, if the clock is simply increased, the reliability of the circuit due to lack of circuit heat and operating margins is reduced. Technical issues such as lack and occurrence of radio interference increase.
[0003]
Therefore, conventionally, a method for dealing with high-speed processing without increasing the clock speed has been considered. For example, in Japanese Patent Laid-Open No. 6-98165, image data for one page is divided into a plurality of blocks in the main scanning direction to form a plurality of blocks, and parallel processing is performed for each of these blocks. Thus, a technique has been proposed in which image data once divided into blocks is returned to line units so that image processing across blocks can be easily performed.
[0004]
[Problems to be solved by the invention]
In the conventional example, a line is divided into blocks, and each block is processed with the same synchronization signal. Therefore, multiple types of image processing cannot be performed in parallel, and there is a limit to speeding up multiple types of image processing.
[0005]
Therefore, an object of the present invention is to provide an image processing apparatus capable of performing a plurality of types of image processing at high speed.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, an invention according to claim 1 is an image reading apparatus that divides one line of image data into arbitrary n blocks and transfers each image data in synchronization with different synchronization signals. In the image processing apparatus that receives the image data and performs predetermined image processing on the image data, the first image processing unit that performs image processing using a separate synchronization signal for each block and the block are combined in units of lines. , A second image processing unit that performs image processing using a synchronization signal having a period of n times,
A third image processing unit that performs image processing using the synchronization signal that is divided again for each block and returned to the original cycle;
It is provided with.
[0007]
In order to achieve the above object, the invention according to claim 2 is the invention according to claim 1,
A one-line unit for parallelizing image data after image processing and dropping the processing clock at the same line period and transferring it to the next stage is provided.
[0008]
In order to achieve the above object, the invention according to claim 3 is the invention according to claim 1,
An image composition processing unit that performs composition processing of image data from an image generation unit that generates image data and image data processed by the image processing unit is provided.
[0009]
In order to achieve the above object, the invention described in claim 4 is the invention described in claim 3,
It is characterized by having an image composition processing unit after parallelizing the image data after image processing and dropping the processing clock in the same line period.
[0010]
In order to achieve the above object, the invention according to claim 5 is the invention according to claim 3,
The image generation unit includes an input interface for inputting image data.
[0011]
In order to achieve the above object, the invention according to claim 6 is the invention according to claim 3 , further comprising a data bus for connecting the image generation unit and the image composition processing unit, wherein the data bus is bidirectional. It is a data bus .
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the accompanying drawings.
FIG. 1 is a block diagram of an image processing apparatus showing a first embodiment of the present invention.
An image processing apparatus including a speed conversion unit 101 and an image processing unit 102 is provided at the subsequent stage of the image processing apparatus 100.
The speed conversion unit 101 includes a FIFO (first in first out) memory 111, a first control circuit 112, a timing generation unit 113, a second control circuit 114, and a LIFO (last in first out) memory 115. Have
[0013]
FIG. 6 is an explanatory diagram showing the operation of the FIFO memory, and FIG. 7 is an explanatory diagram showing the operation of the LIFO memory.
As shown in these figures, the FIFO memory 111 is a memory that outputs data in the input order, and the LIFO memory 115 is a memory that outputs data in reverse order from the last.
The image processing unit 102 includes a pair of first image processing units (1) 121, a pair of second image processing units (2) 122, and a pair of third image processing units (3) 123.
In this embodiment, an example is shown in which one line is divided into two blocks, block 1 (first half) and block 2 (second half).
[0014]
FIG. 3 is a diagram showing data timing from the image reading apparatus, and FIG. 4 is a diagram showing data timing after speed conversion.
First, data timing from the image reading apparatus will be described. In FIG. 3, the length of one line is 7500 pixels, and the block 1 and the block 2 are divided every 3750 pixels. The image data and line synchronization signal of each block are received. A frame gate signal representing the length of one page is common to the blocks.
In this embodiment, the block 2 is arranged from the rear end of the image data due to the convenience of the image reading apparatus 100 (from 7500 pixels to 3751 pixels in order).
[0015]
Image data and a synchronization signal are input from the image reading apparatus 100 to the speed conversion unit 101 of the image processing apparatus for each of the blocks 1 and 2.
Block 1 data is input to the FIFO memory 111 and block 2 data is input to the LIFO memory 115 in synchronization with the input synchronization signal. The FIFO memory 111 and the LIFO memory 115 have a memory amount corresponding to the block size (in this example, half of one line).
[0016]
As shown in FIG. 4, the data of block 1 is read from the FIFO memory 111 in synchronization with the line synchronization signal generated by the timing generation unit 113 inside the speed conversion unit 101. Similarly, the data of block 2 is read from the LIFO memory 115 by the line synchronization signal generated by the timing generator 113. Since the data in block 2 is read in the reverse order, it cannot be read out until after the block data has been completely read, so that the output of data for one period of the line synchronization signal is delayed (T1 in FIG. 4). .
[0017]
Further, since it is necessary to read data before writing the next data, the line synchronization signal of block 2 is earlier than the synchronization signal of block 1 (T2 in FIG. 4). Therefore, in the image processing 1, the line synchronization signal and the data timing are in an asynchronous state for each block. Since the first image processing unit (1) 121 is a block that performs independent processing in units of blocks, there is no problem.
[0018]
FIG. 5 is a diagram showing data timing in the second image processing unit.
Since the second image processing unit (2) 122 is a process for each line like the enlargement process in the conventional example, the block 1 and the block 2 are combined into one line as shown in FIG. At this time, one period is doubled so that the operation clock remains the same (T3 in FIG. 5), and parallel operation is performed on even lines and odd lines.
[0019]
FIG. 8 is a diagram showing data timing in the third image processing unit.
The image processing in the third image processing unit (3) 123 is divided into blocks 1 and 2 as shown in FIG. Normally, data is transferred to the writing unit after image processing.
[0020]
FIG. 2 is a block diagram of an image processing apparatus showing a second embodiment of the present invention.
An image processing apparatus including a speed conversion unit 101 and an image processing unit 102 is provided at the subsequent stage of the image processing apparatus 100.
The speed conversion unit 101 includes a FIFO memory 111, a first control circuit 112, a timing generation unit 113, a second control circuit 114, and a LIFO memory 115.
The image processing unit 102 includes a pair of first image processing units (1) 121, a pair of second image processing units (2) 122, and a pair of third image processing units (3) 123.
In addition, the image processing apparatus according to the present embodiment includes a one-line forming unit 131 subsequent to the image processing unit 102.
[0021]
As described above, data is normally transferred to the writing unit after image processing. However, as in the second embodiment shown in FIG. 2, a single line is formed by the single line forming unit 131 and data is output. There is also. The 1-line unit 131 performs a process of outputting all the processed block 1 and block 2 data as one line within the line synchronization signal 1 period for each block.
[0022]
FIG. 9 is a diagram showing a 1-pixel bit configuration during image processing.
In the present embodiment, as shown in FIG. 9, image processing is performed at an 8-bit quantization level. That is, the density can be expressed from 0 to 255.
[0023]
FIG. 10 is a diagram showing a one-pixel bit configuration after image processing [FIG. 10 (a)] and parallelization [FIG. 10 (b)].
Image data after image processing is usually further quantized and the number of bits is reduced. In this case, as shown in FIG. 10 (a), if it becomes 4 bits, as shown in FIG. 10 (b), if this is transferred in parallel by an 8-bit bus, the line synchronization signal is transmitted with the same clock. The period can be ½. If the blocks 1 and 2 are combined in this state, one line can be formed without changing the line synchronization signal period.
[0024]
The image processing apparatus according to the present embodiment includes a FIFO memory 111, a first control circuit 112, a timing generation unit 113, a second control circuit 114, a speed conversion unit 101 having a LIFO memory 115, and a pair of first images. An image processing unit 102 having a processing unit (1) 121, a pair of second image processing units (2) 122, a pair of third image processing units (3) 123, and one line following the image processing unit 102 The control unit 131 is provided.
Then, a separate synchronization signal is used for each divided block, and a timing shift (skew in FIG. 3) at the time of transfer is absorbed by the FIFO memory 111 and the LIFO memory 115, and then image processing is performed.
Therefore, a plurality of types of image processing can be performed at high speed.
[0025]
FIG. 11 is a block diagram of an image processing apparatus showing the third embodiment.
The fourth image processing unit (4) 124 and the fifth image processing unit (5) 125 receive the synchronization signal from the third image processing unit (3) 123 as they are, and receive the first, second, and third images. The image processing unit performs processing different from the processing units 121, 122, and 123. The sixth image processing unit (6) 126 synthesizes the image data sent from the image generation units 141-1 and 141-2 with the image data processed by the fifth image processing unit (5) 125. Each of the block 1 and the block 2 has an image processing unit 126-1 and 126-2, and outputs image data in synchronization with a synchronization signal from the output I / Fs 142-1 and 142-2, respectively.
[0026]
FIG. 17 is a diagram illustrating an image composition image.
When an image to be combined for easy understanding (output image from the fifth image processing unit (5) 125) 200 is a blank sheet (digital value 0), and the image 201 to be combined is a black portion (digital value 255), A composite output image 202 as shown in the figure is obtained.
[0027]
18 is a diagram showing an image processing unit output synchronization signal and data timing, FIG. 19 is a diagram showing sub-scanning direction synthesis timing, and FIG. 20 is a diagram showing main scanning direction synthesis timing. In these figures, S1 is a frame gate signal, S2 is a block 1 line synchronization signal, S3 is a block 2 line synchronization signal, D1 is block 1 image data, D2 is block 2 image data, D3 is block 1 composite image data, D4 Indicates image data after block 1 synthesis (see FIG. 11).
The synthesis timing will be described with reference to FIGS. Since the block 1 is the first half of the pre-combination image and the block 2 is the second half. In this example, only the first half image is synthesized.
[0028]
FIG. 18 shows the output timing of the fifth image processing unit (5) 125. In this example, the frame gate signal changes in synchronization with the falling edge of the line synchronization signal of block 1 in all image processing units. The timing of the block 2 and the block 1 is such that the rear end of the data of one line of the block 1 and the front end of the first line of the block 2 are connected as shown in the figure. In this way, it is easy to form one line in the second image processing unit (2) 122. Since this operation is not directly related to the present invention, detailed description thereof is omitted.
[0029]
The data from the image generation unit 141-1 is output at a predetermined timing in synchronization with the block 1 line synchronization signal from the fifth image processing unit (5) 125. This example shows a case where a composite image of 3 pixels × 3 pixels is output from the fourth pixel in the main scanning direction of the first line. As shown in the figure, the block 1 composite image data is output from the 4th pixel of the first line main scanning in succession by three lines 255, 0, and 255, and then 0 is output (FIG. 20). The pixel clock shown in FIG. 20 is a synchronization signal in the main scanning direction.
[0030]
In this example, the larger digital value is output. Therefore, since the synthesized data is repeated three lines as shown in FIG. 19, the output of FIG. 17 is obtained. The method of generating the composite image is not limited to a method of simply outputting the larger digital value. For the image to be synthesized, data is prepared in advance in the memory of the image generation unit 141.
[0031]
FIG. 12 is a block diagram of an image processing apparatus showing the fourth embodiment.
In this example, the n-divided block is applied to one line by the one line unit 143 and output to the output I / F 142. Since the image synthesizing unit is placed after the one-line forming unit 143, the number of the image generating unit 141 becomes one, and the cost can be reduced. The synthesis timing is the same as in the example of FIG.
[0032]
FIG. 13 is a block diagram of an image processing apparatus showing the fifth embodiment. FIG. 14 is a block diagram of an image processing apparatus showing the sixth embodiment.
These examples show that a composite image is input to the image generation unit 141 from the outside of the image processing apparatus via the input I / F 144.
The example of FIG. 14 is obtained by reducing the amount of wiring by making the data buses of the image generation unit 141 and the image composition processing unit 126 bidirectional with respect to the example of FIG. When the image processing apparatus is integrated into an LSI and the image generation unit 141 and the other are integrated into separate LSIs, the wiring area between the LSIs can be reduced, and the cost can be reduced.
Specifically, in the example of FIG. 13, the I / F of the image generation unit 141 requires signal lines indicated by S4, S5, S6, and S7, but in the example of FIG. 14, only S8 and S9.
[0033]
FIG. 15 is a block diagram illustrating an example of bidirectional control of the image generation unit.
The image generation unit 141 is bidirectionally controlled by the bidirectional buffer unit 151. The bi-directional buffer control signal is controlled by an external controller (not shown).
[0034]
FIG. 16 is a block diagram of the image generation unit.
The image data is stored in the memory unit 165, and an external controller (not shown) outputs the in-memory data to the image processing apparatus in synchronization with the synchronization signal S11 via the command I / F 166 when outputting the image. The control block 164 and the image data bidirectional control block 161 are controlled. The output image data is input to the image composition processing unit 126 through the bidirectional buffer unit 151 shown in FIG. 15, and is synthesized with the image data after one line. Conversely, image data (input data) from the input I / F 144 is input to the image composition processing unit 126 in synchronization with the input I / F synchronization signal, and is transmitted from the image composition unit to the image generation unit 141 via the bidirectional buffer. Entered. Reference numeral 162 denotes an input I / F, and 163 denotes an output I / F.
[0035]
【The invention's effect】
According to the first aspect of the present invention, image processing is performed using a separate synchronization signal for each block, and then the blocks are synthesized in units of lines, and image processing is performed using a synchronization signal having a period of n times. Finally, by dividing the line for each block again and performing image processing using the synchronization signal returned to the original cycle, parallel processing suitable for each image processing becomes possible, realizing high-speed image processing it can.
[0036]
According to the second aspect of the invention, in addition to the above, the image data after image processing is parallelized, the processing clock is dropped at the same line period and transferred to the next stage, so that the next stage considers block division. One-line processing can be performed, and control is simplified. Further, since the clock frequency is lowered, it becomes difficult to generate unnecessary radiation noise.
[0037]
According to the third aspect of the present invention, the image data registered in the image generation unit at an arbitrary position can be combined with an image divided into blocks.
[0038]
According to the fourth aspect of the present invention, the number of image generation units can be made one, and the cost can be reduced.
[0039]
According to the fifth aspect of the present invention, it is possible to perform registration by registering an arbitrary image in the image generation unit at an arbitrary timing.
[0040]
According to the sixth aspect of the present invention, when the image generating unit is a separate circuit block from the other image processing apparatus, the number of wirings can be reduced and the cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram of an image processing apparatus showing a first embodiment of the present invention.
FIG. 2 is a block diagram of an image processing apparatus showing a second embodiment of the present invention.
FIG. 3 is a diagram illustrating data timing from the image reading apparatus.
FIG. 4 is a diagram showing data timing after speed conversion.
FIG. 5 is a diagram illustrating data timing in a second image processing unit.
FIG. 6 is an explanatory diagram showing the operation of the FIFO memory.
FIG. 7 is an explanatory diagram showing an operation of the LIFO memory.
FIG. 8 is a diagram illustrating data timing in a third image processing unit.
FIG. 9 is a diagram illustrating a 1-pixel bit configuration during image processing.
FIG. 10 is a diagram illustrating a 1-pixel bit configuration and parallelization after image processing.
FIG. 11 is a block diagram of an image processing apparatus showing a third embodiment of the present invention.
FIG. 12 is a block diagram of an image processing apparatus showing a fourth embodiment of the present invention.
FIG. 13 is a block diagram of an image processing apparatus showing a fifth embodiment of the present invention.
FIG. 14 is a block diagram of an image processing apparatus showing a sixth embodiment of the present invention.
FIG. 15 is a block diagram illustrating an example of bidirectional control of an image generation unit.
FIG. 16 is a block diagram of an image generation unit.
FIG. 17 is a diagram illustrating an image composition image.
FIG. 18 is a diagram illustrating an image processing unit output synchronization signal and data timing.
FIG. 19 is a diagram illustrating sub-scanning direction synthesis timing.
FIG. 20 is a diagram illustrating main scanning direction synthesis timing.
[Explanation of symbols]
100 Image Reading Device 101 Speed Conversion Unit 102 Image Processing Unit 111 FIFO Memory 112 Control Circuit 113 Timing Generation Unit 114 Control Circuit 115 LIFO Memory 121 First Image Processing Unit 122 Second Image Processing Unit 123 Third Image Processing Unit 124 Fourth image processing unit 125 Fifth image processing unit 126 Sixth image processing unit 126-1 and 126-2 Image composition processing unit 131 One line forming unit 141 Image generating unit 142 Output I / F
143 1-line unit 144 Input I / F

Claims (6)

One line of image data is divided into arbitrary n blocks, image data is received from an image reading apparatus that transfers each image data in synchronization with different synchronization signals, and predetermined image processing is performed on the image data. In the image processing apparatus,
A first image processing unit that performs image processing using a separate synchronization signal for each block;
A second image processing unit that synthesizes the blocks in units of lines and performs image processing using a synchronization signal having a period of n times;
A third image processing unit that performs image processing using the synchronization signal that is divided again for each block and returned to the original cycle;
An image processing apparatus comprising: In claim 1,
An image processing apparatus comprising a one-line unit that parallelizes image data after image processing, drops a processing clock at the same line period, and transfers the image data to the next stage. In claim 1,
An image processing apparatus comprising: an image composition processing unit that performs composition processing of image data from an image generation unit that generates image data and image data processed by the image processing unit. In claim 3,
An image processing apparatus comprising an image composition processing unit after parallelizing image data after image processing and dropping a processing clock in the same line cycle. In claim 3,
An image processing apparatus comprising an input interface for inputting image data to an image generation unit. In claim 3,
A data bus connecting the image generation unit and the image composition processing unit is provided,
An image processing apparatus , wherein the data bus is a bidirectional data bus .

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