JP3980211B2 - Locally controlled FET data switch for semiconductor memory cards - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is directed to a method and structure for improving the control of isolated data switches for DRAM memory cards and other similar electronic assemblies. By providing a means for the memory chip itself to control the data flow switch, the time required for control is reduced and faster operation is possible. In addition, the use of a separation switch becomes transparent to the system and is easy to use. In addition, connections and electronic circuitry for controlling the switches are removed from the system device controller. This method is applicable to any set of electronic assemblies having a common bus connection.
[0002]
[Prior art]
In a computer memory system, it is common to place a memory chip (DRAM, or dynamic random access memory) on a small memory card (SIMM or DIMM, single or dual inline memory module). Design technology. In the case of a DIMM, the data pins of the DRAM device are plugged into the card edge with printed circuit card wiring. Several DRAMs on a DIMM may share a single data pin, and a particular DRAM is selected by a unique signal (chip select) from the memory controller. In addition, data pins from several DIMMs can be connected to each other, again with the memory controller selecting only one of the DIMMs for reading and writing data at a given time. A set of common RAMs that are accessed simultaneously is referred to as a memory rank or rank. As a result, the data network from the memory controller to the DRAM can have multiple DRAM chips all capable of reading and writing data. Such multiple loads result in large capacitance on the data bus, limiting the speed at which the data bus can be electrically asserted to send and receive data to and from any particular rank of memory.
[0003]
Proposals have been made to reduce the capacitance of the data bus by introducing a switch on the data connection between the DRAM device on the DIMM and the card edge connection. If such a switch is placed close to the card edge to allow a fast transition from a conducting state (low impedance) to a non-conducting state (high impedance), or if the capacitance of the switch device is a DRAM or print card on a DIMM If it is smaller than the wiring, the data bus speed problem may become significant. One possibility is a CMOS FET with very little power flowing, capable of switching at speeds of less than 1 nanosecond, having an on-impedance of 10 ohms or less, and an input capacitance of less than 5 picofarads (pF). (Complementary metal oxide semiconductor field effect transistor) is to use the device. This is a reasonable switch. The problem is that in order to turn this device on and off, all FETs in the system must pass a high speed signal, so each DIMM that is currently using the data bus is electrically connected However, this signal must be controlled with accurate timing so that other unselected DIMMs on the same bus are not connected. One suggestion is that the memory controller provides control over the FET switch, which is a very difficult problem when the data bus speed is high. Another suggestion is to place a separate FET control chip on the DIMM to control the FET. This is also complicated in that the memory controller must control this chip, adding additional components on the DIMM, increasing costs.
[0004]
Therefore, it would be desirable to find a way to control the operation of the FET data flow switch in a high speed memory data bus without using additional controllers or global control circuitry. The manner in which this can be achieved is described in the present invention.
[0005]
[Problems to be solved by the invention]
Thus, the broad aspect of the present invention allows multiple memory cards (or DIMMs) to be used on each memory card (or DIMM) by using FET data flow switches controlled by the memory device itself. To improve the speed of the connected memory data bus.
[0006]
In particular, consider the application of this technology in the case of a synchronous DRAM with a clock doubled data bus (SDRAM-DDR), but this teaching covers any electronic bus connecting multiple electronic devices. I want you to understand.
[0007]
[Means for Solving the Problems]
An object of the present invention includes a printed circuit card, a plurality of electronic devices, each of the plurality of electronic devices, arranged to communicate with said printed circuit card electrically via a corresponding switch the A plurality of electronic devices and an enable line for each of the plurality of electronic devices that provides an electrical connection between each of the plurality of electronic devices and the corresponding switch to provide an enable signal to the switch; Achieved by a structure comprising
[0008]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows the latest prior art in the design of high speed SDRAM-DDR DIMMs. There are many SDRAM-DDR devices 100 on the printed circuit card 110. The signal on the card edge 120 is adjusted so that the maximum distance between the data connection 140 between the DRAM and the card edge is as short as possible. In the design currently presented to the JEDEC standards committee, the largest data line is about 15 mm. One or two DRAMs on each DIMM can share a data line. Other DIMMs having more DRAM devices can be composed of 4 or even 8 DRAMs sharing one data line. These DIMMs increase the length of the printed circuit card between the DRAM and the DIMM card edge.
[0009]
FIG. 2 shows how the data connection 140 of FIG. 1 can be connected via the switch device 210. The connection extends from RAM 250 to the switch by print card wiring 240 and then from the switch to the card edge via print card wiring 220. In this case, the switch device 210 includes a total of four switches, one for each of the four data lines 240 from the RAM. Switch 210 is rendered conductive or non-conductive by an enable signal. The enable signals for the nine switch devices on the printed circuit card 270 are connected to each other via the printed circuit card line 260 and are connected to the card edge for control by a memory controller (not shown). This method is well known in the art, for example, the switch device is a CMOS NFET. In this case, the enable line 260 is connected to the gate of the NFET and is grounded to disable the FET, and is set to the FET operating voltage VCC to enable the FET, ie, conduct the FET. Alternatively, the switch enable line 260 can be controlled by an additional controller located on the memory card 270. Both techniques have problems associated with reducing the switching time of the device 210 because they use an external controller and a large amount of printed circuit wiring. These techniques also have stringent timing requirements for the controller logic when enabling / disabling the switch fast enough to allow high speed data bus access.
[0010]
FIG. 3 illustrates the present invention. In this case, the FET enable line 310 is connected directly to the RAM 330 and all other connections are the same as in FIG. In this case, line 310 is also connected to resistor 320 and then to ground. This is useful when multiple RAMs share a connection to the FET and only one RAM is selected at a time to enable the FET. This well-known type of connection is called “dot-or” and only one device needs to assert the line (drive the line to the FET or RAM supply voltage VCC) to switch the line. Resistor R must be large enough (approximately 50-100 ohms) to quickly restore the switch enable line to ground when no device asserts the line. The resistance can be further increased, and when the enable line is deasserted, the switching speed can be increased when the RAM first drives the line to ground and then releases the line.
[0011]
Alternatively, an inverter can be placed in the switch device, enabling the device by asserting an enable signal to ground, and disabling the device at the supply voltage. This option is highly flexible in that the RAM and switch voltages can be separated. It is also possible to form complementary pass gates with more complex switches, ie parallel PFETs and NFETs. It is preferable if all switch devices 310 on the memory card can be enabled simultaneously, since all memory chips of the same rank on the memory card are accessed.
[0012]
FIG. 4 shows how the multiple memory cards of FIG. 3 can be connected. The number of signals coming out of the memory card is the same as in FIG. 1, that is, the switch card of FIG. 3 is used instead of the conventional memory card of FIG. 1 without changing the memory controller or DIMM connector. Note that you can. This is important for product backward compatibility. Since only one of the four cards (410, 420, 430, 440) is enabled at any given time, the data bus load is reduced and the memory card of FIG. Thus, the operation can be performed at a higher speed than when the memory card of FIG. 4 is replaced.
[0013]
The present invention requires the memory device 330 to provide a new signal, the data FET enable line 310 signal. This signal is preferably driven before or simultaneously with data being read from or written to the RAM. Therefore, the RAM preferably knows that a read / write operation should be performed before read or write data appears on the bus. All RAM devices know in advance about the read operation. This is because the read data must first be retrieved from RAM before it can be driven onto the data bus. However, only recently has a high-speed RAM been created that has a write latency, i.e., a delay between when the RAM is instructed to enter a write mode and when write data appears on the pins of the RAM. For the present invention to work, the write latency must be equal to or longer than the time required for the RAM to recognize the write command and assert the FET enable signal. The present invention is made possible by newly introducing a write latency in the design of a high-speed RAM.
[0014]
In summary, a method has been described for reducing the capacitance of a high speed memory data bus by introducing a switch and a means for controlling the switch. The switch is placed on the data connection between the DRAM device on the DIMM and the card edge connection. If the switch should allow the fastest communication, it must switch quickly at the same time or less than about 1 nanosecond. It is also best if the switch is optional, i.e. the memory controller does not need to know about the switch to properly access the memory device. If the memory device, i.e. the RAM itself, controls the operation of the switch, then both high speed operation and optional use requirements are met.
[0015]
In summary, the following matters are disclosed regarding the configuration of the present invention.
[0016]
(1) One printed circuit card,
A plurality of electronic devices, each of the plurality of electronic devices, said corresponding plurality of electronic devices arranged to communicate with said printed circuit card electrically through the switch, and the plurality of electronic A structure including an enable line for each of the plurality of electronic devices that provides an electrical connection between each of the devices and the corresponding switch to provide an enable signal to the switch.
(2) The structure according to (1), wherein the electronic device is a DRAM.
(3) The structure according to (1), wherein the switch is a circuit including an FET.
(4) The structure according to (1), including a resistor between the enable line and ground.
(5) the electronic device, by enabling the enable line, to provide a means for enabling to and disabling the switch between conductive and non-conductive states, the structure according to (1).
(6) The structure according to (1), wherein the switch includes an inverter.
(7) The electronic device is connected to the enable line to the ground to enable the switch includes means for disabling said switch and connects said enable line to a power source, the structure of (6) .
(8) The structure according to (1), wherein a plurality of printed circuit cards are electrically interconnected.
(9) and the semiconductor switch, controlling the one or more semiconductor devices, said switch and said one or printed wiring card including a plurality of devices, and the switching operation of said switch, means for the semiconductor device The structure includes: a common signal shared between the switch and the semiconductor device .
(10) The structure according to (9), wherein the printed semiconductor switch is a field effect transistor and the semiconductor device is a DRAM.
(11) The structure according to (9), wherein the means has a “dot-or” logic configuration.
[Brief description of the drawings]
FIG. 1 is a diagram showing a component arrangement of a DRAM memory device on a prior art memory card (DIMM).
FIG. 2 FET control signals are connected to the card edge and must be supplied from a controller (not shown). FIG. 2 illustrates the DIMM of FIG. 1 with a data flow switch device (FET) used to connect or disconnect data signals from prior art RAM to the DIMM card edge.
FIG. 3 is a diagram showing a DIMM similar to FIG. 2 except that an FET control signal is connected to a DRAM connected to the FET.
FIG. 4 is a diagram of a set of DIMMs similar to FIG. 3 on a common data bus.
[Explanation of symbols]
100 SDRAM-DDR device 110 Printed circuit card 120 Card edge 140 Data connection 210 Switch device 220 Print card wiring 240 Data line 260 Enable line 270 Memory card 310 FET enable line 320 Resistor 330 Memory device 410 Card 420 Card 430 Card 440 cards

Claims (7)

One printed circuit card,
A plurality of electronic devices, each of the plurality of electronic devices arranged to electrically communicate with the printed circuit card via a corresponding switch;
An enable line providing electrical connection between each of the plurality of electronic devices and the corresponding switch;
A structure for each of the plurality of electronic devices to provide an enable signal to the corresponding switch via the enable line to control a conductive state or a non-conductive state of the switch.   The structure of claim 1, wherein the electronic device is a DRAM.   The structure of claim 1, wherein the switch is a circuit including a FET.   The structure of claim 1 including a resistor between the enable line and ground.   The structure of claim 1, wherein the switch comprises an inverter. 6. The structure of claim 5 , wherein the electronic device includes means for connecting the enable line to ground to enable the switch and connecting the enable line to a power source to disable the switch.   The structure of claim 1, wherein a plurality of the printed circuit cards are electrically interconnected.

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